clk-fsd.c 90 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
  4. * https://www.samsung.com
  5. * Copyright (c) 2017-2022 Tesla, Inc.
  6. * https://www.tesla.com
  7. *
  8. * Common Clock Framework support for FSD SoC.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <dt-bindings/clock/fsd-clk.h>
  19. #include "clk.h"
  20. #include "clk-exynos-arm64.h"
  21. /* Register Offset definitions for CMU_CMU (0x11c10000) */
  22. #define PLL_LOCKTIME_PLL_SHARED0 0x0
  23. #define PLL_LOCKTIME_PLL_SHARED1 0x4
  24. #define PLL_LOCKTIME_PLL_SHARED2 0x8
  25. #define PLL_LOCKTIME_PLL_SHARED3 0xc
  26. #define PLL_CON0_PLL_SHARED0 0x100
  27. #define PLL_CON0_PLL_SHARED1 0x120
  28. #define PLL_CON0_PLL_SHARED2 0x140
  29. #define PLL_CON0_PLL_SHARED3 0x160
  30. #define MUX_CMU_CIS0_CLKMUX 0x1000
  31. #define MUX_CMU_CIS1_CLKMUX 0x1004
  32. #define MUX_CMU_CIS2_CLKMUX 0x1008
  33. #define MUX_CMU_CPUCL_SWITCHMUX 0x100c
  34. #define MUX_CMU_FSYS1_ACLK_MUX 0x1014
  35. #define MUX_PLL_SHARED0_MUX 0x1020
  36. #define MUX_PLL_SHARED1_MUX 0x1024
  37. #define DIV_CMU_CIS0_CLK 0x1800
  38. #define DIV_CMU_CIS1_CLK 0x1804
  39. #define DIV_CMU_CIS2_CLK 0x1808
  40. #define DIV_CMU_CMU_ACLK 0x180c
  41. #define DIV_CMU_CPUCL_SWITCH 0x1810
  42. #define DIV_CMU_FSYS0_SHARED0DIV4 0x181c
  43. #define DIV_CMU_FSYS0_SHARED1DIV3 0x1820
  44. #define DIV_CMU_FSYS0_SHARED1DIV4 0x1824
  45. #define DIV_CMU_FSYS1_SHARED0DIV4 0x1828
  46. #define DIV_CMU_FSYS1_SHARED0DIV8 0x182c
  47. #define DIV_CMU_IMEM_ACLK 0x1834
  48. #define DIV_CMU_IMEM_DMACLK 0x1838
  49. #define DIV_CMU_IMEM_TCUCLK 0x183c
  50. #define DIV_CMU_PERIC_SHARED0DIV20 0x1844
  51. #define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848
  52. #define DIV_CMU_PERIC_SHARED1DIV36 0x184c
  53. #define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850
  54. #define DIV_PLL_SHARED0_DIV2 0x1858
  55. #define DIV_PLL_SHARED0_DIV3 0x185c
  56. #define DIV_PLL_SHARED0_DIV4 0x1860
  57. #define DIV_PLL_SHARED0_DIV6 0x1864
  58. #define DIV_PLL_SHARED1_DIV3 0x1868
  59. #define DIV_PLL_SHARED1_DIV36 0x186c
  60. #define DIV_PLL_SHARED1_DIV4 0x1870
  61. #define DIV_PLL_SHARED1_DIV9 0x1874
  62. #define GAT_CMU_CIS0_CLKGATE 0x2000
  63. #define GAT_CMU_CIS1_CLKGATE 0x2004
  64. #define GAT_CMU_CIS2_CLKGATE 0x2008
  65. #define GAT_CMU_CPUCL_SWITCH_GATE 0x200c
  66. #define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018
  67. #define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c
  68. #define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020
  69. #define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024
  70. #define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028
  71. #define GAT_CMU_IMEM_ACLK_GATE 0x2030
  72. #define GAT_CMU_IMEM_DMACLK_GATE 0x2034
  73. #define GAT_CMU_IMEM_TCUCLK_GATE 0x2038
  74. #define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040
  75. #define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044
  76. #define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048
  77. #define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c
  78. #define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054
  79. #define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058
  80. #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
  81. #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
  82. static const unsigned long cmu_clk_regs[] __initconst = {
  83. PLL_LOCKTIME_PLL_SHARED0,
  84. PLL_LOCKTIME_PLL_SHARED1,
  85. PLL_LOCKTIME_PLL_SHARED2,
  86. PLL_LOCKTIME_PLL_SHARED3,
  87. PLL_CON0_PLL_SHARED0,
  88. PLL_CON0_PLL_SHARED1,
  89. PLL_CON0_PLL_SHARED2,
  90. PLL_CON0_PLL_SHARED3,
  91. MUX_CMU_CIS0_CLKMUX,
  92. MUX_CMU_CIS1_CLKMUX,
  93. MUX_CMU_CIS2_CLKMUX,
  94. MUX_CMU_CPUCL_SWITCHMUX,
  95. MUX_CMU_FSYS1_ACLK_MUX,
  96. MUX_PLL_SHARED0_MUX,
  97. MUX_PLL_SHARED1_MUX,
  98. DIV_CMU_CIS0_CLK,
  99. DIV_CMU_CIS1_CLK,
  100. DIV_CMU_CIS2_CLK,
  101. DIV_CMU_CMU_ACLK,
  102. DIV_CMU_CPUCL_SWITCH,
  103. DIV_CMU_FSYS0_SHARED0DIV4,
  104. DIV_CMU_FSYS0_SHARED1DIV3,
  105. DIV_CMU_FSYS0_SHARED1DIV4,
  106. DIV_CMU_FSYS1_SHARED0DIV4,
  107. DIV_CMU_FSYS1_SHARED0DIV8,
  108. DIV_CMU_IMEM_ACLK,
  109. DIV_CMU_IMEM_DMACLK,
  110. DIV_CMU_IMEM_TCUCLK,
  111. DIV_CMU_PERIC_SHARED0DIV20,
  112. DIV_CMU_PERIC_SHARED0DIV3_TBUCLK,
  113. DIV_CMU_PERIC_SHARED1DIV36,
  114. DIV_CMU_PERIC_SHARED1DIV4_DMACLK,
  115. DIV_PLL_SHARED0_DIV2,
  116. DIV_PLL_SHARED0_DIV3,
  117. DIV_PLL_SHARED0_DIV4,
  118. DIV_PLL_SHARED0_DIV6,
  119. DIV_PLL_SHARED1_DIV3,
  120. DIV_PLL_SHARED1_DIV36,
  121. DIV_PLL_SHARED1_DIV4,
  122. DIV_PLL_SHARED1_DIV9,
  123. GAT_CMU_CIS0_CLKGATE,
  124. GAT_CMU_CIS1_CLKGATE,
  125. GAT_CMU_CIS2_CLKGATE,
  126. GAT_CMU_CPUCL_SWITCH_GATE,
  127. GAT_CMU_FSYS0_SHARED0DIV4_GATE,
  128. GAT_CMU_FSYS0_SHARED1DIV4_CLK,
  129. GAT_CMU_FSYS0_SHARED1DIV4_GATE,
  130. GAT_CMU_FSYS1_SHARED0DIV4_GATE,
  131. GAT_CMU_FSYS1_SHARED1DIV4_GATE,
  132. GAT_CMU_IMEM_ACLK_GATE,
  133. GAT_CMU_IMEM_DMACLK_GATE,
  134. GAT_CMU_IMEM_TCUCLK_GATE,
  135. GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE,
  136. GAT_CMU_PERIC_SHARED0DIVE4_GATE,
  137. GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE,
  138. GAT_CMU_PERIC_SHARED1DIVE4_GATE,
  139. GAT_CMU_CMU_CMU_IPCLKPORT_PCLK,
  140. GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK,
  141. GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU,
  142. GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK,
  143. };
  144. static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
  145. PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0),
  146. };
  147. static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
  148. PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
  149. };
  150. static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
  151. PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
  152. };
  153. static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
  154. PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0),
  155. };
  156. static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
  157. PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
  158. PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
  159. PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
  160. PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
  161. PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
  162. PLL_CON0_PLL_SHARED2, pll_shared2_rate_table),
  163. PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
  164. PLL_CON0_PLL_SHARED3, pll_shared3_rate_table),
  165. };
  166. /* List of parent clocks for Muxes in CMU_CMU */
  167. PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
  168. PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
  169. PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
  170. PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
  171. PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
  172. PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
  173. PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
  174. PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
  175. PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
  176. PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
  177. PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
  178. static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
  179. MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
  180. MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
  181. MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
  182. MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
  183. MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
  184. MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
  185. MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
  186. MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
  187. MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
  188. MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
  189. MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
  190. MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
  191. };
  192. static const struct samsung_div_clock cmu_div_clks[] __initconst = {
  193. DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
  194. DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
  195. DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
  196. DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
  197. DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
  198. DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate",
  199. DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
  200. DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
  201. DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
  202. DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate",
  203. DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
  204. DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate",
  205. DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
  206. DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate",
  207. DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
  208. DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate",
  209. DIV_CMU_IMEM_ACLK, 0, 4),
  210. DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate",
  211. DIV_CMU_IMEM_DMACLK, 0, 4),
  212. DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate",
  213. DIV_CMU_IMEM_TCUCLK, 0, 4),
  214. DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20",
  215. "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
  216. DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk",
  217. "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
  218. DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36",
  219. "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
  220. DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk",
  221. "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
  222. DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
  223. DIV_PLL_SHARED0_DIV2, 0, 4),
  224. DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
  225. DIV_PLL_SHARED0_DIV3, 0, 4),
  226. DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2",
  227. DIV_PLL_SHARED0_DIV4, 0, 4),
  228. DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3",
  229. DIV_PLL_SHARED0_DIV6, 0, 4),
  230. DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
  231. DIV_PLL_SHARED1_DIV3, 0, 4),
  232. DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
  233. DIV_PLL_SHARED1_DIV36, 0, 4),
  234. DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
  235. DIV_PLL_SHARED1_DIV4, 0, 4),
  236. DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
  237. DIV_PLL_SHARED1_DIV9, 0, 4),
  238. };
  239. static const struct samsung_gate_clock cmu_gate_clks[] __initconst = {
  240. GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
  241. CLK_IGNORE_UNUSED, 0),
  242. GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
  243. CLK_IGNORE_UNUSED, 0),
  244. GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
  245. CLK_IGNORE_UNUSED, 0),
  246. GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
  247. GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
  248. GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
  249. GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  250. GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
  251. GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
  252. GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
  253. GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  254. GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
  255. GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  256. GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
  257. GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  258. GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
  259. CLK_IGNORE_UNUSED, 0),
  260. GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
  261. CLK_IGNORE_UNUSED, 0),
  262. GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
  263. CLK_IGNORE_UNUSED, 0),
  264. GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
  265. GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
  266. GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
  267. GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  268. GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
  269. GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
  270. GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
  271. GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  272. GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
  273. GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  274. GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
  275. GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  276. GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
  277. GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
  278. GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
  279. GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  280. };
  281. static const struct samsung_cmu_info cmu_cmu_info __initconst = {
  282. .pll_clks = cmu_pll_clks,
  283. .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks),
  284. .mux_clks = cmu_mux_clks,
  285. .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks),
  286. .div_clks = cmu_div_clks,
  287. .nr_div_clks = ARRAY_SIZE(cmu_div_clks),
  288. .gate_clks = cmu_gate_clks,
  289. .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
  290. .nr_clk_ids = CMU_NR_CLK,
  291. .clk_regs = cmu_clk_regs,
  292. .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
  293. };
  294. static void __init fsd_clk_cmu_init(struct device_node *np)
  295. {
  296. samsung_cmu_register_one(np, &cmu_cmu_info);
  297. }
  298. CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
  299. /* Register Offset definitions for CMU_PERIC (0x14010000) */
  300. #define PLL_CON0_PERIC_DMACLK_MUX 0x100
  301. #define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120
  302. #define PLL_CON0_PERIC_PCLK_MUX 0x140
  303. #define PLL_CON0_PERIC_TBUCLK_MUX 0x160
  304. #define PLL_CON0_SPI_CLK 0x180
  305. #define PLL_CON0_SPI_PCLK 0x1a0
  306. #define PLL_CON0_UART_CLK 0x1c0
  307. #define PLL_CON0_UART_PCLK 0x1e0
  308. #define MUX_PERIC_EQOS_PHYRXCLK 0x1000
  309. #define DIV_EQOS_BUSCLK 0x1800
  310. #define DIV_PERIC_MCAN_CLK 0x1804
  311. #define DIV_RGMII_CLK 0x1808
  312. #define DIV_RII_CLK 0x180c
  313. #define DIV_RMII_CLK 0x1810
  314. #define DIV_SPI_CLK 0x1814
  315. #define DIV_UART_CLK 0x1818
  316. #define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000
  317. #define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004
  318. #define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008
  319. #define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c
  320. #define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010
  321. #define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014
  322. #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018
  323. #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c
  324. #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020
  325. #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024
  326. #define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028
  327. #define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c
  328. #define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030
  329. #define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034
  330. #define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038
  331. #define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c
  332. #define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040
  333. #define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044
  334. #define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048
  335. #define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c
  336. #define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050
  337. #define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054
  338. #define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058
  339. #define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c
  340. #define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060
  341. #define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064
  342. #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068
  343. #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c
  344. #define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070
  345. #define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074
  346. #define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078
  347. #define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c
  348. #define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080
  349. #define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084
  350. #define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088
  351. #define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c
  352. #define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090
  353. #define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094
  354. #define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098
  355. #define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c
  356. #define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0
  357. #define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4
  358. #define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8
  359. #define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac
  360. #define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0
  361. #define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4
  362. #define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8
  363. #define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc
  364. #define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0
  365. #define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4
  366. #define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8
  367. #define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc
  368. #define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0
  369. #define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4
  370. #define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8
  371. #define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc
  372. #define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0
  373. #define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4
  374. #define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8
  375. #define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec
  376. #define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0
  377. #define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4
  378. #define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8
  379. #define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc
  380. #define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100
  381. #define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104
  382. static const unsigned long peric_clk_regs[] __initconst = {
  383. PLL_CON0_PERIC_DMACLK_MUX,
  384. PLL_CON0_PERIC_EQOS_BUSCLK_MUX,
  385. PLL_CON0_PERIC_PCLK_MUX,
  386. PLL_CON0_PERIC_TBUCLK_MUX,
  387. PLL_CON0_SPI_CLK,
  388. PLL_CON0_SPI_PCLK,
  389. PLL_CON0_UART_CLK,
  390. PLL_CON0_UART_PCLK,
  391. MUX_PERIC_EQOS_PHYRXCLK,
  392. DIV_EQOS_BUSCLK,
  393. DIV_PERIC_MCAN_CLK,
  394. DIV_RGMII_CLK,
  395. DIV_RII_CLK,
  396. DIV_RMII_CLK,
  397. DIV_SPI_CLK,
  398. DIV_UART_CLK,
  399. GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I,
  400. GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
  401. GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK,
  402. GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK,
  403. GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK,
  404. GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK,
  405. GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM,
  406. GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS,
  407. GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM,
  408. GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS,
  409. GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK,
  410. GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK,
  411. GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK,
  412. GAT_BUS_D_PERIC_IPCLKPORT_DMACLK,
  413. GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK,
  414. GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK,
  415. GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK,
  416. GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK,
  417. GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK,
  418. GAT_EQOS_TOP_IPCLKPORT_ACLK_I,
  419. GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I,
  420. GAT_EQOS_TOP_IPCLKPORT_HCLK_I,
  421. GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I,
  422. GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I,
  423. GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I,
  424. GAT_GPIO_PERIC_IPCLKPORT_PCLK,
  425. GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D,
  426. GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P,
  427. GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0,
  428. GAT_PERIC_DMA0_IPCLKPORT_ACLK,
  429. GAT_PERIC_DMA1_IPCLKPORT_ACLK,
  430. GAT_PERIC_I2C0_IPCLKPORT_I_PCLK,
  431. GAT_PERIC_I2C1_IPCLKPORT_I_PCLK,
  432. GAT_PERIC_I2C2_IPCLKPORT_I_PCLK,
  433. GAT_PERIC_I2C3_IPCLKPORT_I_PCLK,
  434. GAT_PERIC_I2C4_IPCLKPORT_I_PCLK,
  435. GAT_PERIC_I2C5_IPCLKPORT_I_PCLK,
  436. GAT_PERIC_I2C6_IPCLKPORT_I_PCLK,
  437. GAT_PERIC_I2C7_IPCLKPORT_I_PCLK,
  438. GAT_PERIC_MCAN0_IPCLKPORT_CCLK,
  439. GAT_PERIC_MCAN0_IPCLKPORT_PCLK,
  440. GAT_PERIC_MCAN1_IPCLKPORT_CCLK,
  441. GAT_PERIC_MCAN1_IPCLKPORT_PCLK,
  442. GAT_PERIC_MCAN2_IPCLKPORT_CCLK,
  443. GAT_PERIC_MCAN2_IPCLKPORT_PCLK,
  444. GAT_PERIC_MCAN3_IPCLKPORT_CCLK,
  445. GAT_PERIC_MCAN3_IPCLKPORT_PCLK,
  446. GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0,
  447. GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0,
  448. GAT_PERIC_SMMU_IPCLKPORT_CCLK,
  449. GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK,
  450. GAT_PERIC_SPI0_IPCLKPORT_I_PCLK,
  451. GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI,
  452. GAT_PERIC_SPI1_IPCLKPORT_I_PCLK,
  453. GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI,
  454. GAT_PERIC_SPI2_IPCLKPORT_I_PCLK,
  455. GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI,
  456. GAT_PERIC_TDM0_IPCLKPORT_HCLK_M,
  457. GAT_PERIC_TDM0_IPCLKPORT_PCLK,
  458. GAT_PERIC_TDM1_IPCLKPORT_HCLK_M,
  459. GAT_PERIC_TDM1_IPCLKPORT_PCLK,
  460. GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART,
  461. GAT_PERIC_UART0_IPCLKPORT_PCLK,
  462. GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART,
  463. GAT_PERIC_UART1_IPCLKPORT_PCLK,
  464. GAT_SYSREG_PERI_IPCLKPORT_PCLK,
  465. };
  466. static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = {
  467. FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
  468. };
  469. /* List of parent clocks for Muxes in CMU_PERIC */
  470. PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
  471. PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
  472. PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
  473. PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
  474. PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
  475. PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
  476. PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
  477. PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
  478. PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" };
  479. static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
  480. MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
  481. MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
  482. PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1),
  483. MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
  484. MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
  485. MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
  486. MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
  487. MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
  488. MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
  489. MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p,
  490. MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
  491. };
  492. static const struct samsung_div_clock peric_div_clks[] __initconst = {
  493. DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
  494. DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
  495. DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk",
  496. DIV_RGMII_CLK, 0, 4),
  497. DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
  498. DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
  499. DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
  500. DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
  501. };
  502. static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
  503. GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i",
  504. "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
  505. GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
  506. 21, CLK_IGNORE_UNUSED, 0),
  507. GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
  508. GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
  509. GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
  510. GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  511. GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
  512. CLK_IGNORE_UNUSED, 0),
  513. GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
  514. CLK_IGNORE_UNUSED, 0),
  515. GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
  516. GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
  517. GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
  518. GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
  519. GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
  520. GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
  521. GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
  522. GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
  523. GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
  524. GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  525. GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
  526. GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  527. GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
  528. GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  529. GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
  530. GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
  531. GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk",
  532. "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
  533. GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
  534. GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  535. GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk",
  536. "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
  537. GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
  538. GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  539. GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
  540. GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
  541. GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i",
  542. "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
  543. GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i",
  544. "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
  545. GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i",
  546. "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
  547. GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i",
  548. "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
  549. GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
  550. GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
  551. GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
  552. GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
  553. GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
  554. GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  555. GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
  556. GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
  557. GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
  558. GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
  559. GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
  560. GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
  561. GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk",
  562. GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  563. GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk",
  564. GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  565. GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk",
  566. GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  567. GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk",
  568. GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  569. GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk",
  570. GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  571. GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk",
  572. GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  573. GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk",
  574. GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  575. GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk",
  576. GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  577. GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk",
  578. GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  579. GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk",
  580. GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  581. GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk",
  582. GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
  583. GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk",
  584. GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  585. GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk",
  586. GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
  587. GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk",
  588. GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  589. GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk",
  590. GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
  591. GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk",
  592. GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  593. GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk",
  594. GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
  595. GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk",
  596. GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  597. GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk",
  598. GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
  599. GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk",
  600. GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
  601. GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
  602. GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
  603. GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
  604. GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
  605. GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk",
  606. GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  607. GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
  608. GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
  609. GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk",
  610. GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  611. GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
  612. GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
  613. GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk",
  614. GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  615. GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
  616. GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
  617. GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk",
  618. GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
  619. GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk",
  620. GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  621. GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk",
  622. GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
  623. GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk",
  624. GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  625. GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
  626. GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
  627. GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk",
  628. GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  629. GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
  630. GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
  631. GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk",
  632. GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  633. GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
  634. GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  635. };
  636. static const struct samsung_cmu_info peric_cmu_info __initconst = {
  637. .mux_clks = peric_mux_clks,
  638. .nr_mux_clks = ARRAY_SIZE(peric_mux_clks),
  639. .div_clks = peric_div_clks,
  640. .nr_div_clks = ARRAY_SIZE(peric_div_clks),
  641. .gate_clks = peric_gate_clks,
  642. .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
  643. .fixed_clks = peric_fixed_clks,
  644. .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
  645. .nr_clk_ids = PERIC_NR_CLK,
  646. .clk_regs = peric_clk_regs,
  647. .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
  648. .clk_name = "dout_cmu_pll_shared0_div4",
  649. };
  650. /* Register Offset definitions for CMU_FSYS0 (0x15010000) */
  651. #define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100
  652. #define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140
  653. #define PLL_CON0_EQOS_RGMII_125_MUX1 0x160
  654. #define DIV_CLK_UNIPRO 0x1800
  655. #define DIV_EQS_RGMII_CLK_125 0x1804
  656. #define DIV_PERIBUS_GRP 0x1808
  657. #define DIV_EQOS_RII_CLK2O5 0x180c
  658. #define DIV_EQOS_RMIICLK_25 0x1810
  659. #define DIV_PCIE_PHY_OSCCLK 0x1814
  660. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004
  661. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008
  662. #define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c
  663. #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010
  664. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014
  665. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018
  666. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c
  667. #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020
  668. #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024
  669. #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028
  670. #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c
  671. #define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038
  672. #define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c
  673. #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040
  674. #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044
  675. #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048
  676. #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c
  677. #define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050
  678. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054
  679. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058
  680. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c
  681. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060
  682. #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064
  683. #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068
  684. #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c
  685. #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070
  686. #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074
  687. #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078
  688. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c
  689. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080
  690. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084
  691. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088
  692. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c
  693. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090
  694. #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094
  695. #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098
  696. #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c
  697. #define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0
  698. #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4
  699. #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8
  700. #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac
  701. #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0
  702. #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4
  703. #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8
  704. #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc
  705. #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0
  706. #define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4
  707. static const unsigned long fsys0_clk_regs[] __initconst = {
  708. PLL_CON0_CLKCMU_FSYS0_UNIPRO,
  709. PLL_CON0_CLK_FSYS0_SLAVEBUSCLK,
  710. PLL_CON0_EQOS_RGMII_125_MUX1,
  711. DIV_CLK_UNIPRO,
  712. DIV_EQS_RGMII_CLK_125,
  713. DIV_PERIBUS_GRP,
  714. DIV_EQOS_RII_CLK2O5,
  715. DIV_EQOS_RMIICLK_25,
  716. DIV_PCIE_PHY_OSCCLK,
  717. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I,
  718. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I,
  719. GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
  720. GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK,
  721. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO,
  722. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK,
  723. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC,
  724. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
  725. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
  726. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
  727. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
  728. GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK,
  729. GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK,
  730. GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK,
  731. GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK,
  732. GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK,
  733. GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK,
  734. GAT_FSYS0_CPE425_IPCLKPORT_ACLK,
  735. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I,
  736. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I,
  737. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I,
  738. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I,
  739. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I,
  740. GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK,
  741. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D,
  742. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1,
  743. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P,
  744. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S,
  745. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK,
  746. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
  747. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0,
  748. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC,
  749. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
  750. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC,
  751. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC,
  752. GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK,
  753. GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK,
  754. GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK,
  755. GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS,
  756. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK,
  757. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO,
  758. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK,
  759. GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS,
  760. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK,
  761. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO,
  762. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK,
  763. GAT_FSYS0_RII_CLK_DIVGATE,
  764. };
  765. static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = {
  766. FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000),
  767. FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000),
  768. FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000),
  769. };
  770. /* List of parent clocks for Muxes in CMU_FSYS0 */
  771. PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" };
  772. PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" };
  773. PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" };
  774. static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
  775. MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
  776. PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1),
  777. MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p,
  778. PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1),
  779. MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
  780. PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1),
  781. };
  782. static const struct samsung_div_clock fsys0_div_clks[] __initconst = {
  783. DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4),
  784. DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1",
  785. DIV_EQS_RGMII_CLK_125, 0, 4),
  786. DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp",
  787. "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4),
  788. DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4),
  789. DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1",
  790. DIV_EQOS_RMIICLK_25, 0, 5),
  791. DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1",
  792. DIV_PCIE_PHY_OSCCLK, 0, 4),
  793. };
  794. static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
  795. GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i",
  796. "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21,
  797. CLK_IGNORE_UNUSED, 0),
  798. GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC,
  799. "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll",
  800. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21,
  801. CLK_IGNORE_UNUSED, 0),
  802. GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
  803. GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  804. GATE(0,
  805. "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo",
  806. "xtal_clk_pcie_phy",
  807. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21,
  808. CLK_IGNORE_UNUSED, 0),
  809. GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24",
  810. "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
  811. CLK_IGNORE_UNUSED, 0),
  812. GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26",
  813. "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
  814. CLK_IGNORE_UNUSED, 0),
  815. GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24",
  816. "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
  817. CLK_IGNORE_UNUSED, 0),
  818. GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26",
  819. "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
  820. CLK_IGNORE_UNUSED, 0),
  821. GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp",
  822. GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0),
  823. GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp",
  824. GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  825. GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk",
  826. GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  827. GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp",
  828. GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
  829. GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp",
  830. GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  831. GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1",
  832. GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
  833. GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk",
  834. GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  835. GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i",
  836. "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21,
  837. CLK_IGNORE_UNUSED, 0),
  838. GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i",
  839. "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21,
  840. CLK_IGNORE_UNUSED, 0),
  841. GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i",
  842. "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21,
  843. CLK_IGNORE_UNUSED, 0),
  844. GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5",
  845. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
  846. GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25",
  847. GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
  848. GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
  849. GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  850. GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
  851. GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
  852. GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d",
  853. "mout_fsys0_clk_fsys0_slavebusclk",
  854. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21,
  855. CLK_IGNORE_UNUSED, 0),
  856. GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1",
  857. "mout_fsys0_eqos_rgmii_125_mux1",
  858. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21,
  859. CLK_IGNORE_UNUSED, 0),
  860. GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p",
  861. "dout_fsys0_peribus_grp",
  862. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21,
  863. CLK_IGNORE_UNUSED, 0),
  864. GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s",
  865. "mout_fsys0_clk_fsys0_slavebusclk",
  866. GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21,
  867. CLK_IGNORE_UNUSED, 0),
  868. GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk",
  869. "dout_fsys0_peribus_grp",
  870. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21,
  871. CLK_IGNORE_UNUSED, 0),
  872. GATE(0,
  873. "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll",
  874. "dout_fsys0_pcie_phy_oscclk",
  875. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
  876. 21, CLK_IGNORE_UNUSED, 0),
  877. GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp",
  878. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0),
  879. GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
  880. GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0),
  881. GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC,
  882. "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc",
  883. "dout_fsys0_peribus_grp",
  884. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21,
  885. CLK_IGNORE_UNUSED, 0),
  886. GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
  887. "dout_fsys0_peribus_grp",
  888. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21,
  889. CLK_IGNORE_UNUSED, 0),
  890. GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC,
  891. "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc",
  892. "mout_fsys0_clk_fsys0_slavebusclk",
  893. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21,
  894. CLK_IGNORE_UNUSED, 0),
  895. GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC,
  896. "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc",
  897. "mout_fsys0_clk_fsys0_slavebusclk",
  898. GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21,
  899. CLK_IGNORE_UNUSED, 0),
  900. GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1",
  901. GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
  902. GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk",
  903. GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0),
  904. GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
  905. GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  906. GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
  907. GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
  908. GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
  909. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  910. GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
  911. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
  912. GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
  913. GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
  914. GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
  915. GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
  916. GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
  917. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  918. GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
  919. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
  920. GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
  921. GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
  922. GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE,
  923. 21, CLK_IGNORE_UNUSED, 0),
  924. GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i",
  925. "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
  926. };
  927. static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
  928. .mux_clks = fsys0_mux_clks,
  929. .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
  930. .div_clks = fsys0_div_clks,
  931. .nr_div_clks = ARRAY_SIZE(fsys0_div_clks),
  932. .gate_clks = fsys0_gate_clks,
  933. .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
  934. .fixed_clks = fsys0_fixed_clks,
  935. .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks),
  936. .nr_clk_ids = FSYS0_NR_CLK,
  937. .clk_regs = fsys0_clk_regs,
  938. .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
  939. .clk_name = "dout_cmu_fsys0_shared1div4",
  940. };
  941. /* Register Offset definitions for CMU_FSYS1 (0x16810000) */
  942. #define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100
  943. #define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180
  944. #define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800
  945. #define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804
  946. #define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000
  947. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004
  948. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008
  949. #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c
  950. #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c
  951. #define GAT_FSYS1_PHY0_OSCCLLK 0x2034
  952. #define GAT_FSYS1_PHY1_OSCCLK 0x2038
  953. #define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c
  954. #define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040
  955. #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048
  956. #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c
  957. #define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054
  958. #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c
  959. #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064
  960. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c
  961. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070
  962. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074
  963. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078
  964. #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c
  965. #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080
  966. #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084
  967. #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088
  968. #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c
  969. #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4
  970. #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8
  971. #define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4
  972. #define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8
  973. static const unsigned long fsys1_clk_regs[] __initconst = {
  974. PLL_CON0_ACLK_FSYS1_BUSP_MUX,
  975. PLL_CON0_PCLKL_FSYS1_BUSP_MUX,
  976. DIV_CLK_FSYS1_PHY0_OSCCLK,
  977. DIV_CLK_FSYS1_PHY1_OSCCLK,
  978. GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
  979. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK,
  980. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK,
  981. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK,
  982. GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL,
  983. GAT_FSYS1_PHY0_OSCCLLK,
  984. GAT_FSYS1_PHY1_OSCCLK,
  985. GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK,
  986. GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK,
  987. GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK,
  988. GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK,
  989. GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK,
  990. GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0,
  991. GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0,
  992. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK,
  993. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK,
  994. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK,
  995. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK,
  996. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK,
  997. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK,
  998. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK,
  999. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK,
  1000. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK,
  1001. GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK,
  1002. GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL,
  1003. GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK,
  1004. GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK,
  1005. };
  1006. static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = {
  1007. FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000),
  1008. FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000),
  1009. };
  1010. /* List of parent clocks for Muxes in CMU_FSYS1 */
  1011. PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" };
  1012. PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" };
  1013. static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
  1014. MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p,
  1015. PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1),
  1016. MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
  1017. PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1),
  1018. };
  1019. static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
  1020. DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk",
  1021. DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4),
  1022. DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk",
  1023. DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4),
  1024. };
  1025. static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
  1026. GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1027. GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1028. GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref",
  1029. GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0),
  1030. GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux",
  1031. GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0),
  1032. GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux",
  1033. GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
  1034. GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1035. GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1036. GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
  1037. GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  1038. GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1039. GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0),
  1040. GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
  1041. GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  1042. GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
  1043. GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1044. GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0",
  1045. "mout_fsys1_aclk_fsys1_busp_mux",
  1046. GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21,
  1047. CLK_IGNORE_UNUSED, 0),
  1048. GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0",
  1049. "mout_fsys1_aclk_fsys1_busp_mux",
  1050. GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21,
  1051. CLK_IGNORE_UNUSED, 0),
  1052. GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk",
  1053. "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21,
  1054. CLK_IGNORE_UNUSED, 0),
  1055. GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1056. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1057. GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
  1058. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1059. GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1060. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1061. GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk",
  1062. "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21,
  1063. CLK_IGNORE_UNUSED, 0),
  1064. GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk",
  1065. "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21,
  1066. CLK_IGNORE_UNUSED, 0),
  1067. GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk",
  1068. "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21,
  1069. CLK_IGNORE_UNUSED, 0),
  1070. GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1071. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1072. GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk",
  1073. "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21,
  1074. CLK_IGNORE_UNUSED, 0),
  1075. GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk",
  1076. "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21,
  1077. CLK_IGNORE_UNUSED, 0),
  1078. GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1079. GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1080. GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll",
  1081. GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
  1082. GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll",
  1083. GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
  1084. GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk",
  1085. GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0),
  1086. GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
  1087. GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1088. GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
  1089. GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1090. };
  1091. static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
  1092. .mux_clks = fsys1_mux_clks,
  1093. .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
  1094. .div_clks = fsys1_div_clks,
  1095. .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
  1096. .gate_clks = fsys1_gate_clks,
  1097. .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
  1098. .fixed_clks = fsys1_fixed_clks,
  1099. .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks),
  1100. .nr_clk_ids = FSYS1_NR_CLK,
  1101. .clk_regs = fsys1_clk_regs,
  1102. .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
  1103. .clk_name = "dout_cmu_fsys1_shared0div4",
  1104. };
  1105. /* Register Offset definitions for CMU_IMEM (0x10010000) */
  1106. #define PLL_CON0_CLK_IMEM_ACLK 0x100
  1107. #define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120
  1108. #define PLL_CON0_CLK_IMEM_TCUCLK 0x140
  1109. #define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800
  1110. #define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000
  1111. #define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004
  1112. #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
  1113. #define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c
  1114. #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010
  1115. #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014
  1116. #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018
  1117. #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c
  1118. #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020
  1119. #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024
  1120. #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028
  1121. #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c
  1122. #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030
  1123. #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034
  1124. #define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038
  1125. #define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c
  1126. #define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040
  1127. #define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044
  1128. #define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048
  1129. #define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c
  1130. #define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050
  1131. #define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054
  1132. #define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058
  1133. #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c
  1134. #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060
  1135. #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064
  1136. #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068
  1137. #define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c
  1138. #define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070
  1139. #define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074
  1140. #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078
  1141. #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c
  1142. #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080
  1143. #define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084
  1144. #define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088
  1145. #define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c
  1146. #define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090
  1147. #define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094
  1148. #define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098
  1149. #define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c
  1150. #define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0
  1151. #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4
  1152. #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8
  1153. #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac
  1154. #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0
  1155. #define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4
  1156. #define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8
  1157. #define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc
  1158. #define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0
  1159. #define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4
  1160. #define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8
  1161. #define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc
  1162. #define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0
  1163. #define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4
  1164. #define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8
  1165. #define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc
  1166. static const unsigned long imem_clk_regs[] __initconst = {
  1167. PLL_CON0_CLK_IMEM_ACLK,
  1168. PLL_CON0_CLK_IMEM_INTMEMCLK,
  1169. PLL_CON0_CLK_IMEM_TCUCLK,
  1170. DIV_OSCCLK_IMEM_TMUTSCLK,
  1171. GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
  1172. GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,
  1173. GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
  1174. GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,
  1175. GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,
  1176. GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,
  1177. GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,
  1178. GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,
  1179. GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,
  1180. GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,
  1181. GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,
  1182. GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,
  1183. GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,
  1184. GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,
  1185. GAT_IMEM_WDT0_IPCLKPORT_CLK,
  1186. GAT_IMEM_WDT1_IPCLKPORT_CLK,
  1187. GAT_IMEM_WDT2_IPCLKPORT_CLK,
  1188. GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,
  1189. GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,
  1190. GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,
  1191. GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,
  1192. GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,
  1193. GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,
  1194. GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,
  1195. GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,
  1196. GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,
  1197. GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,
  1198. GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,
  1199. GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,
  1200. GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,
  1201. GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,
  1202. GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,
  1203. GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,
  1204. GAT_IMEM_DMA0_IPCLKPORT_ACLK,
  1205. GAT_IMEM_DMA1_IPCLKPORT_ACLK,
  1206. GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,
  1207. GAT_IMEM_GIC_IPCLKPORT_CLK,
  1208. GAT_IMEM_INTMEM_IPCLKPORT_ACLK,
  1209. GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,
  1210. GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,
  1211. GAT_IMEM_MCT_IPCLKPORT_PCLK,
  1212. GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,
  1213. GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,
  1214. GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,
  1215. GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,
  1216. GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,
  1217. GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,
  1218. GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,
  1219. GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,
  1220. GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,
  1221. GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,
  1222. GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,
  1223. GAT_IMEM_TCU_IPCLKPORT_ACLK,
  1224. GAT_IMEM_WDT0_IPCLKPORT_PCLK,
  1225. GAT_IMEM_WDT1_IPCLKPORT_PCLK,
  1226. GAT_IMEM_WDT2_IPCLKPORT_PCLK,
  1227. };
  1228. PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
  1229. PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
  1230. PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
  1231. static const struct samsung_mux_clock imem_mux_clks[] __initconst = {
  1232. MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
  1233. PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),
  1234. MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
  1235. MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
  1236. PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),
  1237. };
  1238. static const struct samsung_div_clock imem_div_clks[] __initconst = {
  1239. DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
  1240. };
  1241. static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
  1242. GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1243. GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1244. GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
  1245. GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
  1246. GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
  1247. GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1248. GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
  1249. GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1250. GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
  1251. GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1252. GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
  1253. GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1254. GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
  1255. GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
  1256. GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
  1257. GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1258. GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
  1259. GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1260. GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
  1261. GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1262. GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",
  1263. "dout_imem_oscclk_imem_tmutsclk",
  1264. GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
  1265. GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",
  1266. "dout_imem_oscclk_imem_tmutsclk",
  1267. GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
  1268. GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",
  1269. "dout_imem_oscclk_imem_tmutsclk",
  1270. GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
  1271. GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",
  1272. "dout_imem_oscclk_imem_tmutsclk",
  1273. GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
  1274. GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",
  1275. "dout_imem_oscclk_imem_tmutsclk",
  1276. GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
  1277. GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
  1278. GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
  1279. GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
  1280. GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
  1281. GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
  1282. GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
  1283. GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
  1284. GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
  1285. GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
  1286. GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
  1287. GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
  1288. GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
  1289. GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
  1290. GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
  1291. GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
  1292. GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
  1293. GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
  1294. GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
  1295. GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
  1296. GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
  1297. GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
  1298. GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1299. GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
  1300. GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1301. GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
  1302. GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  1303. GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
  1304. GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
  1305. GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
  1306. GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
  1307. GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
  1308. GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
  1309. GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
  1310. GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
  1311. GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
  1312. GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
  1313. GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
  1314. GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1315. GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
  1316. GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1317. GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
  1318. GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1319. GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1320. GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1321. GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1322. GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1323. GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1324. GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1325. GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
  1326. "mout_imem_clk_imem_tcuclk",
  1327. GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
  1328. GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
  1329. "mout_imem_clk_imem_tcuclk",
  1330. GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,
  1331. CLK_IGNORE_UNUSED, 0),
  1332. GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
  1333. GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
  1334. GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1335. GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1336. GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
  1337. GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1338. GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
  1339. GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1340. GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
  1341. GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1342. GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
  1343. GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1344. GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1345. GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1346. GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1347. GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1348. GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
  1349. GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1350. GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1351. GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1352. GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
  1353. GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1354. GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
  1355. GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1356. GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1357. GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1358. GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1359. GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1360. GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",
  1361. GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1362. };
  1363. static const struct samsung_cmu_info imem_cmu_info __initconst = {
  1364. .mux_clks = imem_mux_clks,
  1365. .nr_mux_clks = ARRAY_SIZE(imem_mux_clks),
  1366. .div_clks = imem_div_clks,
  1367. .nr_div_clks = ARRAY_SIZE(imem_div_clks),
  1368. .gate_clks = imem_gate_clks,
  1369. .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
  1370. .nr_clk_ids = IMEM_NR_CLK,
  1371. .clk_regs = imem_clk_regs,
  1372. .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
  1373. };
  1374. static void __init fsd_clk_imem_init(struct device_node *np)
  1375. {
  1376. samsung_cmu_register_one(np, &imem_cmu_info);
  1377. }
  1378. CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
  1379. /* Register Offset definitions for CMU_MFC (0x12810000) */
  1380. #define PLL_LOCKTIME_PLL_MFC 0x0
  1381. #define PLL_CON0_PLL_MFC 0x100
  1382. #define MUX_MFC_BUSD 0x1000
  1383. #define MUX_MFC_BUSP 0x1008
  1384. #define DIV_MFC_BUSD_DIV4 0x1800
  1385. #define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000
  1386. #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004
  1387. #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008
  1388. #define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c
  1389. #define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010
  1390. #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018
  1391. #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c
  1392. #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028
  1393. #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c
  1394. #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030
  1395. #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034
  1396. #define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038
  1397. #define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c
  1398. #define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040
  1399. #define GAT_MFC_BUSD_DIV4_GATE 0x2044
  1400. #define GAT_MFC_BUSD_GATE 0x2048
  1401. static const unsigned long mfc_clk_regs[] __initconst = {
  1402. PLL_LOCKTIME_PLL_MFC,
  1403. PLL_CON0_PLL_MFC,
  1404. MUX_MFC_BUSD,
  1405. MUX_MFC_BUSP,
  1406. DIV_MFC_BUSD_DIV4,
  1407. GAT_MFC_CMU_MFC_IPCLKPORT_PCLK,
  1408. GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM,
  1409. GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS,
  1410. GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK,
  1411. GAT_MFC_MFC_IPCLKPORT_ACLK,
  1412. GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D,
  1413. GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P,
  1414. GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK,
  1415. GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK,
  1416. GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK,
  1417. GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK,
  1418. GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK,
  1419. GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK,
  1420. GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK,
  1421. GAT_MFC_BUSD_DIV4_GATE,
  1422. GAT_MFC_BUSD_GATE,
  1423. };
  1424. static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = {
  1425. PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0),
  1426. };
  1427. static const struct samsung_pll_clock mfc_pll_clks[] __initconst = {
  1428. PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
  1429. PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table),
  1430. };
  1431. PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
  1432. PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
  1433. PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
  1434. static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
  1435. MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
  1436. MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
  1437. MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
  1438. };
  1439. static const struct samsung_div_clock mfc_div_clks[] __initconst = {
  1440. DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
  1441. };
  1442. static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
  1443. GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
  1444. GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1445. GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
  1446. GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
  1447. GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
  1448. GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
  1449. GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
  1450. GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1451. GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd",
  1452. GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1453. GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
  1454. GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
  1455. GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
  1456. GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
  1457. GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
  1458. GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1459. GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
  1460. GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1461. GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
  1462. GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1463. GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
  1464. GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1465. GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
  1466. GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1467. GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
  1468. GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1469. GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
  1470. GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
  1471. GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
  1472. GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
  1473. GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
  1474. };
  1475. static const struct samsung_cmu_info mfc_cmu_info __initconst = {
  1476. .pll_clks = mfc_pll_clks,
  1477. .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks),
  1478. .mux_clks = mfc_mux_clks,
  1479. .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
  1480. .div_clks = mfc_div_clks,
  1481. .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
  1482. .gate_clks = mfc_gate_clks,
  1483. .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
  1484. .nr_clk_ids = MFC_NR_CLK,
  1485. .clk_regs = mfc_clk_regs,
  1486. .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
  1487. };
  1488. /* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
  1489. #define PLL_LOCKTIME_PLL_CAM_CSI 0x0
  1490. #define PLL_CON0_PLL_CAM_CSI 0x100
  1491. #define DIV_CAM_CSI0_ACLK 0x1800
  1492. #define DIV_CAM_CSI1_ACLK 0x1804
  1493. #define DIV_CAM_CSI2_ACLK 0x1808
  1494. #define DIV_CAM_CSI_BUSD 0x180c
  1495. #define DIV_CAM_CSI_BUSP 0x1810
  1496. #define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
  1497. #define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
  1498. #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
  1499. #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
  1500. #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
  1501. #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
  1502. #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
  1503. #define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
  1504. #define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
  1505. #define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
  1506. #define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
  1507. #define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
  1508. #define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
  1509. #define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
  1510. #define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
  1511. #define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
  1512. #define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
  1513. #define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
  1514. #define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
  1515. #define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
  1516. #define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
  1517. #define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
  1518. #define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
  1519. #define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
  1520. #define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
  1521. #define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
  1522. #define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
  1523. #define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
  1524. #define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
  1525. #define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
  1526. #define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
  1527. #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
  1528. #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
  1529. #define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
  1530. #define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
  1531. static const unsigned long cam_csi_clk_regs[] __initconst = {
  1532. PLL_LOCKTIME_PLL_CAM_CSI,
  1533. PLL_CON0_PLL_CAM_CSI,
  1534. DIV_CAM_CSI0_ACLK,
  1535. DIV_CAM_CSI1_ACLK,
  1536. DIV_CAM_CSI2_ACLK,
  1537. DIV_CAM_CSI_BUSD,
  1538. DIV_CAM_CSI_BUSP,
  1539. GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
  1540. GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
  1541. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
  1542. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
  1543. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
  1544. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
  1545. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
  1546. GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
  1547. GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
  1548. GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
  1549. GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
  1550. GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
  1551. GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
  1552. GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
  1553. GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
  1554. GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
  1555. GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
  1556. GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
  1557. GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
  1558. GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
  1559. GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
  1560. GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
  1561. GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
  1562. GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
  1563. GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
  1564. GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
  1565. GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
  1566. GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
  1567. GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
  1568. GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
  1569. GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
  1570. GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
  1571. GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
  1572. GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
  1573. GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
  1574. };
  1575. static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
  1576. PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
  1577. };
  1578. static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
  1579. PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
  1580. PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
  1581. };
  1582. PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
  1583. static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
  1584. MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
  1585. };
  1586. static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
  1587. DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
  1588. DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
  1589. DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
  1590. DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
  1591. DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
  1592. };
  1593. static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
  1594. GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
  1595. GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1596. GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
  1597. GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1598. GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
  1599. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
  1600. GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
  1601. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
  1602. GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
  1603. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
  1604. GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
  1605. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
  1606. CLK_IGNORE_UNUSED, 0),
  1607. GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
  1608. GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
  1609. GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
  1610. GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1611. GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
  1612. GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1613. GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
  1614. GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1615. GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
  1616. GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1617. GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
  1618. GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1619. GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
  1620. GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1621. GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
  1622. GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1623. GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
  1624. GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1625. GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
  1626. GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1627. GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
  1628. GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1629. GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
  1630. GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1631. GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
  1632. GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1633. GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
  1634. GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1635. GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
  1636. GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1637. GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
  1638. GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1639. GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
  1640. GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1641. GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
  1642. GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1643. GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
  1644. GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1645. GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
  1646. GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1647. GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
  1648. GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1649. GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
  1650. GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1651. GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
  1652. GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1653. GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
  1654. GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1655. GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
  1656. GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1657. GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
  1658. "dout_cam_csi_busd",
  1659. GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
  1660. CLK_IGNORE_UNUSED, 0),
  1661. GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
  1662. "dout_cam_csi_busp",
  1663. GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
  1664. CLK_IGNORE_UNUSED, 0),
  1665. GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
  1666. GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
  1667. GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
  1668. GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
  1669. };
  1670. static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
  1671. .pll_clks = cam_csi_pll_clks,
  1672. .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
  1673. .mux_clks = cam_csi_mux_clks,
  1674. .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
  1675. .div_clks = cam_csi_div_clks,
  1676. .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
  1677. .gate_clks = cam_csi_gate_clks,
  1678. .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
  1679. .nr_clk_ids = CAM_CSI_NR_CLK,
  1680. .clk_regs = cam_csi_clk_regs,
  1681. .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
  1682. };
  1683. /**
  1684. * fsd_cmu_probe - Probe function for FSD platform clocks
  1685. * @pdev: Pointer to platform device
  1686. *
  1687. * Configure clock hierarchy for clock domains of FSD platform
  1688. */
  1689. static int __init fsd_cmu_probe(struct platform_device *pdev)
  1690. {
  1691. const struct samsung_cmu_info *info;
  1692. struct device *dev = &pdev->dev;
  1693. info = of_device_get_match_data(dev);
  1694. exynos_arm64_register_cmu(dev, dev->of_node, info);
  1695. return 0;
  1696. }
  1697. /* CMUs which belong to Power Domains and need runtime PM to be implemented */
  1698. static const struct of_device_id fsd_cmu_of_match[] = {
  1699. {
  1700. .compatible = "tesla,fsd-clock-peric",
  1701. .data = &peric_cmu_info,
  1702. }, {
  1703. .compatible = "tesla,fsd-clock-fsys0",
  1704. .data = &fsys0_cmu_info,
  1705. }, {
  1706. .compatible = "tesla,fsd-clock-fsys1",
  1707. .data = &fsys1_cmu_info,
  1708. }, {
  1709. .compatible = "tesla,fsd-clock-mfc",
  1710. .data = &mfc_cmu_info,
  1711. }, {
  1712. .compatible = "tesla,fsd-clock-cam_csi",
  1713. .data = &cam_csi_cmu_info,
  1714. }, {
  1715. },
  1716. };
  1717. static struct platform_driver fsd_cmu_driver __refdata = {
  1718. .driver = {
  1719. .name = "fsd-cmu",
  1720. .of_match_table = fsd_cmu_of_match,
  1721. .suppress_bind_attrs = true,
  1722. },
  1723. .probe = fsd_cmu_probe,
  1724. };
  1725. static int __init fsd_cmu_init(void)
  1726. {
  1727. return platform_driver_register(&fsd_cmu_driver);
  1728. }
  1729. core_initcall(fsd_cmu_init);