rcar-gen4-cpg.h 2.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * R-Car Gen4 Clock Pulse Generator
  4. *
  5. * Copyright (C) 2021 Renesas Electronics Corp.
  6. *
  7. */
  8. #ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
  9. #define __CLK_RENESAS_RCAR_GEN4_CPG_H__
  10. enum rcar_gen4_clk_types {
  11. CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
  12. CLK_TYPE_GEN4_PLL1,
  13. CLK_TYPE_GEN4_PLL2,
  14. CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
  15. CLK_TYPE_GEN4_PLL3,
  16. CLK_TYPE_GEN4_PLL5,
  17. CLK_TYPE_GEN4_PLL4,
  18. CLK_TYPE_GEN4_PLL6,
  19. CLK_TYPE_GEN4_SDSRC,
  20. CLK_TYPE_GEN4_SDH,
  21. CLK_TYPE_GEN4_SD,
  22. CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
  23. CLK_TYPE_GEN4_Z,
  24. CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
  25. CLK_TYPE_GEN4_RPCSRC,
  26. CLK_TYPE_GEN4_RPC,
  27. CLK_TYPE_GEN4_RPCD2,
  28. /* SoC specific definitions start here */
  29. CLK_TYPE_GEN4_SOC_BASE,
  30. };
  31. #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
  32. DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
  33. #define DEF_GEN4_SD(_name, _id, _parent, _offset) \
  34. DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
  35. #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
  36. DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
  37. (_parent0) << 16 | (_parent1), \
  38. .div = (_div0) << 16 | (_div1), .offset = _md)
  39. #define DEF_GEN4_OSC(_name, _id, _parent, _div) \
  40. DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
  41. #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
  42. DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
  43. struct rcar_gen4_cpg_pll_config {
  44. u8 extal_div;
  45. u8 pll1_mult;
  46. u8 pll1_div;
  47. u8 pll2_mult;
  48. u8 pll2_div;
  49. u8 pll3_mult;
  50. u8 pll3_div;
  51. u8 pll4_mult;
  52. u8 pll4_div;
  53. u8 pll5_mult;
  54. u8 pll5_div;
  55. u8 pll6_mult;
  56. u8 pll6_div;
  57. u8 osc_prediv;
  58. };
  59. #define CPG_RPCCKCR 0x874
  60. #define SD0CKCR1 0x8a4
  61. struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
  62. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  63. struct clk **clks, void __iomem *base,
  64. struct raw_notifier_head *notifiers);
  65. int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
  66. unsigned int clk_extalr, u32 mode);
  67. #endif