videocc-sdm845.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/module.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  10. #include "common.h"
  11. #include "clk-alpha-pll.h"
  12. #include "clk-branch.h"
  13. #include "clk-rcg.h"
  14. #include "clk-regmap.h"
  15. #include "clk-pll.h"
  16. #include "gdsc.h"
  17. enum {
  18. P_BI_TCXO,
  19. P_VIDEO_PLL0_OUT_MAIN,
  20. /* P_VIDEO_PLL0_OUT_EVEN, */
  21. /* P_VIDEO_PLL0_OUT_ODD, */
  22. };
  23. static const struct alpha_pll_config video_pll0_config = {
  24. .l = 0x10,
  25. .alpha = 0xaaab,
  26. };
  27. static struct clk_alpha_pll video_pll0 = {
  28. .offset = 0x42c,
  29. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  30. .clkr = {
  31. .hw.init = &(struct clk_init_data){
  32. .name = "video_pll0",
  33. .parent_data = &(const struct clk_parent_data){
  34. .fw_name = "bi_tcxo", .name = "bi_tcxo",
  35. },
  36. .num_parents = 1,
  37. .ops = &clk_alpha_pll_fabia_ops,
  38. },
  39. },
  40. };
  41. static const struct parent_map video_cc_parent_map_0[] = {
  42. { P_BI_TCXO, 0 },
  43. { P_VIDEO_PLL0_OUT_MAIN, 1 },
  44. /* { P_VIDEO_PLL0_OUT_EVEN, 2 }, */
  45. /* { P_VIDEO_PLL0_OUT_ODD, 3 }, */
  46. };
  47. static const struct clk_parent_data video_cc_parent_data_0[] = {
  48. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  49. { .hw = &video_pll0.clkr.hw },
  50. /* { .name = "video_pll0_out_even" }, */
  51. /* { .name = "video_pll0_out_odd" }, */
  52. };
  53. static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
  54. F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
  55. F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  56. F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  57. F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  58. F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  59. F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  60. { }
  61. };
  62. static struct clk_rcg2 video_cc_venus_clk_src = {
  63. .cmd_rcgr = 0x7f0,
  64. .mnd_width = 0,
  65. .hid_width = 5,
  66. .parent_map = video_cc_parent_map_0,
  67. .freq_tbl = ftbl_video_cc_venus_clk_src,
  68. .clkr.hw.init = &(struct clk_init_data){
  69. .name = "video_cc_venus_clk_src",
  70. .parent_data = video_cc_parent_data_0,
  71. .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
  72. .flags = CLK_SET_RATE_PARENT,
  73. .ops = &clk_rcg2_shared_ops,
  74. },
  75. };
  76. static struct clk_branch video_cc_apb_clk = {
  77. .halt_reg = 0x990,
  78. .halt_check = BRANCH_HALT,
  79. .clkr = {
  80. .enable_reg = 0x990,
  81. .enable_mask = BIT(0),
  82. .hw.init = &(struct clk_init_data){
  83. .name = "video_cc_apb_clk",
  84. .ops = &clk_branch2_ops,
  85. },
  86. },
  87. };
  88. static struct clk_branch video_cc_at_clk = {
  89. .halt_reg = 0x9f0,
  90. .halt_check = BRANCH_HALT,
  91. .clkr = {
  92. .enable_reg = 0x9f0,
  93. .enable_mask = BIT(0),
  94. .hw.init = &(struct clk_init_data){
  95. .name = "video_cc_at_clk",
  96. .ops = &clk_branch2_ops,
  97. },
  98. },
  99. };
  100. static struct clk_branch video_cc_qdss_trig_clk = {
  101. .halt_reg = 0x970,
  102. .halt_check = BRANCH_HALT,
  103. .clkr = {
  104. .enable_reg = 0x970,
  105. .enable_mask = BIT(0),
  106. .hw.init = &(struct clk_init_data){
  107. .name = "video_cc_qdss_trig_clk",
  108. .ops = &clk_branch2_ops,
  109. },
  110. },
  111. };
  112. static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
  113. .halt_reg = 0x9d0,
  114. .halt_check = BRANCH_HALT,
  115. .clkr = {
  116. .enable_reg = 0x9d0,
  117. .enable_mask = BIT(0),
  118. .hw.init = &(struct clk_init_data){
  119. .name = "video_cc_qdss_tsctr_div8_clk",
  120. .ops = &clk_branch2_ops,
  121. },
  122. },
  123. };
  124. static struct clk_branch video_cc_vcodec0_axi_clk = {
  125. .halt_reg = 0x930,
  126. .halt_check = BRANCH_HALT,
  127. .clkr = {
  128. .enable_reg = 0x930,
  129. .enable_mask = BIT(0),
  130. .hw.init = &(struct clk_init_data){
  131. .name = "video_cc_vcodec0_axi_clk",
  132. .ops = &clk_branch2_ops,
  133. },
  134. },
  135. };
  136. static struct clk_branch video_cc_vcodec0_core_clk = {
  137. .halt_reg = 0x890,
  138. .halt_check = BRANCH_VOTED,
  139. .clkr = {
  140. .enable_reg = 0x890,
  141. .enable_mask = BIT(0),
  142. .hw.init = &(struct clk_init_data){
  143. .name = "video_cc_vcodec0_core_clk",
  144. .parent_hws = (const struct clk_hw*[]){
  145. &video_cc_venus_clk_src.clkr.hw,
  146. },
  147. .num_parents = 1,
  148. .flags = CLK_SET_RATE_PARENT,
  149. .ops = &clk_branch2_ops,
  150. },
  151. },
  152. };
  153. static struct clk_branch video_cc_vcodec1_axi_clk = {
  154. .halt_reg = 0x950,
  155. .halt_check = BRANCH_HALT,
  156. .clkr = {
  157. .enable_reg = 0x950,
  158. .enable_mask = BIT(0),
  159. .hw.init = &(struct clk_init_data){
  160. .name = "video_cc_vcodec1_axi_clk",
  161. .ops = &clk_branch2_ops,
  162. },
  163. },
  164. };
  165. static struct clk_branch video_cc_vcodec1_core_clk = {
  166. .halt_reg = 0x8d0,
  167. .halt_check = BRANCH_VOTED,
  168. .clkr = {
  169. .enable_reg = 0x8d0,
  170. .enable_mask = BIT(0),
  171. .hw.init = &(struct clk_init_data){
  172. .name = "video_cc_vcodec1_core_clk",
  173. .parent_hws = (const struct clk_hw*[]){
  174. &video_cc_venus_clk_src.clkr.hw,
  175. },
  176. .num_parents = 1,
  177. .flags = CLK_SET_RATE_PARENT,
  178. .ops = &clk_branch2_ops,
  179. },
  180. },
  181. };
  182. static struct clk_branch video_cc_venus_ahb_clk = {
  183. .halt_reg = 0x9b0,
  184. .halt_check = BRANCH_HALT,
  185. .clkr = {
  186. .enable_reg = 0x9b0,
  187. .enable_mask = BIT(0),
  188. .hw.init = &(struct clk_init_data){
  189. .name = "video_cc_venus_ahb_clk",
  190. .ops = &clk_branch2_ops,
  191. },
  192. },
  193. };
  194. static struct clk_branch video_cc_venus_ctl_axi_clk = {
  195. .halt_reg = 0x910,
  196. .halt_check = BRANCH_HALT,
  197. .clkr = {
  198. .enable_reg = 0x910,
  199. .enable_mask = BIT(0),
  200. .hw.init = &(struct clk_init_data){
  201. .name = "video_cc_venus_ctl_axi_clk",
  202. .ops = &clk_branch2_ops,
  203. },
  204. },
  205. };
  206. static struct clk_branch video_cc_venus_ctl_core_clk = {
  207. .halt_reg = 0x850,
  208. .halt_check = BRANCH_HALT,
  209. .clkr = {
  210. .enable_reg = 0x850,
  211. .enable_mask = BIT(0),
  212. .hw.init = &(struct clk_init_data){
  213. .name = "video_cc_venus_ctl_core_clk",
  214. .parent_hws = (const struct clk_hw*[]){
  215. &video_cc_venus_clk_src.clkr.hw,
  216. },
  217. .num_parents = 1,
  218. .flags = CLK_SET_RATE_PARENT,
  219. .ops = &clk_branch2_ops,
  220. },
  221. },
  222. };
  223. static struct gdsc venus_gdsc = {
  224. .gdscr = 0x814,
  225. .pd = {
  226. .name = "venus_gdsc",
  227. },
  228. .cxcs = (unsigned int []){ 0x850, 0x910 },
  229. .cxc_count = 2,
  230. .pwrsts = PWRSTS_OFF_ON,
  231. .flags = POLL_CFG_GDSCR,
  232. };
  233. static struct gdsc vcodec0_gdsc = {
  234. .gdscr = 0x874,
  235. .pd = {
  236. .name = "vcodec0_gdsc",
  237. },
  238. .cxcs = (unsigned int []){ 0x890, 0x930 },
  239. .cxc_count = 2,
  240. .flags = HW_CTRL | POLL_CFG_GDSCR,
  241. .pwrsts = PWRSTS_OFF_ON,
  242. };
  243. static struct gdsc vcodec1_gdsc = {
  244. .gdscr = 0x8b4,
  245. .pd = {
  246. .name = "vcodec1_gdsc",
  247. },
  248. .cxcs = (unsigned int []){ 0x8d0, 0x950 },
  249. .cxc_count = 2,
  250. .flags = HW_CTRL | POLL_CFG_GDSCR,
  251. .pwrsts = PWRSTS_OFF_ON,
  252. };
  253. static struct clk_regmap *video_cc_sdm845_clocks[] = {
  254. [VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
  255. [VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
  256. [VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
  257. [VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
  258. [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
  259. [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
  260. [VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
  261. [VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
  262. [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
  263. [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
  264. [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
  265. [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
  266. [VIDEO_PLL0] = &video_pll0.clkr,
  267. };
  268. static struct gdsc *video_cc_sdm845_gdscs[] = {
  269. [VENUS_GDSC] = &venus_gdsc,
  270. [VCODEC0_GDSC] = &vcodec0_gdsc,
  271. [VCODEC1_GDSC] = &vcodec1_gdsc,
  272. };
  273. static const struct regmap_config video_cc_sdm845_regmap_config = {
  274. .reg_bits = 32,
  275. .reg_stride = 4,
  276. .val_bits = 32,
  277. .max_register = 0xb90,
  278. .fast_io = true,
  279. };
  280. static const struct qcom_cc_desc video_cc_sdm845_desc = {
  281. .config = &video_cc_sdm845_regmap_config,
  282. .clks = video_cc_sdm845_clocks,
  283. .num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
  284. .gdscs = video_cc_sdm845_gdscs,
  285. .num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
  286. };
  287. static const struct of_device_id video_cc_sdm845_match_table[] = {
  288. { .compatible = "qcom,sdm845-videocc" },
  289. { }
  290. };
  291. MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
  292. static int video_cc_sdm845_probe(struct platform_device *pdev)
  293. {
  294. struct regmap *regmap;
  295. regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
  296. if (IS_ERR(regmap))
  297. return PTR_ERR(regmap);
  298. clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
  299. return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
  300. }
  301. static struct platform_driver video_cc_sdm845_driver = {
  302. .probe = video_cc_sdm845_probe,
  303. .driver = {
  304. .name = "sdm845-videocc",
  305. .of_match_table = video_cc_sdm845_match_table,
  306. .sync_state = clk_sync_state,
  307. },
  308. };
  309. static int __init video_cc_sdm845_init(void)
  310. {
  311. return platform_driver_register(&video_cc_sdm845_driver);
  312. }
  313. subsys_initcall(video_cc_sdm845_init);
  314. static void __exit video_cc_sdm845_exit(void)
  315. {
  316. platform_driver_unregister(&video_cc_sdm845_driver);
  317. }
  318. module_exit(video_cc_sdm845_exit);
  319. MODULE_LICENSE("GPL v2");