videocc-lemans.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <dt-bindings/clock/qcom,videocc-lemans.h>
  15. #include "clk-alpha-pll.h"
  16. #include "clk-branch.h"
  17. #include "clk-rcg.h"
  18. #include "clk-regmap.h"
  19. #include "clk-regmap-divider.h"
  20. #include "common.h"
  21. #include "reset.h"
  22. #include "vdd-level-sm8150.h"
  23. static DEFINE_VDD_REGULATORS(vdd_mm, VDD_HIGH_L1 + 1, 1, vdd_corner);
  24. static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);
  25. static struct clk_vdd_class *video_cc_lemans_regulators[] = {
  26. &vdd_mm,
  27. &vdd_mx,
  28. };
  29. enum {
  30. P_BI_TCXO,
  31. P_SLEEP_CLK,
  32. P_VIDEO_PLL0_OUT_MAIN,
  33. P_VIDEO_PLL1_OUT_MAIN,
  34. };
  35. static const struct pll_vco lucid_evo_vco[] = {
  36. { 249600000, 2020000000, 0 },
  37. };
  38. /* 1098MHz configuration */
  39. static struct alpha_pll_config video_pll0_config = {
  40. .l = 0x39,
  41. .cal_l = 0x44,
  42. .alpha = 0x3000,
  43. .config_ctl_val = 0x20485699,
  44. .config_ctl_hi_val = 0x00182261,
  45. .config_ctl_hi1_val = 0x32AA299C,
  46. .user_ctl_val = 0x00000001,
  47. .user_ctl_hi_val = 0x00400805,
  48. };
  49. static struct clk_alpha_pll video_pll0 = {
  50. .offset = 0x0,
  51. .vco_table = lucid_evo_vco,
  52. .num_vco = ARRAY_SIZE(lucid_evo_vco),
  53. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  54. .config = &video_pll0_config,
  55. .clkr = {
  56. .hw.init = &(const struct clk_init_data){
  57. .name = "video_pll0",
  58. .parent_data = &(const struct clk_parent_data){
  59. .fw_name = "bi_tcxo",
  60. },
  61. .num_parents = 1,
  62. .ops = &clk_alpha_pll_lucid_evo_ops,
  63. },
  64. .vdd_data = {
  65. .vdd_class = &vdd_mx,
  66. .num_rate_max = VDD_NUM,
  67. .rate_max = (unsigned long[VDD_NUM]) {
  68. [VDD_LOWER_D1] = 500000000,
  69. [VDD_LOWER] = 615000000,
  70. [VDD_LOW] = 1066000000,
  71. [VDD_LOW_L1] = 1500000000,
  72. [VDD_NOMINAL] = 1800000000,
  73. [VDD_HIGH] = 2020000000},
  74. },
  75. },
  76. };
  77. /* 1098MHz configuration */
  78. static struct alpha_pll_config video_pll1_config = {
  79. .l = 0x39,
  80. .cal_l = 0x44,
  81. .alpha = 0x3000,
  82. .config_ctl_val = 0x20485699,
  83. .config_ctl_hi_val = 0x00182261,
  84. .config_ctl_hi1_val = 0x32AA299C,
  85. .user_ctl_val = 0x00000001,
  86. .user_ctl_hi_val = 0x00400805,
  87. };
  88. static struct clk_alpha_pll video_pll1 = {
  89. .offset = 0x1000,
  90. .vco_table = lucid_evo_vco,
  91. .num_vco = ARRAY_SIZE(lucid_evo_vco),
  92. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  93. .config = &video_pll1_config,
  94. .clkr = {
  95. .hw.init = &(const struct clk_init_data){
  96. .name = "video_pll1",
  97. .parent_data = &(const struct clk_parent_data){
  98. .fw_name = "bi_tcxo",
  99. },
  100. .num_parents = 1,
  101. .ops = &clk_alpha_pll_lucid_evo_ops,
  102. },
  103. .vdd_data = {
  104. .vdd_class = &vdd_mx,
  105. .num_rate_max = VDD_NUM,
  106. .rate_max = (unsigned long[VDD_NUM]) {
  107. [VDD_LOWER_D1] = 500000000,
  108. [VDD_LOWER] = 615000000,
  109. [VDD_LOW] = 1066000000,
  110. [VDD_LOW_L1] = 1500000000,
  111. [VDD_NOMINAL] = 1800000000,
  112. [VDD_HIGH] = 2020000000},
  113. },
  114. },
  115. };
  116. static const struct parent_map video_cc_parent_map_0[] = {
  117. { P_BI_TCXO, 0 },
  118. };
  119. static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
  120. { .fw_name = "bi_tcxo_ao" },
  121. };
  122. static const struct parent_map video_cc_parent_map_1[] = {
  123. { P_BI_TCXO, 0 },
  124. { P_VIDEO_PLL0_OUT_MAIN, 1 },
  125. };
  126. static const struct clk_parent_data video_cc_parent_data_1[] = {
  127. { .fw_name = "bi_tcxo" },
  128. { .hw = &video_pll0.clkr.hw },
  129. };
  130. static const struct parent_map video_cc_parent_map_2[] = {
  131. { P_BI_TCXO, 0 },
  132. { P_VIDEO_PLL1_OUT_MAIN, 1 },
  133. };
  134. static const struct clk_parent_data video_cc_parent_data_2[] = {
  135. { .fw_name = "bi_tcxo" },
  136. { .hw = &video_pll1.clkr.hw },
  137. };
  138. static const struct parent_map video_cc_parent_map_3[] = {
  139. { P_SLEEP_CLK, 0 },
  140. };
  141. static const struct clk_parent_data video_cc_parent_data_3[] = {
  142. { .fw_name = "sleep_clk" },
  143. };
  144. static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
  145. F(19200000, P_BI_TCXO, 1, 0, 0),
  146. { }
  147. };
  148. static struct clk_rcg2 video_cc_ahb_clk_src = {
  149. .cmd_rcgr = 0x8030,
  150. .mnd_width = 0,
  151. .hid_width = 5,
  152. .parent_map = video_cc_parent_map_0,
  153. .freq_tbl = ftbl_video_cc_ahb_clk_src,
  154. .enable_safe_config = true,
  155. .clkr.hw.init = &(const struct clk_init_data){
  156. .name = "video_cc_ahb_clk_src",
  157. .parent_data = video_cc_parent_data_0_ao,
  158. .num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
  159. .ops = &clk_rcg2_ops,
  160. },
  161. };
  162. static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
  163. F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  164. F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  165. F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  166. F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
  167. { }
  168. };
  169. static struct clk_rcg2 video_cc_mvs0_clk_src = {
  170. .cmd_rcgr = 0x8000,
  171. .mnd_width = 0,
  172. .hid_width = 5,
  173. .parent_map = video_cc_parent_map_1,
  174. .freq_tbl = ftbl_video_cc_mvs0_clk_src,
  175. .enable_safe_config = true,
  176. .clkr.hw.init = &(const struct clk_init_data){
  177. .name = "video_cc_mvs0_clk_src",
  178. .parent_data = video_cc_parent_data_1,
  179. .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
  180. .flags = CLK_SET_RATE_PARENT,
  181. .ops = &clk_rcg2_ops,
  182. },
  183. .clkr.vdd_data = {
  184. .vdd_classes = video_cc_lemans_regulators,
  185. .num_vdd_classes = ARRAY_SIZE(video_cc_lemans_regulators),
  186. .num_rate_max = VDD_NUM,
  187. .rate_max = (unsigned long[VDD_NUM]) {
  188. [VDD_LOW_L1] = 1098000000,
  189. [VDD_NOMINAL] = 1332000000,
  190. [VDD_HIGH] = 1599000000,
  191. [VDD_HIGH_L1] = 1680000000},
  192. },
  193. };
  194. static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
  195. F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
  196. F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
  197. F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
  198. F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
  199. { }
  200. };
  201. static struct clk_rcg2 video_cc_mvs1_clk_src = {
  202. .cmd_rcgr = 0x8018,
  203. .mnd_width = 0,
  204. .hid_width = 5,
  205. .parent_map = video_cc_parent_map_2,
  206. .freq_tbl = ftbl_video_cc_mvs1_clk_src,
  207. .enable_safe_config = true,
  208. .clkr.hw.init = &(const struct clk_init_data){
  209. .name = "video_cc_mvs1_clk_src",
  210. .parent_data = video_cc_parent_data_2,
  211. .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
  212. .flags = CLK_SET_RATE_PARENT,
  213. .ops = &clk_rcg2_ops,
  214. },
  215. .clkr.vdd_data = {
  216. .vdd_classes = video_cc_lemans_regulators,
  217. .num_vdd_classes = ARRAY_SIZE(video_cc_lemans_regulators),
  218. .num_rate_max = VDD_NUM,
  219. .rate_max = (unsigned long[VDD_NUM]) {
  220. [VDD_LOW_L1] = 1098000000,
  221. [VDD_NOMINAL] = 1332000000,
  222. [VDD_HIGH] = 1600000000,
  223. [VDD_HIGH_L1] = 1800000000},
  224. },
  225. };
  226. static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
  227. F(32000, P_SLEEP_CLK, 1, 0, 0),
  228. { }
  229. };
  230. static struct clk_rcg2 video_cc_sleep_clk_src = {
  231. .cmd_rcgr = 0x812c,
  232. .mnd_width = 0,
  233. .hid_width = 5,
  234. .parent_map = video_cc_parent_map_3,
  235. .freq_tbl = ftbl_video_cc_sleep_clk_src,
  236. .clkr.hw.init = &(const struct clk_init_data){
  237. .name = "video_cc_sleep_clk_src",
  238. .parent_data = video_cc_parent_data_3,
  239. .num_parents = ARRAY_SIZE(video_cc_parent_data_3),
  240. .ops = &clk_rcg2_ops,
  241. },
  242. .clkr.vdd_data = {
  243. .vdd_class = &vdd_mm,
  244. .num_rate_max = VDD_NUM,
  245. .rate_max = (unsigned long[VDD_NUM]) {
  246. [VDD_LOW_L1] = 32000},
  247. },
  248. };
  249. static struct clk_rcg2 video_cc_xo_clk_src = {
  250. .cmd_rcgr = 0x8110,
  251. .mnd_width = 0,
  252. .hid_width = 5,
  253. .parent_map = video_cc_parent_map_0,
  254. .freq_tbl = ftbl_video_cc_ahb_clk_src,
  255. .enable_safe_config = true,
  256. .clkr.hw.init = &(const struct clk_init_data){
  257. .name = "video_cc_xo_clk_src",
  258. .parent_data = video_cc_parent_data_0_ao,
  259. .num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
  260. .ops = &clk_rcg2_ops,
  261. },
  262. };
  263. static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
  264. .reg = 0x80b8,
  265. .shift = 0,
  266. .width = 4,
  267. .clkr.hw.init = &(const struct clk_init_data) {
  268. .name = "video_cc_mvs0_div_clk_src",
  269. .parent_hws = (const struct clk_hw*[]){
  270. &video_cc_mvs0_clk_src.clkr.hw,
  271. },
  272. .num_parents = 1,
  273. .flags = CLK_SET_RATE_PARENT,
  274. .ops = &clk_regmap_div_ro_ops,
  275. },
  276. };
  277. static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
  278. .reg = 0x806c,
  279. .shift = 0,
  280. .width = 4,
  281. .clkr.hw.init = &(const struct clk_init_data) {
  282. .name = "video_cc_mvs0c_div2_div_clk_src",
  283. .parent_hws = (const struct clk_hw*[]){
  284. &video_cc_mvs0_clk_src.clkr.hw,
  285. },
  286. .num_parents = 1,
  287. .flags = CLK_SET_RATE_PARENT,
  288. .ops = &clk_regmap_div_ro_ops,
  289. },
  290. };
  291. static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
  292. .reg = 0x80dc,
  293. .shift = 0,
  294. .width = 4,
  295. .clkr.hw.init = &(const struct clk_init_data) {
  296. .name = "video_cc_mvs1_div_clk_src",
  297. .parent_hws = (const struct clk_hw*[]){
  298. &video_cc_mvs1_clk_src.clkr.hw,
  299. },
  300. .num_parents = 1,
  301. .flags = CLK_SET_RATE_PARENT,
  302. .ops = &clk_regmap_div_ro_ops,
  303. },
  304. };
  305. static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
  306. .reg = 0x8094,
  307. .shift = 0,
  308. .width = 4,
  309. .clkr.hw.init = &(const struct clk_init_data) {
  310. .name = "video_cc_mvs1c_div2_div_clk_src",
  311. .parent_hws = (const struct clk_hw*[]){
  312. &video_cc_mvs1_clk_src.clkr.hw,
  313. },
  314. .num_parents = 1,
  315. .flags = CLK_SET_RATE_PARENT,
  316. .ops = &clk_regmap_div_ro_ops,
  317. },
  318. };
  319. static struct clk_branch video_cc_mvs0_clk = {
  320. .halt_reg = 0x80b0,
  321. .halt_check = BRANCH_HALT_VOTED,
  322. .hwcg_reg = 0x80b0,
  323. .hwcg_bit = 1,
  324. .clkr = {
  325. .enable_reg = 0x80b0,
  326. .enable_mask = BIT(0),
  327. .hw.init = &(const struct clk_init_data){
  328. .name = "video_cc_mvs0_clk",
  329. .parent_hws = (const struct clk_hw*[]){
  330. &video_cc_mvs0_div_clk_src.clkr.hw,
  331. },
  332. .num_parents = 1,
  333. .flags = CLK_SET_RATE_PARENT,
  334. .ops = &clk_branch2_ops,
  335. },
  336. },
  337. };
  338. static struct clk_branch video_cc_mvs0c_clk = {
  339. .halt_reg = 0x8064,
  340. .halt_check = BRANCH_HALT,
  341. .clkr = {
  342. .enable_reg = 0x8064,
  343. .enable_mask = BIT(0),
  344. .hw.init = &(const struct clk_init_data){
  345. .name = "video_cc_mvs0c_clk",
  346. .parent_hws = (const struct clk_hw*[]){
  347. &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
  348. },
  349. .num_parents = 1,
  350. .flags = CLK_SET_RATE_PARENT,
  351. .ops = &clk_branch2_ops,
  352. },
  353. },
  354. };
  355. static struct clk_branch video_cc_mvs1_clk = {
  356. .halt_reg = 0x80d4,
  357. .halt_check = BRANCH_HALT_VOTED,
  358. .hwcg_reg = 0x80d4,
  359. .hwcg_bit = 1,
  360. .clkr = {
  361. .enable_reg = 0x80d4,
  362. .enable_mask = BIT(0),
  363. .hw.init = &(const struct clk_init_data){
  364. .name = "video_cc_mvs1_clk",
  365. .parent_hws = (const struct clk_hw*[]){
  366. &video_cc_mvs1_div_clk_src.clkr.hw,
  367. },
  368. .num_parents = 1,
  369. .flags = CLK_SET_RATE_PARENT,
  370. .ops = &clk_branch2_ops,
  371. },
  372. },
  373. };
  374. static struct clk_branch video_cc_mvs1c_clk = {
  375. .halt_reg = 0x808c,
  376. .halt_check = BRANCH_HALT,
  377. .clkr = {
  378. .enable_reg = 0x808c,
  379. .enable_mask = BIT(0),
  380. .hw.init = &(const struct clk_init_data){
  381. .name = "video_cc_mvs1c_clk",
  382. .parent_hws = (const struct clk_hw*[]){
  383. &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
  384. },
  385. .num_parents = 1,
  386. .flags = CLK_SET_RATE_PARENT,
  387. .ops = &clk_branch2_ops,
  388. },
  389. },
  390. };
  391. static struct clk_branch video_cc_sleep_clk = {
  392. .halt_reg = 0x8144,
  393. .halt_check = BRANCH_HALT,
  394. .clkr = {
  395. .enable_reg = 0x8144,
  396. .enable_mask = BIT(0),
  397. .hw.init = &(const struct clk_init_data){
  398. .name = "video_cc_sleep_clk",
  399. .parent_hws = (const struct clk_hw*[]){
  400. &video_cc_sleep_clk_src.clkr.hw,
  401. },
  402. .num_parents = 1,
  403. .flags = CLK_SET_RATE_PARENT,
  404. .ops = &clk_branch2_ops,
  405. },
  406. },
  407. };
  408. static struct clk_regmap *video_cc_lemans_clocks[] = {
  409. [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
  410. [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
  411. [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
  412. [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
  413. [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
  414. [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
  415. [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
  416. [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
  417. [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
  418. [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
  419. [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
  420. [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
  421. [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
  422. [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
  423. [VIDEO_PLL0] = &video_pll0.clkr,
  424. [VIDEO_PLL1] = &video_pll1.clkr,
  425. };
  426. static const struct qcom_reset_map video_cc_lemans_resets[] = {
  427. [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e8 },
  428. [CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
  429. [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
  430. [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
  431. [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
  432. [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
  433. [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
  434. };
  435. static const struct regmap_config video_cc_lemans_regmap_config = {
  436. .reg_bits = 32,
  437. .reg_stride = 4,
  438. .val_bits = 32,
  439. .max_register = 0xb000,
  440. .fast_io = true,
  441. };
  442. static struct qcom_cc_desc video_cc_lemans_desc = {
  443. .config = &video_cc_lemans_regmap_config,
  444. .clks = video_cc_lemans_clocks,
  445. .num_clks = ARRAY_SIZE(video_cc_lemans_clocks),
  446. .resets = video_cc_lemans_resets,
  447. .num_resets = ARRAY_SIZE(video_cc_lemans_resets),
  448. .clk_regulators = video_cc_lemans_regulators,
  449. .num_clk_regulators = ARRAY_SIZE(video_cc_lemans_regulators),
  450. };
  451. static const struct of_device_id video_cc_lemans_match_table[] = {
  452. { .compatible = "qcom,lemans-videocc" },
  453. { }
  454. };
  455. MODULE_DEVICE_TABLE(of, video_cc_lemans_match_table);
  456. static int video_cc_lemans_probe(struct platform_device *pdev)
  457. {
  458. struct regmap *regmap;
  459. int ret;
  460. regmap = qcom_cc_map(pdev, &video_cc_lemans_desc);
  461. if (IS_ERR(regmap))
  462. return PTR_ERR(regmap);
  463. ret = qcom_cc_runtime_init(pdev, &video_cc_lemans_desc);
  464. if (ret)
  465. return ret;
  466. ret = pm_runtime_get_sync(&pdev->dev);
  467. if (ret)
  468. return ret;
  469. clk_lucid_evo_pll_configure(&video_pll0, regmap, video_pll0.config);
  470. clk_lucid_evo_pll_configure(&video_pll1, regmap, video_pll1.config);
  471. /*
  472. * Keep clocks always enabled:
  473. * video_cc_ahb_clk
  474. * video_cc_xo_clk
  475. */
  476. regmap_update_bits(regmap, 0x80ec, BIT(0), BIT(0));
  477. regmap_update_bits(regmap, 0x8128, BIT(0), BIT(0));
  478. ret = qcom_cc_really_probe(pdev, &video_cc_lemans_desc, regmap);
  479. if (ret) {
  480. dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
  481. return ret;
  482. }
  483. pm_runtime_put_sync(&pdev->dev);
  484. dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
  485. return ret;
  486. }
  487. static void video_cc_lemans_sync_state(struct device *dev)
  488. {
  489. qcom_cc_sync_state(dev, &video_cc_lemans_desc);
  490. }
  491. static const struct dev_pm_ops video_cc_lemans_pm_ops = {
  492. SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL)
  493. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  494. pm_runtime_force_resume)
  495. };
  496. static struct platform_driver video_cc_lemans_driver = {
  497. .probe = video_cc_lemans_probe,
  498. .driver = {
  499. .name = "video_cc-lemans",
  500. .of_match_table = video_cc_lemans_match_table,
  501. .sync_state = video_cc_lemans_sync_state,
  502. .pm = &video_cc_lemans_pm_ops,
  503. },
  504. };
  505. static int __init video_cc_lemans_init(void)
  506. {
  507. return platform_driver_register(&video_cc_lemans_driver);
  508. }
  509. subsys_initcall(video_cc_lemans_init);
  510. static void __exit video_cc_lemans_exit(void)
  511. {
  512. platform_driver_unregister(&video_cc_lemans_driver);
  513. }
  514. module_exit(video_cc_lemans_exit);
  515. MODULE_DESCRIPTION("QTI VIDEO_CC LEMANS Driver");
  516. MODULE_LICENSE("GPL");