gpucc-pitti.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of.h>
  12. #include <linux/regmap.h>
  13. #include <dt-bindings/clock/qcom,gpucc-pitti.h>
  14. #include "clk-alpha-pll.h"
  15. #include "clk-branch.h"
  16. #include "clk-pll.h"
  17. #include "clk-rcg.h"
  18. #include "clk-regmap.h"
  19. #include "clk-regmap-divider.h"
  20. #include "clk-regmap-mux.h"
  21. #include "common.h"
  22. #include "reset.h"
  23. #include "vdd-level-holi.h"
  24. #define CX_GMU_CBCR_SLEEP_MASK 0xf
  25. #define CX_GMU_CBCR_SLEEP_SHIFT 4
  26. #define CX_GMU_CBCR_WAKE_MASK 0xf
  27. #define CX_GMU_CBCR_WAKE_SHIFT 8
  28. static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);
  29. static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);
  30. static struct clk_vdd_class *gpu_cc_pitti_regulators[] = {
  31. &vdd_cx,
  32. &vdd_mx,
  33. };
  34. enum {
  35. P_BI_TCXO,
  36. P_GPLL0_OUT_MAIN,
  37. P_GPLL0_OUT_MAIN_DIV,
  38. P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
  39. P_GPU_CC_PLL0_OUT_EVEN,
  40. P_GPU_CC_PLL1_OUT_EVEN,
  41. P_GPU_CC_PLL1_OUT_MAIN,
  42. P_GPU_CC_PLL1_OUT_ODD,
  43. };
  44. static const struct pll_vco lucid_evo_vco[] = {
  45. { 249600000, 2020000000, 0 },
  46. };
  47. static const struct pll_vco zonda_evo_vco[] = {
  48. { 600000000, 3600000000, 0 },
  49. };
  50. /* 680MHz configuration */
  51. static const struct alpha_pll_config gpu_cc_pll0_config = {
  52. .l = 0x23,
  53. .alpha = 0x6aaa,
  54. .config_ctl_val = 0x08200800,
  55. .config_ctl_hi_val = 0x05028001,
  56. .config_ctl_hi1_val = 0x00000000,
  57. .user_ctl_hi_val = 0x02001000,
  58. };
  59. static struct clk_alpha_pll gpu_cc_pll0 = {
  60. .offset = 0x0,
  61. .vco_table = zonda_evo_vco,
  62. .num_vco = ARRAY_SIZE(zonda_evo_vco),
  63. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_EVO],
  64. .clkr = {
  65. .hw.init = &(const struct clk_init_data) {
  66. .name = "gpu_cc_pll0",
  67. .parent_data = &(const struct clk_parent_data) {
  68. .fw_name = "bi_tcxo",
  69. },
  70. .num_parents = 1,
  71. .ops = &clk_alpha_pll_zonda_evo_ops,
  72. },
  73. .vdd_data = {
  74. .vdd_class = &vdd_mx,
  75. .num_rate_max = VDD_NUM,
  76. .rate_max = (unsigned long[VDD_NUM]) {
  77. [VDD_LOWER] = 1450000000,
  78. [VDD_LOW] = 2000000000,
  79. [VDD_NOMINAL] = 2900000000,
  80. [VDD_HIGH] = 3600000000},
  81. },
  82. },
  83. };
  84. static struct clk_fixed_factor gpu_cc_pll0_out_even = {
  85. .mult = 1,
  86. .div = 2,
  87. .hw.init = &(struct clk_init_data){
  88. .name = "gpu_cc_pll0_out_even",
  89. .parent_hws = (const struct clk_hw*[]){
  90. &gpu_cc_pll0.clkr.hw,
  91. },
  92. .num_parents = 1,
  93. .flags = CLK_SET_RATE_PARENT,
  94. .ops = &clk_fixed_factor_ops,
  95. },
  96. };
  97. /* 690MHz configuration */
  98. static const struct alpha_pll_config gpu_cc_pll1_config = {
  99. .l = 0x23,
  100. .cal_l = 0x44,
  101. .alpha = 0xf000,
  102. .config_ctl_val = 0x20485699,
  103. .config_ctl_hi_val = 0x00182261,
  104. .config_ctl_hi1_val = 0x32aa299c,
  105. .user_ctl_val = 0x00000000,
  106. .user_ctl_hi_val = 0x00000805,
  107. };
  108. static struct clk_alpha_pll gpu_cc_pll1 = {
  109. .offset = 0x1000,
  110. .vco_table = lucid_evo_vco,
  111. .num_vco = ARRAY_SIZE(lucid_evo_vco),
  112. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  113. .clkr = {
  114. .hw.init = &(const struct clk_init_data) {
  115. .name = "gpu_cc_pll1",
  116. .parent_data = &(const struct clk_parent_data) {
  117. .fw_name = "bi_tcxo",
  118. },
  119. .num_parents = 1,
  120. .ops = &clk_alpha_pll_lucid_evo_ops,
  121. },
  122. .vdd_data = {
  123. .vdd_class = &vdd_mx,
  124. .num_rate_max = VDD_NUM,
  125. .rate_max = (unsigned long[VDD_NUM]) {
  126. [VDD_LOWER_D1] = 500000000,
  127. [VDD_LOWER] = 615000000,
  128. [VDD_LOW] = 1066000000,
  129. [VDD_LOW_L1] = 1500000000,
  130. [VDD_NOMINAL] = 1800000000,
  131. [VDD_HIGH] = 2020000000},
  132. },
  133. },
  134. };
  135. static const struct parent_map gpu_cc_parent_map_0[] = {
  136. { P_BI_TCXO, 0 },
  137. { P_GPU_CC_PLL0_OUT_EVEN, 1 },
  138. { P_GPU_CC_PLL1_OUT_MAIN, 3 },
  139. { P_GPLL0_OUT_MAIN, 5 },
  140. { P_GPLL0_OUT_MAIN_DIV, 6 },
  141. };
  142. static const struct clk_parent_data gpu_cc_parent_data_0[] = {
  143. { .fw_name = "bi_tcxo" },
  144. { .hw = &gpu_cc_pll0_out_even.hw },
  145. { .hw = &gpu_cc_pll1.clkr.hw },
  146. { .fw_name = "gpll0_out_main" },
  147. { .fw_name = "gpll0_out_main_div" },
  148. };
  149. static const struct parent_map gpu_cc_parent_map_1[] = {
  150. { P_BI_TCXO, 0 },
  151. { P_GPU_CC_PLL0_OUT_EVEN, 1 },
  152. { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 2 },
  153. { P_GPU_CC_PLL1_OUT_EVEN, 3 },
  154. { P_GPU_CC_PLL1_OUT_ODD, 4 },
  155. { P_GPLL0_OUT_MAIN, 5 },
  156. };
  157. static const struct clk_parent_data gpu_cc_parent_data_1[] = {
  158. { .fw_name = "bi_tcxo" },
  159. { .hw = &gpu_cc_pll0_out_even.hw },
  160. { .hw = &gpu_cc_pll0.clkr.hw },
  161. { .hw = &gpu_cc_pll1.clkr.hw },
  162. { .hw = &gpu_cc_pll1.clkr.hw },
  163. { .fw_name = "gpll0_out_main" },
  164. };
  165. static const struct parent_map gpu_cc_parent_map_2[] = {
  166. { P_BI_TCXO, 0 },
  167. };
  168. static const struct clk_parent_data gpu_cc_parent_data_2_ao[] = {
  169. { .fw_name = "bi_tcxo_ao" },
  170. };
  171. static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
  172. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  173. { }
  174. };
  175. static struct clk_rcg2 gpu_cc_gmu_clk_src = {
  176. .cmd_rcgr = 0x9160,
  177. .mnd_width = 0,
  178. .hid_width = 5,
  179. .parent_map = gpu_cc_parent_map_0,
  180. .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
  181. .enable_safe_config = true,
  182. .flags = HW_CLK_CTRL_MODE,
  183. .clkr.hw.init = &(const struct clk_init_data) {
  184. .name = "gpu_cc_gmu_clk_src",
  185. .parent_data = gpu_cc_parent_data_0,
  186. .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
  187. .flags = CLK_SET_RATE_PARENT,
  188. .ops = &clk_rcg2_ops,
  189. },
  190. .clkr.vdd_data = {
  191. .vdd_classes = gpu_cc_pitti_regulators,
  192. .num_vdd_classes = ARRAY_SIZE(gpu_cc_pitti_regulators),
  193. .num_rate_max = VDD_NUM,
  194. .rate_max = (unsigned long[VDD_NUM]) {
  195. [VDD_LOWER] = 200000000},
  196. },
  197. };
  198. static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
  199. F(340000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  200. F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  201. F(605000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  202. F(765000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  203. F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  204. F(975000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  205. F(1115000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
  206. { }
  207. };
  208. static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
  209. .cmd_rcgr = 0x906c,
  210. .mnd_width = 0,
  211. .hid_width = 5,
  212. .parent_map = gpu_cc_parent_map_1,
  213. .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
  214. .enable_safe_config = true,
  215. .flags = HW_CLK_CTRL_MODE,
  216. .clkr.hw.init = &(const struct clk_init_data) {
  217. .name = "gpu_cc_gx_gfx3d_clk_src",
  218. .parent_data = gpu_cc_parent_data_1,
  219. .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
  220. .flags = CLK_SET_RATE_PARENT,
  221. .ops = &clk_rcg2_ops,
  222. },
  223. .clkr.vdd_data = {
  224. .vdd_classes = gpu_cc_pitti_regulators,
  225. .num_vdd_classes = ARRAY_SIZE(gpu_cc_pitti_regulators),
  226. .num_rate_max = VDD_NUM,
  227. .rate_max = (unsigned long[VDD_NUM]) {
  228. [VDD_LOWER] = 340000000,
  229. [VDD_LOW] = 500000000,
  230. [VDD_LOW_L1] = 605000000,
  231. [VDD_NOMINAL] = 765024000,
  232. [VDD_NOMINAL_L1] = 875000000,
  233. [VDD_HIGH] = 975072000,
  234. [VDD_HIGH_L1] = 1115000000},
  235. },
  236. };
  237. static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
  238. F(19200000, P_BI_TCXO, 1, 0, 0),
  239. { }
  240. };
  241. static struct clk_rcg2 gpu_cc_xo_clk_src = {
  242. .cmd_rcgr = 0x9008,
  243. .mnd_width = 0,
  244. .hid_width = 5,
  245. .parent_map = gpu_cc_parent_map_2,
  246. .freq_tbl = ftbl_gpu_cc_xo_clk_src,
  247. .enable_safe_config = true,
  248. .flags = HW_CLK_CTRL_MODE,
  249. .clkr.hw.init = &(const struct clk_init_data) {
  250. .name = "gpu_cc_xo_clk_src",
  251. .parent_data = gpu_cc_parent_data_2_ao,
  252. .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2_ao),
  253. .flags = CLK_SET_RATE_PARENT,
  254. .ops = &clk_rcg2_ops,
  255. },
  256. };
  257. static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
  258. .reg = 0x9048,
  259. .shift = 0,
  260. .width = 4,
  261. .clkr.hw.init = &(const struct clk_init_data) {
  262. .name = "gpu_cc_demet_div_clk_src",
  263. .parent_hws = (const struct clk_hw*[]) {
  264. &gpu_cc_xo_clk_src.clkr.hw,
  265. },
  266. .num_parents = 1,
  267. .flags = CLK_SET_RATE_PARENT,
  268. .ops = &clk_regmap_div_ro_ops,
  269. },
  270. };
  271. static struct clk_branch gpu_cc_crc_ahb_clk = {
  272. .halt_reg = 0x90e8,
  273. .halt_check = BRANCH_HALT_DELAY,
  274. .clkr = {
  275. .enable_reg = 0x90e8,
  276. .enable_mask = BIT(0),
  277. .hw.init = &(const struct clk_init_data) {
  278. .name = "gpu_cc_crc_ahb_clk",
  279. .ops = &clk_branch2_ops,
  280. },
  281. },
  282. };
  283. static struct clk_branch gpu_cc_cx_accu_shift_clk = {
  284. .halt_reg = 0x9124,
  285. .halt_check = BRANCH_HALT_VOTED,
  286. .clkr = {
  287. .enable_reg = 0x9124,
  288. .enable_mask = BIT(0),
  289. .hw.init = &(const struct clk_init_data) {
  290. .name = "gpu_cc_cx_accu_shift_clk",
  291. .parent_hws = (const struct clk_hw*[]) {
  292. &gpu_cc_xo_clk_src.clkr.hw,
  293. },
  294. .num_parents = 1,
  295. .flags = CLK_SET_RATE_PARENT,
  296. .ops = &clk_branch2_ops,
  297. },
  298. },
  299. };
  300. static struct clk_branch gpu_cc_cx_gfx3d_clk = {
  301. .halt_reg = 0x9130,
  302. .halt_check = BRANCH_HALT_DELAY,
  303. .clkr = {
  304. .enable_reg = 0x9130,
  305. .enable_mask = BIT(0),
  306. .hw.init = &(const struct clk_init_data) {
  307. .name = "gpu_cc_cx_gfx3d_clk",
  308. .parent_hws = (const struct clk_hw*[]) {
  309. &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
  310. },
  311. .num_parents = 1,
  312. .flags = CLK_SET_RATE_PARENT,
  313. .ops = &clk_branch2_ops,
  314. },
  315. },
  316. };
  317. static struct clk_branch gpu_cc_cx_gmu_clk = {
  318. .halt_reg = 0x9104,
  319. .halt_check = BRANCH_HALT_VOTED,
  320. .clkr = {
  321. .enable_reg = 0x9104,
  322. .enable_mask = BIT(0),
  323. .hw.init = &(const struct clk_init_data) {
  324. .name = "gpu_cc_cx_gmu_clk",
  325. .parent_hws = (const struct clk_hw*[]) {
  326. &gpu_cc_gmu_clk_src.clkr.hw,
  327. },
  328. .num_parents = 1,
  329. .flags = CLK_SET_RATE_PARENT,
  330. .ops = &clk_branch2_ops,
  331. },
  332. },
  333. };
  334. static struct clk_branch gpu_cc_cxo_clk = {
  335. .halt_reg = 0x910c,
  336. .halt_check = BRANCH_HALT,
  337. .clkr = {
  338. .enable_reg = 0x910c,
  339. .enable_mask = BIT(0),
  340. .hw.init = &(const struct clk_init_data) {
  341. .name = "gpu_cc_cxo_clk",
  342. .parent_hws = (const struct clk_hw*[]) {
  343. &gpu_cc_xo_clk_src.clkr.hw,
  344. },
  345. .num_parents = 1,
  346. .flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
  347. .ops = &clk_branch2_ops,
  348. },
  349. },
  350. };
  351. static struct clk_branch gpu_cc_gx_accu_shift_clk = {
  352. .halt_reg = 0x90c4,
  353. .halt_check = BRANCH_HALT_VOTED,
  354. .clkr = {
  355. .enable_reg = 0x90c4,
  356. .enable_mask = BIT(0),
  357. .hw.init = &(const struct clk_init_data) {
  358. .name = "gpu_cc_gx_accu_shift_clk",
  359. .parent_hws = (const struct clk_hw*[]) {
  360. &gpu_cc_xo_clk_src.clkr.hw,
  361. },
  362. .num_parents = 1,
  363. .flags = CLK_SET_RATE_PARENT,
  364. .ops = &clk_branch2_ops,
  365. },
  366. },
  367. };
  368. static struct clk_branch gpu_cc_gx_gfx3d_clk = {
  369. .halt_reg = 0x90a4,
  370. .halt_check = BRANCH_HALT_SKIP,
  371. .clkr = {
  372. .enable_reg = 0x90a4,
  373. .enable_mask = BIT(0),
  374. .hw.init = &(const struct clk_init_data) {
  375. .name = "gpu_cc_gx_gfx3d_clk",
  376. .parent_hws = (const struct clk_hw*[]) {
  377. &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
  378. },
  379. .num_parents = 1,
  380. .flags = CLK_SET_RATE_PARENT,
  381. .ops = &clk_branch2_ops,
  382. },
  383. },
  384. };
  385. static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
  386. .halt_reg = 0x7000,
  387. .halt_check = BRANCH_VOTED,
  388. .clkr = {
  389. .enable_reg = 0x7000,
  390. .enable_mask = BIT(0),
  391. .hw.init = &(const struct clk_init_data) {
  392. .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
  393. .ops = &clk_branch2_ops,
  394. },
  395. },
  396. };
  397. static struct clk_branch gpu_cc_memnoc_gfx_clk = {
  398. .halt_reg = 0x9114,
  399. .halt_check = BRANCH_HALT,
  400. .clkr = {
  401. .enable_reg = 0x9114,
  402. .enable_mask = BIT(0),
  403. .hw.init = &(const struct clk_init_data) {
  404. .name = "gpu_cc_memnoc_gfx_clk",
  405. .ops = &clk_branch2_ops,
  406. },
  407. },
  408. };
  409. struct clk_hw *gpu_cc_pitti_hws[] = {
  410. [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.hw,
  411. };
  412. static struct clk_regmap *gpu_cc_pitti_clocks[] = {
  413. [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
  414. [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
  415. [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
  416. [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
  417. [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
  418. [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
  419. [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
  420. [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
  421. [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
  422. [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
  423. [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
  424. [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
  425. [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
  426. [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
  427. [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
  428. };
  429. static const struct qcom_reset_map gpu_cc_pitti_resets[] = {
  430. [GPUCC_GPU_CC_CX_BCR] = { 0x90cc },
  431. [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x912c },
  432. [GPUCC_GPU_CC_GMU_BCR] = { 0x915c },
  433. [GPUCC_GPU_CC_GX_BCR] = { 0x9050 },
  434. [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
  435. [GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR] = { 0x91b0 },
  436. };
  437. static const struct regmap_config gpu_cc_pitti_regmap_config = {
  438. .reg_bits = 32,
  439. .reg_stride = 4,
  440. .val_bits = 32,
  441. .max_register = 0x9240,
  442. .fast_io = true,
  443. };
  444. static const struct qcom_cc_desc gpu_cc_pitti_desc = {
  445. .config = &gpu_cc_pitti_regmap_config,
  446. .clks = gpu_cc_pitti_clocks,
  447. .num_clks = ARRAY_SIZE(gpu_cc_pitti_clocks),
  448. .clk_hws = gpu_cc_pitti_hws,
  449. .num_clk_hws = ARRAY_SIZE(gpu_cc_pitti_hws),
  450. .resets = gpu_cc_pitti_resets,
  451. .num_resets = ARRAY_SIZE(gpu_cc_pitti_resets),
  452. .clk_regulators = gpu_cc_pitti_regulators,
  453. .num_clk_regulators = ARRAY_SIZE(gpu_cc_pitti_regulators),
  454. };
  455. static const struct of_device_id gpu_cc_pitti_match_table[] = {
  456. { .compatible = "qcom,pitti-gpucc" },
  457. { }
  458. };
  459. MODULE_DEVICE_TABLE(of, gpu_cc_pitti_match_table);
  460. static int gpu_cc_pitti_probe(struct platform_device *pdev)
  461. {
  462. struct regmap *regmap;
  463. unsigned int value, mask;
  464. int ret;
  465. regmap = qcom_cc_map(pdev, &gpu_cc_pitti_desc);
  466. if (IS_ERR(regmap))
  467. return PTR_ERR(regmap);
  468. clk_zonda_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
  469. clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
  470. /* Enable frequency limiter irq */
  471. regmap_write(regmap, 0x91ac, 0x0);
  472. /*
  473. * Keep clocks always enabled:
  474. * gpu_cc_ahb_clk
  475. * gpu_cc_cxo_aon_clk
  476. * gpu_cc_demet_clk
  477. * gpu_cc_gx_cxo_clk
  478. * gpu_cc_sleep_clk
  479. */
  480. regmap_update_bits(regmap, 0x90e4, BIT(0), BIT(0));
  481. regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
  482. regmap_update_bits(regmap, 0x904c, BIT(0), BIT(0));
  483. regmap_update_bits(regmap, 0x90b4, BIT(0), BIT(0));
  484. regmap_update_bits(regmap, 0x90fc, BIT(0), BIT(0));
  485. /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
  486. mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
  487. mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
  488. value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
  489. regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
  490. mask, value);
  491. ret = qcom_cc_really_probe(pdev, &gpu_cc_pitti_desc, regmap);
  492. if (ret) {
  493. dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
  494. return ret;
  495. }
  496. dev_info(&pdev->dev, "Registered GPU CC clocks\n");
  497. return ret;
  498. }
  499. static void gpu_cc_pitti_sync_state(struct device *dev)
  500. {
  501. qcom_cc_sync_state(dev, &gpu_cc_pitti_desc);
  502. }
  503. static struct platform_driver gpu_cc_pitti_driver = {
  504. .probe = gpu_cc_pitti_probe,
  505. .driver = {
  506. .name = "gpu_cc-pitti",
  507. .of_match_table = gpu_cc_pitti_match_table,
  508. .sync_state = gpu_cc_pitti_sync_state,
  509. },
  510. };
  511. static int __init gpu_cc_pitti_init(void)
  512. {
  513. return platform_driver_register(&gpu_cc_pitti_driver);
  514. }
  515. subsys_initcall(gpu_cc_pitti_init);
  516. static void __exit gpu_cc_pitti_exit(void)
  517. {
  518. platform_driver_unregister(&gpu_cc_pitti_driver);
  519. }
  520. module_exit(gpu_cc_pitti_exit);
  521. MODULE_DESCRIPTION("QTI GPU_CC PITTI Driver");
  522. MODULE_LICENSE("GPL");