gcc-msm8998.c 84 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset-controller.h>
  15. #include <dt-bindings/clock/qcom,gcc-msm8998.h>
  16. #include "common.h"
  17. #include "clk-regmap.h"
  18. #include "clk-alpha-pll.h"
  19. #include "clk-pll.h"
  20. #include "clk-rcg.h"
  21. #include "clk-branch.h"
  22. #include "reset.h"
  23. #include "gdsc.h"
  24. static struct pll_vco fabia_vco[] = {
  25. { 250000000, 2000000000, 0 },
  26. { 125000000, 1000000000, 1 },
  27. };
  28. static struct clk_alpha_pll gpll0 = {
  29. .offset = 0x0,
  30. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  31. .vco_table = fabia_vco,
  32. .num_vco = ARRAY_SIZE(fabia_vco),
  33. .clkr = {
  34. .enable_reg = 0x52000,
  35. .enable_mask = BIT(0),
  36. .hw.init = &(struct clk_init_data){
  37. .name = "gpll0",
  38. .parent_data = (const struct clk_parent_data []) {
  39. { .fw_name = "xo" },
  40. },
  41. .num_parents = 1,
  42. .ops = &clk_alpha_pll_fixed_fabia_ops,
  43. }
  44. },
  45. };
  46. static struct clk_alpha_pll_postdiv gpll0_out_even = {
  47. .offset = 0x0,
  48. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  49. .clkr.hw.init = &(struct clk_init_data){
  50. .name = "gpll0_out_even",
  51. .parent_hws = (const struct clk_hw*[]) {
  52. &gpll0.clkr.hw,
  53. },
  54. .num_parents = 1,
  55. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  56. },
  57. };
  58. static struct clk_alpha_pll_postdiv gpll0_out_main = {
  59. .offset = 0x0,
  60. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  61. .clkr.hw.init = &(struct clk_init_data){
  62. .name = "gpll0_out_main",
  63. .parent_hws = (const struct clk_hw*[]) {
  64. &gpll0.clkr.hw,
  65. },
  66. .num_parents = 1,
  67. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  68. },
  69. };
  70. static struct clk_alpha_pll_postdiv gpll0_out_odd = {
  71. .offset = 0x0,
  72. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  73. .clkr.hw.init = &(struct clk_init_data){
  74. .name = "gpll0_out_odd",
  75. .parent_hws = (const struct clk_hw*[]) {
  76. &gpll0.clkr.hw,
  77. },
  78. .num_parents = 1,
  79. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  80. },
  81. };
  82. static struct clk_alpha_pll_postdiv gpll0_out_test = {
  83. .offset = 0x0,
  84. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  85. .clkr.hw.init = &(struct clk_init_data){
  86. .name = "gpll0_out_test",
  87. .parent_hws = (const struct clk_hw*[]) {
  88. &gpll0.clkr.hw,
  89. },
  90. .num_parents = 1,
  91. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  92. },
  93. };
  94. static struct clk_alpha_pll gpll1 = {
  95. .offset = 0x1000,
  96. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  97. .vco_table = fabia_vco,
  98. .num_vco = ARRAY_SIZE(fabia_vco),
  99. .clkr = {
  100. .enable_reg = 0x52000,
  101. .enable_mask = BIT(1),
  102. .hw.init = &(struct clk_init_data){
  103. .name = "gpll1",
  104. .parent_data = (const struct clk_parent_data []) {
  105. { .fw_name = "xo" },
  106. },
  107. .num_parents = 1,
  108. .ops = &clk_alpha_pll_fixed_fabia_ops,
  109. }
  110. },
  111. };
  112. static struct clk_alpha_pll_postdiv gpll1_out_even = {
  113. .offset = 0x1000,
  114. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  115. .clkr.hw.init = &(struct clk_init_data){
  116. .name = "gpll1_out_even",
  117. .parent_hws = (const struct clk_hw*[]) {
  118. &gpll1.clkr.hw,
  119. },
  120. .num_parents = 1,
  121. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  122. },
  123. };
  124. static struct clk_alpha_pll_postdiv gpll1_out_main = {
  125. .offset = 0x1000,
  126. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  127. .clkr.hw.init = &(struct clk_init_data){
  128. .name = "gpll1_out_main",
  129. .parent_hws = (const struct clk_hw*[]) {
  130. &gpll1.clkr.hw,
  131. },
  132. .num_parents = 1,
  133. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  134. },
  135. };
  136. static struct clk_alpha_pll_postdiv gpll1_out_odd = {
  137. .offset = 0x1000,
  138. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  139. .clkr.hw.init = &(struct clk_init_data){
  140. .name = "gpll1_out_odd",
  141. .parent_hws = (const struct clk_hw*[]) {
  142. &gpll1.clkr.hw,
  143. },
  144. .num_parents = 1,
  145. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  146. },
  147. };
  148. static struct clk_alpha_pll_postdiv gpll1_out_test = {
  149. .offset = 0x1000,
  150. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  151. .clkr.hw.init = &(struct clk_init_data){
  152. .name = "gpll1_out_test",
  153. .parent_hws = (const struct clk_hw*[]) {
  154. &gpll1.clkr.hw,
  155. },
  156. .num_parents = 1,
  157. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  158. },
  159. };
  160. static struct clk_alpha_pll gpll2 = {
  161. .offset = 0x2000,
  162. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  163. .vco_table = fabia_vco,
  164. .num_vco = ARRAY_SIZE(fabia_vco),
  165. .clkr = {
  166. .enable_reg = 0x52000,
  167. .enable_mask = BIT(2),
  168. .hw.init = &(struct clk_init_data){
  169. .name = "gpll2",
  170. .parent_data = (const struct clk_parent_data []) {
  171. { .fw_name = "xo" },
  172. },
  173. .num_parents = 1,
  174. .ops = &clk_alpha_pll_fixed_fabia_ops,
  175. }
  176. },
  177. };
  178. static struct clk_alpha_pll_postdiv gpll2_out_even = {
  179. .offset = 0x2000,
  180. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  181. .clkr.hw.init = &(struct clk_init_data){
  182. .name = "gpll2_out_even",
  183. .parent_hws = (const struct clk_hw*[]) {
  184. &gpll2.clkr.hw,
  185. },
  186. .num_parents = 1,
  187. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  188. },
  189. };
  190. static struct clk_alpha_pll_postdiv gpll2_out_main = {
  191. .offset = 0x2000,
  192. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  193. .clkr.hw.init = &(struct clk_init_data){
  194. .name = "gpll2_out_main",
  195. .parent_hws = (const struct clk_hw*[]) {
  196. &gpll2.clkr.hw,
  197. },
  198. .num_parents = 1,
  199. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  200. },
  201. };
  202. static struct clk_alpha_pll_postdiv gpll2_out_odd = {
  203. .offset = 0x2000,
  204. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  205. .clkr.hw.init = &(struct clk_init_data){
  206. .name = "gpll2_out_odd",
  207. .parent_hws = (const struct clk_hw*[]) {
  208. &gpll2.clkr.hw,
  209. },
  210. .num_parents = 1,
  211. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  212. },
  213. };
  214. static struct clk_alpha_pll_postdiv gpll2_out_test = {
  215. .offset = 0x2000,
  216. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  217. .clkr.hw.init = &(struct clk_init_data){
  218. .name = "gpll2_out_test",
  219. .parent_hws = (const struct clk_hw*[]) {
  220. &gpll2.clkr.hw,
  221. },
  222. .num_parents = 1,
  223. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  224. },
  225. };
  226. static struct clk_alpha_pll gpll3 = {
  227. .offset = 0x3000,
  228. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  229. .vco_table = fabia_vco,
  230. .num_vco = ARRAY_SIZE(fabia_vco),
  231. .clkr = {
  232. .enable_reg = 0x52000,
  233. .enable_mask = BIT(3),
  234. .hw.init = &(struct clk_init_data){
  235. .name = "gpll3",
  236. .parent_data = (const struct clk_parent_data []) {
  237. { .fw_name = "xo" },
  238. },
  239. .num_parents = 1,
  240. .ops = &clk_alpha_pll_fixed_fabia_ops,
  241. }
  242. },
  243. };
  244. static struct clk_alpha_pll_postdiv gpll3_out_even = {
  245. .offset = 0x3000,
  246. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  247. .clkr.hw.init = &(struct clk_init_data){
  248. .name = "gpll3_out_even",
  249. .parent_hws = (const struct clk_hw*[]) {
  250. &gpll3.clkr.hw,
  251. },
  252. .num_parents = 1,
  253. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  254. },
  255. };
  256. static struct clk_alpha_pll_postdiv gpll3_out_main = {
  257. .offset = 0x3000,
  258. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  259. .clkr.hw.init = &(struct clk_init_data){
  260. .name = "gpll3_out_main",
  261. .parent_hws = (const struct clk_hw*[]) {
  262. &gpll3.clkr.hw,
  263. },
  264. .num_parents = 1,
  265. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  266. },
  267. };
  268. static struct clk_alpha_pll_postdiv gpll3_out_odd = {
  269. .offset = 0x3000,
  270. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  271. .clkr.hw.init = &(struct clk_init_data){
  272. .name = "gpll3_out_odd",
  273. .parent_hws = (const struct clk_hw*[]) {
  274. &gpll3.clkr.hw,
  275. },
  276. .num_parents = 1,
  277. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  278. },
  279. };
  280. static struct clk_alpha_pll_postdiv gpll3_out_test = {
  281. .offset = 0x3000,
  282. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  283. .clkr.hw.init = &(struct clk_init_data){
  284. .name = "gpll3_out_test",
  285. .parent_hws = (const struct clk_hw*[]) {
  286. &gpll3.clkr.hw,
  287. },
  288. .num_parents = 1,
  289. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  290. },
  291. };
  292. static struct clk_alpha_pll gpll4 = {
  293. .offset = 0x77000,
  294. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  295. .vco_table = fabia_vco,
  296. .num_vco = ARRAY_SIZE(fabia_vco),
  297. .clkr = {
  298. .enable_reg = 0x52000,
  299. .enable_mask = BIT(4),
  300. .hw.init = &(struct clk_init_data){
  301. .name = "gpll4",
  302. .parent_data = (const struct clk_parent_data []) {
  303. { .fw_name = "xo" },
  304. },
  305. .num_parents = 1,
  306. .ops = &clk_alpha_pll_fixed_fabia_ops,
  307. }
  308. },
  309. };
  310. static struct clk_alpha_pll_postdiv gpll4_out_even = {
  311. .offset = 0x77000,
  312. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  313. .clkr.hw.init = &(struct clk_init_data){
  314. .name = "gpll4_out_even",
  315. .parent_hws = (const struct clk_hw*[]) {
  316. &gpll4.clkr.hw,
  317. },
  318. .num_parents = 1,
  319. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  320. },
  321. };
  322. static struct clk_alpha_pll_postdiv gpll4_out_main = {
  323. .offset = 0x77000,
  324. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  325. .clkr.hw.init = &(struct clk_init_data){
  326. .name = "gpll4_out_main",
  327. .parent_hws = (const struct clk_hw*[]) {
  328. &gpll4.clkr.hw,
  329. },
  330. .num_parents = 1,
  331. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  332. },
  333. };
  334. static struct clk_alpha_pll_postdiv gpll4_out_odd = {
  335. .offset = 0x77000,
  336. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  337. .clkr.hw.init = &(struct clk_init_data){
  338. .name = "gpll4_out_odd",
  339. .parent_hws = (const struct clk_hw*[]) {
  340. &gpll4.clkr.hw,
  341. },
  342. .num_parents = 1,
  343. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  344. },
  345. };
  346. static struct clk_alpha_pll_postdiv gpll4_out_test = {
  347. .offset = 0x77000,
  348. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  349. .clkr.hw.init = &(struct clk_init_data){
  350. .name = "gpll4_out_test",
  351. .parent_hws = (const struct clk_hw*[]) {
  352. &gpll4.clkr.hw,
  353. },
  354. .num_parents = 1,
  355. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  356. },
  357. };
  358. enum {
  359. P_AUD_REF_CLK,
  360. P_CORE_BI_PLL_TEST_SE,
  361. P_GPLL0_OUT_MAIN,
  362. P_GPLL4_OUT_MAIN,
  363. P_PLL0_EARLY_DIV_CLK_SRC,
  364. P_SLEEP_CLK,
  365. P_XO,
  366. };
  367. static const struct parent_map gcc_parent_map_0[] = {
  368. { P_XO, 0 },
  369. { P_GPLL0_OUT_MAIN, 1 },
  370. { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  371. { P_CORE_BI_PLL_TEST_SE, 7 },
  372. };
  373. static const struct clk_parent_data gcc_parent_data_0[] = {
  374. { .fw_name = "xo" },
  375. { .hw = &gpll0_out_main.clkr.hw },
  376. { .hw = &gpll0_out_main.clkr.hw },
  377. { .fw_name = "core_bi_pll_test_se" },
  378. };
  379. static const struct parent_map gcc_parent_map_1[] = {
  380. { P_XO, 0 },
  381. { P_GPLL0_OUT_MAIN, 1 },
  382. { P_CORE_BI_PLL_TEST_SE, 7 },
  383. };
  384. static const struct clk_parent_data gcc_parent_data_1[] = {
  385. { .fw_name = "xo" },
  386. { .hw = &gpll0_out_main.clkr.hw },
  387. { .fw_name = "core_bi_pll_test_se" },
  388. };
  389. static const struct parent_map gcc_parent_map_2[] = {
  390. { P_XO, 0 },
  391. { P_GPLL0_OUT_MAIN, 1 },
  392. { P_SLEEP_CLK, 5 },
  393. { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  394. { P_CORE_BI_PLL_TEST_SE, 7 },
  395. };
  396. static const struct clk_parent_data gcc_parent_data_2[] = {
  397. { .fw_name = "xo" },
  398. { .hw = &gpll0_out_main.clkr.hw },
  399. { .fw_name = "sleep_clk" },
  400. { .hw = &gpll0_out_main.clkr.hw },
  401. { .fw_name = "core_bi_pll_test_se" },
  402. };
  403. static const struct parent_map gcc_parent_map_3[] = {
  404. { P_XO, 0 },
  405. { P_SLEEP_CLK, 5 },
  406. { P_CORE_BI_PLL_TEST_SE, 7 },
  407. };
  408. static const struct clk_parent_data gcc_parent_data_3[] = {
  409. { .fw_name = "xo" },
  410. { .fw_name = "sleep_clk" },
  411. { .fw_name = "core_bi_pll_test_se" },
  412. };
  413. static const struct parent_map gcc_parent_map_4[] = {
  414. { P_XO, 0 },
  415. { P_GPLL0_OUT_MAIN, 1 },
  416. { P_GPLL4_OUT_MAIN, 5 },
  417. { P_CORE_BI_PLL_TEST_SE, 7 },
  418. };
  419. static const struct clk_parent_data gcc_parent_data_4[] = {
  420. { .fw_name = "xo" },
  421. { .hw = &gpll0_out_main.clkr.hw },
  422. { .hw = &gpll4_out_main.clkr.hw },
  423. { .fw_name = "core_bi_pll_test_se" },
  424. };
  425. static const struct parent_map gcc_parent_map_5[] = {
  426. { P_XO, 0 },
  427. { P_GPLL0_OUT_MAIN, 1 },
  428. { P_AUD_REF_CLK, 2 },
  429. { P_CORE_BI_PLL_TEST_SE, 7 },
  430. };
  431. static const struct clk_parent_data gcc_parent_data_5[] = {
  432. { .fw_name = "xo" },
  433. { .hw = &gpll0_out_main.clkr.hw },
  434. { .fw_name = "aud_ref_clk" },
  435. { .fw_name = "core_bi_pll_test_se" },
  436. };
  437. static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
  438. F(19200000, P_XO, 1, 0, 0),
  439. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  440. { }
  441. };
  442. static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
  443. .cmd_rcgr = 0x19020,
  444. .mnd_width = 0,
  445. .hid_width = 5,
  446. .parent_map = gcc_parent_map_1,
  447. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  448. .clkr.hw.init = &(struct clk_init_data){
  449. .name = "blsp1_qup1_i2c_apps_clk_src",
  450. .parent_data = gcc_parent_data_1,
  451. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  452. .ops = &clk_rcg2_ops,
  453. },
  454. };
  455. static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
  456. F(960000, P_XO, 10, 1, 2),
  457. F(4800000, P_XO, 4, 0, 0),
  458. F(9600000, P_XO, 2, 0, 0),
  459. F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
  460. F(19200000, P_XO, 1, 0, 0),
  461. F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
  462. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  463. { }
  464. };
  465. static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
  466. .cmd_rcgr = 0x1900c,
  467. .mnd_width = 8,
  468. .hid_width = 5,
  469. .parent_map = gcc_parent_map_0,
  470. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  471. .clkr.hw.init = &(struct clk_init_data){
  472. .name = "blsp1_qup1_spi_apps_clk_src",
  473. .parent_data = gcc_parent_data_0,
  474. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  475. .ops = &clk_rcg2_ops,
  476. },
  477. };
  478. static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
  479. .cmd_rcgr = 0x1b020,
  480. .mnd_width = 0,
  481. .hid_width = 5,
  482. .parent_map = gcc_parent_map_1,
  483. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  484. .clkr.hw.init = &(struct clk_init_data){
  485. .name = "blsp1_qup2_i2c_apps_clk_src",
  486. .parent_data = gcc_parent_data_1,
  487. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  488. .ops = &clk_rcg2_ops,
  489. },
  490. };
  491. static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
  492. .cmd_rcgr = 0x1b00c,
  493. .mnd_width = 8,
  494. .hid_width = 5,
  495. .parent_map = gcc_parent_map_0,
  496. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  497. .clkr.hw.init = &(struct clk_init_data){
  498. .name = "blsp1_qup2_spi_apps_clk_src",
  499. .parent_data = gcc_parent_data_0,
  500. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  501. .ops = &clk_rcg2_ops,
  502. },
  503. };
  504. static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
  505. .cmd_rcgr = 0x1d020,
  506. .mnd_width = 0,
  507. .hid_width = 5,
  508. .parent_map = gcc_parent_map_1,
  509. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  510. .clkr.hw.init = &(struct clk_init_data){
  511. .name = "blsp1_qup3_i2c_apps_clk_src",
  512. .parent_data = gcc_parent_data_1,
  513. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  514. .ops = &clk_rcg2_ops,
  515. },
  516. };
  517. static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
  518. .cmd_rcgr = 0x1d00c,
  519. .mnd_width = 8,
  520. .hid_width = 5,
  521. .parent_map = gcc_parent_map_0,
  522. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  523. .clkr.hw.init = &(struct clk_init_data){
  524. .name = "blsp1_qup3_spi_apps_clk_src",
  525. .parent_data = gcc_parent_data_0,
  526. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  527. .ops = &clk_rcg2_ops,
  528. },
  529. };
  530. static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
  531. .cmd_rcgr = 0x1f020,
  532. .mnd_width = 0,
  533. .hid_width = 5,
  534. .parent_map = gcc_parent_map_1,
  535. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  536. .clkr.hw.init = &(struct clk_init_data){
  537. .name = "blsp1_qup4_i2c_apps_clk_src",
  538. .parent_data = gcc_parent_data_1,
  539. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  540. .ops = &clk_rcg2_ops,
  541. },
  542. };
  543. static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
  544. .cmd_rcgr = 0x1f00c,
  545. .mnd_width = 8,
  546. .hid_width = 5,
  547. .parent_map = gcc_parent_map_0,
  548. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  549. .clkr.hw.init = &(struct clk_init_data){
  550. .name = "blsp1_qup4_spi_apps_clk_src",
  551. .parent_data = gcc_parent_data_0,
  552. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  553. .ops = &clk_rcg2_ops,
  554. },
  555. };
  556. static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
  557. .cmd_rcgr = 0x21020,
  558. .mnd_width = 0,
  559. .hid_width = 5,
  560. .parent_map = gcc_parent_map_1,
  561. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  562. .clkr.hw.init = &(struct clk_init_data){
  563. .name = "blsp1_qup5_i2c_apps_clk_src",
  564. .parent_data = gcc_parent_data_1,
  565. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  566. .ops = &clk_rcg2_ops,
  567. },
  568. };
  569. static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
  570. .cmd_rcgr = 0x2100c,
  571. .mnd_width = 8,
  572. .hid_width = 5,
  573. .parent_map = gcc_parent_map_0,
  574. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  575. .clkr.hw.init = &(struct clk_init_data){
  576. .name = "blsp1_qup5_spi_apps_clk_src",
  577. .parent_data = gcc_parent_data_0,
  578. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  579. .ops = &clk_rcg2_ops,
  580. },
  581. };
  582. static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
  583. .cmd_rcgr = 0x23020,
  584. .mnd_width = 0,
  585. .hid_width = 5,
  586. .parent_map = gcc_parent_map_1,
  587. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  588. .clkr.hw.init = &(struct clk_init_data){
  589. .name = "blsp1_qup6_i2c_apps_clk_src",
  590. .parent_data = gcc_parent_data_1,
  591. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  592. .ops = &clk_rcg2_ops,
  593. },
  594. };
  595. static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
  596. .cmd_rcgr = 0x2300c,
  597. .mnd_width = 8,
  598. .hid_width = 5,
  599. .parent_map = gcc_parent_map_0,
  600. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  601. .clkr.hw.init = &(struct clk_init_data){
  602. .name = "blsp1_qup6_spi_apps_clk_src",
  603. .parent_data = gcc_parent_data_0,
  604. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  605. .ops = &clk_rcg2_ops,
  606. },
  607. };
  608. static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
  609. F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
  610. F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
  611. F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
  612. F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
  613. F(19200000, P_XO, 1, 0, 0),
  614. F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
  615. F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
  616. F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
  617. F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
  618. F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
  619. F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
  620. F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
  621. F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
  622. F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
  623. F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
  624. { }
  625. };
  626. static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
  627. .cmd_rcgr = 0x1a00c,
  628. .mnd_width = 16,
  629. .hid_width = 5,
  630. .parent_map = gcc_parent_map_0,
  631. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  632. .clkr.hw.init = &(struct clk_init_data){
  633. .name = "blsp1_uart1_apps_clk_src",
  634. .parent_data = gcc_parent_data_0,
  635. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  636. .ops = &clk_rcg2_ops,
  637. },
  638. };
  639. static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
  640. .cmd_rcgr = 0x1c00c,
  641. .mnd_width = 16,
  642. .hid_width = 5,
  643. .parent_map = gcc_parent_map_0,
  644. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  645. .clkr.hw.init = &(struct clk_init_data){
  646. .name = "blsp1_uart2_apps_clk_src",
  647. .parent_data = gcc_parent_data_0,
  648. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  649. .ops = &clk_rcg2_ops,
  650. },
  651. };
  652. static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
  653. .cmd_rcgr = 0x1e00c,
  654. .mnd_width = 16,
  655. .hid_width = 5,
  656. .parent_map = gcc_parent_map_0,
  657. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  658. .clkr.hw.init = &(struct clk_init_data){
  659. .name = "blsp1_uart3_apps_clk_src",
  660. .parent_data = gcc_parent_data_0,
  661. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  662. .ops = &clk_rcg2_ops,
  663. },
  664. };
  665. static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
  666. .cmd_rcgr = 0x26020,
  667. .mnd_width = 0,
  668. .hid_width = 5,
  669. .parent_map = gcc_parent_map_1,
  670. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  671. .clkr.hw.init = &(struct clk_init_data){
  672. .name = "blsp2_qup1_i2c_apps_clk_src",
  673. .parent_data = gcc_parent_data_1,
  674. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  675. .ops = &clk_rcg2_ops,
  676. },
  677. };
  678. static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
  679. .cmd_rcgr = 0x2600c,
  680. .mnd_width = 8,
  681. .hid_width = 5,
  682. .parent_map = gcc_parent_map_0,
  683. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  684. .clkr.hw.init = &(struct clk_init_data){
  685. .name = "blsp2_qup1_spi_apps_clk_src",
  686. .parent_data = gcc_parent_data_0,
  687. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  688. .ops = &clk_rcg2_ops,
  689. },
  690. };
  691. static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
  692. .cmd_rcgr = 0x28020,
  693. .mnd_width = 0,
  694. .hid_width = 5,
  695. .parent_map = gcc_parent_map_1,
  696. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  697. .clkr.hw.init = &(struct clk_init_data){
  698. .name = "blsp2_qup2_i2c_apps_clk_src",
  699. .parent_data = gcc_parent_data_1,
  700. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  701. .ops = &clk_rcg2_ops,
  702. },
  703. };
  704. static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
  705. .cmd_rcgr = 0x2800c,
  706. .mnd_width = 8,
  707. .hid_width = 5,
  708. .parent_map = gcc_parent_map_0,
  709. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  710. .clkr.hw.init = &(struct clk_init_data){
  711. .name = "blsp2_qup2_spi_apps_clk_src",
  712. .parent_data = gcc_parent_data_0,
  713. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  714. .ops = &clk_rcg2_ops,
  715. },
  716. };
  717. static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
  718. .cmd_rcgr = 0x2a020,
  719. .mnd_width = 0,
  720. .hid_width = 5,
  721. .parent_map = gcc_parent_map_1,
  722. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  723. .clkr.hw.init = &(struct clk_init_data){
  724. .name = "blsp2_qup3_i2c_apps_clk_src",
  725. .parent_data = gcc_parent_data_1,
  726. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  727. .ops = &clk_rcg2_ops,
  728. },
  729. };
  730. static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
  731. .cmd_rcgr = 0x2a00c,
  732. .mnd_width = 8,
  733. .hid_width = 5,
  734. .parent_map = gcc_parent_map_0,
  735. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  736. .clkr.hw.init = &(struct clk_init_data){
  737. .name = "blsp2_qup3_spi_apps_clk_src",
  738. .parent_data = gcc_parent_data_0,
  739. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  740. .ops = &clk_rcg2_ops,
  741. },
  742. };
  743. static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
  744. .cmd_rcgr = 0x2c020,
  745. .mnd_width = 0,
  746. .hid_width = 5,
  747. .parent_map = gcc_parent_map_1,
  748. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  749. .clkr.hw.init = &(struct clk_init_data){
  750. .name = "blsp2_qup4_i2c_apps_clk_src",
  751. .parent_data = gcc_parent_data_1,
  752. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  753. .ops = &clk_rcg2_ops,
  754. },
  755. };
  756. static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
  757. .cmd_rcgr = 0x2c00c,
  758. .mnd_width = 8,
  759. .hid_width = 5,
  760. .parent_map = gcc_parent_map_0,
  761. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  762. .clkr.hw.init = &(struct clk_init_data){
  763. .name = "blsp2_qup4_spi_apps_clk_src",
  764. .parent_data = gcc_parent_data_0,
  765. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  766. .ops = &clk_rcg2_ops,
  767. },
  768. };
  769. static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
  770. .cmd_rcgr = 0x2e020,
  771. .mnd_width = 0,
  772. .hid_width = 5,
  773. .parent_map = gcc_parent_map_1,
  774. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  775. .clkr.hw.init = &(struct clk_init_data){
  776. .name = "blsp2_qup5_i2c_apps_clk_src",
  777. .parent_data = gcc_parent_data_1,
  778. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  779. .ops = &clk_rcg2_ops,
  780. },
  781. };
  782. static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
  783. .cmd_rcgr = 0x2e00c,
  784. .mnd_width = 8,
  785. .hid_width = 5,
  786. .parent_map = gcc_parent_map_0,
  787. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  788. .clkr.hw.init = &(struct clk_init_data){
  789. .name = "blsp2_qup5_spi_apps_clk_src",
  790. .parent_data = gcc_parent_data_0,
  791. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  792. .ops = &clk_rcg2_ops,
  793. },
  794. };
  795. static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
  796. .cmd_rcgr = 0x30020,
  797. .mnd_width = 0,
  798. .hid_width = 5,
  799. .parent_map = gcc_parent_map_1,
  800. .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
  801. .clkr.hw.init = &(struct clk_init_data){
  802. .name = "blsp2_qup6_i2c_apps_clk_src",
  803. .parent_data = gcc_parent_data_1,
  804. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  805. .ops = &clk_rcg2_ops,
  806. },
  807. };
  808. static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
  809. .cmd_rcgr = 0x3000c,
  810. .mnd_width = 8,
  811. .hid_width = 5,
  812. .parent_map = gcc_parent_map_0,
  813. .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
  814. .clkr.hw.init = &(struct clk_init_data){
  815. .name = "blsp2_qup6_spi_apps_clk_src",
  816. .parent_data = gcc_parent_data_0,
  817. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  818. .ops = &clk_rcg2_ops,
  819. },
  820. };
  821. static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
  822. .cmd_rcgr = 0x2700c,
  823. .mnd_width = 16,
  824. .hid_width = 5,
  825. .parent_map = gcc_parent_map_0,
  826. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  827. .clkr.hw.init = &(struct clk_init_data){
  828. .name = "blsp2_uart1_apps_clk_src",
  829. .parent_data = gcc_parent_data_0,
  830. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  831. .ops = &clk_rcg2_ops,
  832. },
  833. };
  834. static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
  835. .cmd_rcgr = 0x2900c,
  836. .mnd_width = 16,
  837. .hid_width = 5,
  838. .parent_map = gcc_parent_map_0,
  839. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  840. .clkr.hw.init = &(struct clk_init_data){
  841. .name = "blsp2_uart2_apps_clk_src",
  842. .parent_data = gcc_parent_data_0,
  843. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  844. .ops = &clk_rcg2_ops,
  845. },
  846. };
  847. static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
  848. .cmd_rcgr = 0x2b00c,
  849. .mnd_width = 16,
  850. .hid_width = 5,
  851. .parent_map = gcc_parent_map_0,
  852. .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
  853. .clkr.hw.init = &(struct clk_init_data){
  854. .name = "blsp2_uart3_apps_clk_src",
  855. .parent_data = gcc_parent_data_0,
  856. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  857. .ops = &clk_rcg2_ops,
  858. },
  859. };
  860. static const struct freq_tbl ftbl_gp1_clk_src[] = {
  861. F(19200000, P_XO, 1, 0, 0),
  862. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  863. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  864. { }
  865. };
  866. static struct clk_rcg2 gp1_clk_src = {
  867. .cmd_rcgr = 0x64004,
  868. .mnd_width = 8,
  869. .hid_width = 5,
  870. .parent_map = gcc_parent_map_2,
  871. .freq_tbl = ftbl_gp1_clk_src,
  872. .clkr.hw.init = &(struct clk_init_data){
  873. .name = "gp1_clk_src",
  874. .parent_data = gcc_parent_data_2,
  875. .num_parents = ARRAY_SIZE(gcc_parent_data_2),
  876. .ops = &clk_rcg2_ops,
  877. },
  878. };
  879. static struct clk_rcg2 gp2_clk_src = {
  880. .cmd_rcgr = 0x65004,
  881. .mnd_width = 8,
  882. .hid_width = 5,
  883. .parent_map = gcc_parent_map_2,
  884. .freq_tbl = ftbl_gp1_clk_src,
  885. .clkr.hw.init = &(struct clk_init_data){
  886. .name = "gp2_clk_src",
  887. .parent_data = gcc_parent_data_2,
  888. .num_parents = ARRAY_SIZE(gcc_parent_data_2),
  889. .ops = &clk_rcg2_ops,
  890. },
  891. };
  892. static struct clk_rcg2 gp3_clk_src = {
  893. .cmd_rcgr = 0x66004,
  894. .mnd_width = 8,
  895. .hid_width = 5,
  896. .parent_map = gcc_parent_map_2,
  897. .freq_tbl = ftbl_gp1_clk_src,
  898. .clkr.hw.init = &(struct clk_init_data){
  899. .name = "gp3_clk_src",
  900. .parent_data = gcc_parent_data_2,
  901. .num_parents = ARRAY_SIZE(gcc_parent_data_2),
  902. .ops = &clk_rcg2_ops,
  903. },
  904. };
  905. static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
  906. F(19200000, P_XO, 1, 0, 0),
  907. F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
  908. F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
  909. { }
  910. };
  911. static struct clk_rcg2 hmss_ahb_clk_src = {
  912. .cmd_rcgr = 0x48014,
  913. .mnd_width = 0,
  914. .hid_width = 5,
  915. .parent_map = gcc_parent_map_1,
  916. .freq_tbl = ftbl_hmss_ahb_clk_src,
  917. .clkr.hw.init = &(struct clk_init_data){
  918. .name = "hmss_ahb_clk_src",
  919. .parent_data = gcc_parent_data_1,
  920. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  921. .ops = &clk_rcg2_ops,
  922. },
  923. };
  924. static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
  925. F(19200000, P_XO, 1, 0, 0),
  926. { }
  927. };
  928. static struct clk_rcg2 hmss_rbcpr_clk_src = {
  929. .cmd_rcgr = 0x48044,
  930. .mnd_width = 0,
  931. .hid_width = 5,
  932. .parent_map = gcc_parent_map_1,
  933. .freq_tbl = ftbl_hmss_rbcpr_clk_src,
  934. .clkr.hw.init = &(struct clk_init_data){
  935. .name = "hmss_rbcpr_clk_src",
  936. .parent_data = gcc_parent_data_1,
  937. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  938. .ops = &clk_rcg2_ops,
  939. },
  940. };
  941. static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
  942. F(1010526, P_XO, 1, 1, 19),
  943. { }
  944. };
  945. static struct clk_rcg2 pcie_aux_clk_src = {
  946. .cmd_rcgr = 0x6c000,
  947. .mnd_width = 16,
  948. .hid_width = 5,
  949. .parent_map = gcc_parent_map_3,
  950. .freq_tbl = ftbl_pcie_aux_clk_src,
  951. .clkr.hw.init = &(struct clk_init_data){
  952. .name = "pcie_aux_clk_src",
  953. .parent_data = gcc_parent_data_3,
  954. .num_parents = ARRAY_SIZE(gcc_parent_data_3),
  955. .ops = &clk_rcg2_ops,
  956. },
  957. };
  958. static const struct freq_tbl ftbl_pdm2_clk_src[] = {
  959. F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
  960. { }
  961. };
  962. static struct clk_rcg2 pdm2_clk_src = {
  963. .cmd_rcgr = 0x33010,
  964. .mnd_width = 0,
  965. .hid_width = 5,
  966. .parent_map = gcc_parent_map_1,
  967. .freq_tbl = ftbl_pdm2_clk_src,
  968. .clkr.hw.init = &(struct clk_init_data){
  969. .name = "pdm2_clk_src",
  970. .parent_data = gcc_parent_data_1,
  971. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  972. .ops = &clk_rcg2_ops,
  973. },
  974. };
  975. static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
  976. F(144000, P_XO, 16, 3, 25),
  977. F(400000, P_XO, 12, 1, 4),
  978. F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
  979. F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
  980. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  981. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  982. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  983. { }
  984. };
  985. static struct clk_rcg2 sdcc2_apps_clk_src = {
  986. .cmd_rcgr = 0x14010,
  987. .mnd_width = 8,
  988. .hid_width = 5,
  989. .parent_map = gcc_parent_map_4,
  990. .freq_tbl = ftbl_sdcc2_apps_clk_src,
  991. .clkr.hw.init = &(struct clk_init_data){
  992. .name = "sdcc2_apps_clk_src",
  993. .parent_data = gcc_parent_data_4,
  994. .num_parents = ARRAY_SIZE(gcc_parent_data_4),
  995. .ops = &clk_rcg2_floor_ops,
  996. },
  997. };
  998. static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
  999. F(144000, P_XO, 16, 3, 25),
  1000. F(400000, P_XO, 12, 1, 4),
  1001. F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
  1002. F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
  1003. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  1004. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  1005. { }
  1006. };
  1007. static struct clk_rcg2 sdcc4_apps_clk_src = {
  1008. .cmd_rcgr = 0x16010,
  1009. .mnd_width = 8,
  1010. .hid_width = 5,
  1011. .parent_map = gcc_parent_map_1,
  1012. .freq_tbl = ftbl_sdcc4_apps_clk_src,
  1013. .clkr.hw.init = &(struct clk_init_data){
  1014. .name = "sdcc4_apps_clk_src",
  1015. .parent_data = gcc_parent_data_1,
  1016. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  1017. .ops = &clk_rcg2_floor_ops,
  1018. },
  1019. };
  1020. static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
  1021. F(105495, P_XO, 1, 1, 182),
  1022. { }
  1023. };
  1024. static struct clk_rcg2 tsif_ref_clk_src = {
  1025. .cmd_rcgr = 0x36010,
  1026. .mnd_width = 8,
  1027. .hid_width = 5,
  1028. .parent_map = gcc_parent_map_5,
  1029. .freq_tbl = ftbl_tsif_ref_clk_src,
  1030. .clkr.hw.init = &(struct clk_init_data){
  1031. .name = "tsif_ref_clk_src",
  1032. .parent_data = gcc_parent_data_5,
  1033. .num_parents = ARRAY_SIZE(gcc_parent_data_5),
  1034. .ops = &clk_rcg2_ops,
  1035. },
  1036. };
  1037. static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
  1038. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  1039. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  1040. F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
  1041. { }
  1042. };
  1043. static struct clk_rcg2 ufs_axi_clk_src = {
  1044. .cmd_rcgr = 0x75018,
  1045. .mnd_width = 8,
  1046. .hid_width = 5,
  1047. .parent_map = gcc_parent_map_0,
  1048. .freq_tbl = ftbl_ufs_axi_clk_src,
  1049. .clkr.hw.init = &(struct clk_init_data){
  1050. .name = "ufs_axi_clk_src",
  1051. .parent_data = gcc_parent_data_0,
  1052. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  1053. .ops = &clk_rcg2_ops,
  1054. },
  1055. };
  1056. static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
  1057. F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
  1058. F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
  1059. F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
  1060. { }
  1061. };
  1062. static struct clk_rcg2 ufs_unipro_core_clk_src = {
  1063. .cmd_rcgr = 0x76028,
  1064. .mnd_width = 8,
  1065. .hid_width = 5,
  1066. .parent_map = gcc_parent_map_0,
  1067. .freq_tbl = ftbl_ufs_unipro_core_clk_src,
  1068. .clkr.hw.init = &(struct clk_init_data){
  1069. .name = "ufs_unipro_core_clk_src",
  1070. .parent_data = gcc_parent_data_0,
  1071. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  1072. .ops = &clk_rcg2_ops,
  1073. },
  1074. };
  1075. static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
  1076. F(19200000, P_XO, 1, 0, 0),
  1077. F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
  1078. F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
  1079. F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
  1080. { }
  1081. };
  1082. static struct clk_rcg2 usb30_master_clk_src = {
  1083. .cmd_rcgr = 0xf014,
  1084. .mnd_width = 8,
  1085. .hid_width = 5,
  1086. .parent_map = gcc_parent_map_0,
  1087. .freq_tbl = ftbl_usb30_master_clk_src,
  1088. .clkr.hw.init = &(struct clk_init_data){
  1089. .name = "usb30_master_clk_src",
  1090. .parent_data = gcc_parent_data_0,
  1091. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  1092. .ops = &clk_rcg2_ops,
  1093. },
  1094. };
  1095. static struct clk_rcg2 usb30_mock_utmi_clk_src = {
  1096. .cmd_rcgr = 0xf028,
  1097. .mnd_width = 0,
  1098. .hid_width = 5,
  1099. .parent_map = gcc_parent_map_0,
  1100. .freq_tbl = ftbl_hmss_rbcpr_clk_src,
  1101. .clkr.hw.init = &(struct clk_init_data){
  1102. .name = "usb30_mock_utmi_clk_src",
  1103. .parent_data = gcc_parent_data_0,
  1104. .num_parents = ARRAY_SIZE(gcc_parent_data_0),
  1105. .ops = &clk_rcg2_ops,
  1106. },
  1107. };
  1108. static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
  1109. F(1200000, P_XO, 16, 0, 0),
  1110. { }
  1111. };
  1112. static struct clk_rcg2 usb3_phy_aux_clk_src = {
  1113. .cmd_rcgr = 0x5000c,
  1114. .mnd_width = 0,
  1115. .hid_width = 5,
  1116. .parent_map = gcc_parent_map_3,
  1117. .freq_tbl = ftbl_usb3_phy_aux_clk_src,
  1118. .clkr.hw.init = &(struct clk_init_data){
  1119. .name = "usb3_phy_aux_clk_src",
  1120. .parent_data = gcc_parent_data_3,
  1121. .num_parents = ARRAY_SIZE(gcc_parent_data_3),
  1122. .ops = &clk_rcg2_ops,
  1123. },
  1124. };
  1125. static struct clk_branch gcc_aggre1_noc_xo_clk = {
  1126. .halt_reg = 0x8202c,
  1127. .halt_check = BRANCH_HALT,
  1128. .clkr = {
  1129. .enable_reg = 0x8202c,
  1130. .enable_mask = BIT(0),
  1131. .hw.init = &(struct clk_init_data){
  1132. .name = "gcc_aggre1_noc_xo_clk",
  1133. .ops = &clk_branch2_ops,
  1134. },
  1135. },
  1136. };
  1137. static struct clk_branch gcc_aggre1_ufs_axi_clk = {
  1138. .halt_reg = 0x82028,
  1139. .halt_check = BRANCH_HALT,
  1140. .clkr = {
  1141. .enable_reg = 0x82028,
  1142. .enable_mask = BIT(0),
  1143. .hw.init = &(struct clk_init_data){
  1144. .name = "gcc_aggre1_ufs_axi_clk",
  1145. .parent_hws = (const struct clk_hw *[]) {
  1146. &ufs_axi_clk_src.clkr.hw,
  1147. },
  1148. .num_parents = 1,
  1149. .flags = CLK_SET_RATE_PARENT,
  1150. .ops = &clk_branch2_ops,
  1151. },
  1152. },
  1153. };
  1154. static struct clk_branch gcc_aggre1_usb3_axi_clk = {
  1155. .halt_reg = 0x82024,
  1156. .halt_check = BRANCH_HALT,
  1157. .clkr = {
  1158. .enable_reg = 0x82024,
  1159. .enable_mask = BIT(0),
  1160. .hw.init = &(struct clk_init_data){
  1161. .name = "gcc_aggre1_usb3_axi_clk",
  1162. .parent_hws = (const struct clk_hw *[]) {
  1163. &usb30_master_clk_src.clkr.hw,
  1164. },
  1165. .num_parents = 1,
  1166. .flags = CLK_SET_RATE_PARENT,
  1167. .ops = &clk_branch2_ops,
  1168. },
  1169. },
  1170. };
  1171. static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
  1172. .halt_reg = 0x48090,
  1173. .halt_check = BRANCH_HALT,
  1174. .clkr = {
  1175. .enable_reg = 0x48090,
  1176. .enable_mask = BIT(0),
  1177. .hw.init = &(struct clk_init_data){
  1178. .name = "gcc_apss_qdss_tsctr_div2_clk",
  1179. .ops = &clk_branch2_ops,
  1180. },
  1181. },
  1182. };
  1183. static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
  1184. .halt_reg = 0x48094,
  1185. .halt_check = BRANCH_HALT,
  1186. .clkr = {
  1187. .enable_reg = 0x48094,
  1188. .enable_mask = BIT(0),
  1189. .hw.init = &(struct clk_init_data){
  1190. .name = "gcc_apss_qdss_tsctr_div8_clk",
  1191. .ops = &clk_branch2_ops,
  1192. },
  1193. },
  1194. };
  1195. static struct clk_branch gcc_bimc_hmss_axi_clk = {
  1196. .halt_reg = 0x48004,
  1197. .halt_check = BRANCH_HALT_VOTED,
  1198. .clkr = {
  1199. .enable_reg = 0x52004,
  1200. .enable_mask = BIT(22),
  1201. .hw.init = &(struct clk_init_data){
  1202. .name = "gcc_bimc_hmss_axi_clk",
  1203. .ops = &clk_branch2_ops,
  1204. },
  1205. },
  1206. };
  1207. static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
  1208. .halt_reg = 0x4401c,
  1209. .halt_check = BRANCH_HALT,
  1210. .clkr = {
  1211. .enable_reg = 0x4401c,
  1212. .enable_mask = BIT(0),
  1213. .hw.init = &(struct clk_init_data){
  1214. .name = "gcc_bimc_mss_q6_axi_clk",
  1215. .ops = &clk_branch2_ops,
  1216. },
  1217. },
  1218. };
  1219. static struct clk_branch gcc_mss_cfg_ahb_clk = {
  1220. .halt_reg = 0x8a000,
  1221. .halt_check = BRANCH_HALT,
  1222. .clkr = {
  1223. .enable_reg = 0x8a000,
  1224. .enable_mask = BIT(0),
  1225. .hw.init = &(struct clk_init_data){
  1226. .name = "gcc_mss_cfg_ahb_clk",
  1227. .ops = &clk_branch2_ops,
  1228. },
  1229. },
  1230. };
  1231. static struct clk_branch gcc_mss_snoc_axi_clk = {
  1232. .halt_reg = 0x8a03c,
  1233. .halt_check = BRANCH_HALT,
  1234. .clkr = {
  1235. .enable_reg = 0x8a03c,
  1236. .enable_mask = BIT(0),
  1237. .hw.init = &(struct clk_init_data){
  1238. .name = "gcc_mss_snoc_axi_clk",
  1239. .ops = &clk_branch2_ops,
  1240. },
  1241. },
  1242. };
  1243. static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
  1244. .halt_reg = 0x8a004,
  1245. .halt_check = BRANCH_HALT,
  1246. .clkr = {
  1247. .enable_reg = 0x8a004,
  1248. .enable_mask = BIT(0),
  1249. .hw.init = &(struct clk_init_data){
  1250. .name = "gcc_mss_mnoc_bimc_axi_clk",
  1251. .ops = &clk_branch2_ops,
  1252. },
  1253. },
  1254. };
  1255. static struct clk_branch gcc_boot_rom_ahb_clk = {
  1256. .halt_reg = 0x38004,
  1257. .halt_check = BRANCH_HALT_VOTED,
  1258. .hwcg_reg = 0x38004,
  1259. .hwcg_bit = 1,
  1260. .clkr = {
  1261. .enable_reg = 0x52004,
  1262. .enable_mask = BIT(10),
  1263. .hw.init = &(struct clk_init_data){
  1264. .name = "gcc_boot_rom_ahb_clk",
  1265. .ops = &clk_branch2_ops,
  1266. },
  1267. },
  1268. };
  1269. static struct clk_branch gcc_mmss_gpll0_clk = {
  1270. .halt_check = BRANCH_HALT_DELAY,
  1271. .clkr = {
  1272. .enable_reg = 0x5200c,
  1273. .enable_mask = BIT(1),
  1274. .hw.init = &(struct clk_init_data){
  1275. .name = "gcc_mmss_gpll0_clk",
  1276. .parent_hws = (const struct clk_hw *[]) {
  1277. &gpll0_out_main.clkr.hw,
  1278. },
  1279. .num_parents = 1,
  1280. .ops = &clk_branch2_ops,
  1281. },
  1282. },
  1283. };
  1284. static struct clk_branch gcc_mss_gpll0_div_clk_src = {
  1285. .halt_check = BRANCH_HALT_DELAY,
  1286. .clkr = {
  1287. .enable_reg = 0x5200c,
  1288. .enable_mask = BIT(2),
  1289. .hw.init = &(struct clk_init_data){
  1290. .name = "gcc_mss_gpll0_div_clk_src",
  1291. .ops = &clk_branch2_ops,
  1292. },
  1293. },
  1294. };
  1295. static struct clk_branch gcc_blsp1_ahb_clk = {
  1296. .halt_reg = 0x17004,
  1297. .halt_check = BRANCH_HALT_VOTED,
  1298. .clkr = {
  1299. .enable_reg = 0x52004,
  1300. .enable_mask = BIT(17),
  1301. .hw.init = &(struct clk_init_data){
  1302. .name = "gcc_blsp1_ahb_clk",
  1303. .ops = &clk_branch2_ops,
  1304. },
  1305. },
  1306. };
  1307. static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
  1308. .halt_reg = 0x19008,
  1309. .halt_check = BRANCH_HALT,
  1310. .clkr = {
  1311. .enable_reg = 0x19008,
  1312. .enable_mask = BIT(0),
  1313. .hw.init = &(struct clk_init_data){
  1314. .name = "gcc_blsp1_qup1_i2c_apps_clk",
  1315. .parent_hws = (const struct clk_hw *[]) {
  1316. &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
  1317. },
  1318. .num_parents = 1,
  1319. .flags = CLK_SET_RATE_PARENT,
  1320. .ops = &clk_branch2_ops,
  1321. },
  1322. },
  1323. };
  1324. static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
  1325. .halt_reg = 0x19004,
  1326. .halt_check = BRANCH_HALT,
  1327. .clkr = {
  1328. .enable_reg = 0x19004,
  1329. .enable_mask = BIT(0),
  1330. .hw.init = &(struct clk_init_data){
  1331. .name = "gcc_blsp1_qup1_spi_apps_clk",
  1332. .parent_hws = (const struct clk_hw *[]) {
  1333. &blsp1_qup1_spi_apps_clk_src.clkr.hw,
  1334. },
  1335. .num_parents = 1,
  1336. .flags = CLK_SET_RATE_PARENT,
  1337. .ops = &clk_branch2_ops,
  1338. },
  1339. },
  1340. };
  1341. static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
  1342. .halt_reg = 0x1b008,
  1343. .halt_check = BRANCH_HALT,
  1344. .clkr = {
  1345. .enable_reg = 0x1b008,
  1346. .enable_mask = BIT(0),
  1347. .hw.init = &(struct clk_init_data){
  1348. .name = "gcc_blsp1_qup2_i2c_apps_clk",
  1349. .parent_hws = (const struct clk_hw *[]) {
  1350. &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
  1351. },
  1352. .num_parents = 1,
  1353. .flags = CLK_SET_RATE_PARENT,
  1354. .ops = &clk_branch2_ops,
  1355. },
  1356. },
  1357. };
  1358. static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
  1359. .halt_reg = 0x1b004,
  1360. .halt_check = BRANCH_HALT,
  1361. .clkr = {
  1362. .enable_reg = 0x1b004,
  1363. .enable_mask = BIT(0),
  1364. .hw.init = &(struct clk_init_data){
  1365. .name = "gcc_blsp1_qup2_spi_apps_clk",
  1366. .parent_hws = (const struct clk_hw *[]) {
  1367. &blsp1_qup2_spi_apps_clk_src.clkr.hw,
  1368. },
  1369. .num_parents = 1,
  1370. .flags = CLK_SET_RATE_PARENT,
  1371. .ops = &clk_branch2_ops,
  1372. },
  1373. },
  1374. };
  1375. static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
  1376. .halt_reg = 0x1d008,
  1377. .halt_check = BRANCH_HALT,
  1378. .clkr = {
  1379. .enable_reg = 0x1d008,
  1380. .enable_mask = BIT(0),
  1381. .hw.init = &(struct clk_init_data){
  1382. .name = "gcc_blsp1_qup3_i2c_apps_clk",
  1383. .parent_hws = (const struct clk_hw *[]) {
  1384. &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
  1385. },
  1386. .num_parents = 1,
  1387. .flags = CLK_SET_RATE_PARENT,
  1388. .ops = &clk_branch2_ops,
  1389. },
  1390. },
  1391. };
  1392. static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
  1393. .halt_reg = 0x1d004,
  1394. .halt_check = BRANCH_HALT,
  1395. .clkr = {
  1396. .enable_reg = 0x1d004,
  1397. .enable_mask = BIT(0),
  1398. .hw.init = &(struct clk_init_data){
  1399. .name = "gcc_blsp1_qup3_spi_apps_clk",
  1400. .parent_hws = (const struct clk_hw *[]) {
  1401. &blsp1_qup3_spi_apps_clk_src.clkr.hw,
  1402. },
  1403. .num_parents = 1,
  1404. .flags = CLK_SET_RATE_PARENT,
  1405. .ops = &clk_branch2_ops,
  1406. },
  1407. },
  1408. };
  1409. static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
  1410. .halt_reg = 0x1f008,
  1411. .halt_check = BRANCH_HALT,
  1412. .clkr = {
  1413. .enable_reg = 0x1f008,
  1414. .enable_mask = BIT(0),
  1415. .hw.init = &(struct clk_init_data){
  1416. .name = "gcc_blsp1_qup4_i2c_apps_clk",
  1417. .parent_hws = (const struct clk_hw *[]) {
  1418. &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
  1419. },
  1420. .num_parents = 1,
  1421. .flags = CLK_SET_RATE_PARENT,
  1422. .ops = &clk_branch2_ops,
  1423. },
  1424. },
  1425. };
  1426. static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
  1427. .halt_reg = 0x1f004,
  1428. .halt_check = BRANCH_HALT,
  1429. .clkr = {
  1430. .enable_reg = 0x1f004,
  1431. .enable_mask = BIT(0),
  1432. .hw.init = &(struct clk_init_data){
  1433. .name = "gcc_blsp1_qup4_spi_apps_clk",
  1434. .parent_hws = (const struct clk_hw *[]) {
  1435. &blsp1_qup4_spi_apps_clk_src.clkr.hw,
  1436. },
  1437. .num_parents = 1,
  1438. .flags = CLK_SET_RATE_PARENT,
  1439. .ops = &clk_branch2_ops,
  1440. },
  1441. },
  1442. };
  1443. static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
  1444. .halt_reg = 0x21008,
  1445. .halt_check = BRANCH_HALT,
  1446. .clkr = {
  1447. .enable_reg = 0x21008,
  1448. .enable_mask = BIT(0),
  1449. .hw.init = &(struct clk_init_data){
  1450. .name = "gcc_blsp1_qup5_i2c_apps_clk",
  1451. .parent_hws = (const struct clk_hw *[]) {
  1452. &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
  1453. },
  1454. .num_parents = 1,
  1455. .flags = CLK_SET_RATE_PARENT,
  1456. .ops = &clk_branch2_ops,
  1457. },
  1458. },
  1459. };
  1460. static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
  1461. .halt_reg = 0x21004,
  1462. .halt_check = BRANCH_HALT,
  1463. .clkr = {
  1464. .enable_reg = 0x21004,
  1465. .enable_mask = BIT(0),
  1466. .hw.init = &(struct clk_init_data){
  1467. .name = "gcc_blsp1_qup5_spi_apps_clk",
  1468. .parent_hws = (const struct clk_hw *[]) {
  1469. &blsp1_qup5_spi_apps_clk_src.clkr.hw,
  1470. },
  1471. .num_parents = 1,
  1472. .flags = CLK_SET_RATE_PARENT,
  1473. .ops = &clk_branch2_ops,
  1474. },
  1475. },
  1476. };
  1477. static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
  1478. .halt_reg = 0x23008,
  1479. .halt_check = BRANCH_HALT,
  1480. .clkr = {
  1481. .enable_reg = 0x23008,
  1482. .enable_mask = BIT(0),
  1483. .hw.init = &(struct clk_init_data){
  1484. .name = "gcc_blsp1_qup6_i2c_apps_clk",
  1485. .parent_hws = (const struct clk_hw *[]) {
  1486. &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
  1487. },
  1488. .num_parents = 1,
  1489. .flags = CLK_SET_RATE_PARENT,
  1490. .ops = &clk_branch2_ops,
  1491. },
  1492. },
  1493. };
  1494. static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
  1495. .halt_reg = 0x23004,
  1496. .halt_check = BRANCH_HALT,
  1497. .clkr = {
  1498. .enable_reg = 0x23004,
  1499. .enable_mask = BIT(0),
  1500. .hw.init = &(struct clk_init_data){
  1501. .name = "gcc_blsp1_qup6_spi_apps_clk",
  1502. .parent_hws = (const struct clk_hw *[]) {
  1503. &blsp1_qup6_spi_apps_clk_src.clkr.hw,
  1504. },
  1505. .num_parents = 1,
  1506. .flags = CLK_SET_RATE_PARENT,
  1507. .ops = &clk_branch2_ops,
  1508. },
  1509. },
  1510. };
  1511. static struct clk_branch gcc_blsp1_sleep_clk = {
  1512. .halt_reg = 0x17008,
  1513. .halt_check = BRANCH_HALT_VOTED,
  1514. .clkr = {
  1515. .enable_reg = 0x52004,
  1516. .enable_mask = BIT(16),
  1517. .hw.init = &(struct clk_init_data){
  1518. .name = "gcc_blsp1_sleep_clk",
  1519. .ops = &clk_branch2_ops,
  1520. },
  1521. },
  1522. };
  1523. static struct clk_branch gcc_blsp1_uart1_apps_clk = {
  1524. .halt_reg = 0x1a004,
  1525. .halt_check = BRANCH_HALT,
  1526. .clkr = {
  1527. .enable_reg = 0x1a004,
  1528. .enable_mask = BIT(0),
  1529. .hw.init = &(struct clk_init_data){
  1530. .name = "gcc_blsp1_uart1_apps_clk",
  1531. .parent_hws = (const struct clk_hw *[]) {
  1532. &blsp1_uart1_apps_clk_src.clkr.hw,
  1533. },
  1534. .num_parents = 1,
  1535. .flags = CLK_SET_RATE_PARENT,
  1536. .ops = &clk_branch2_ops,
  1537. },
  1538. },
  1539. };
  1540. static struct clk_branch gcc_blsp1_uart2_apps_clk = {
  1541. .halt_reg = 0x1c004,
  1542. .halt_check = BRANCH_HALT,
  1543. .clkr = {
  1544. .enable_reg = 0x1c004,
  1545. .enable_mask = BIT(0),
  1546. .hw.init = &(struct clk_init_data){
  1547. .name = "gcc_blsp1_uart2_apps_clk",
  1548. .parent_hws = (const struct clk_hw *[]) {
  1549. &blsp1_uart2_apps_clk_src.clkr.hw,
  1550. },
  1551. .num_parents = 1,
  1552. .flags = CLK_SET_RATE_PARENT,
  1553. .ops = &clk_branch2_ops,
  1554. },
  1555. },
  1556. };
  1557. static struct clk_branch gcc_blsp1_uart3_apps_clk = {
  1558. .halt_reg = 0x1e004,
  1559. .halt_check = BRANCH_HALT,
  1560. .clkr = {
  1561. .enable_reg = 0x1e004,
  1562. .enable_mask = BIT(0),
  1563. .hw.init = &(struct clk_init_data){
  1564. .name = "gcc_blsp1_uart3_apps_clk",
  1565. .parent_hws = (const struct clk_hw *[]) {
  1566. &blsp1_uart3_apps_clk_src.clkr.hw,
  1567. },
  1568. .num_parents = 1,
  1569. .flags = CLK_SET_RATE_PARENT,
  1570. .ops = &clk_branch2_ops,
  1571. },
  1572. },
  1573. };
  1574. static struct clk_branch gcc_blsp2_ahb_clk = {
  1575. .halt_reg = 0x25004,
  1576. .halt_check = BRANCH_HALT_VOTED,
  1577. .clkr = {
  1578. .enable_reg = 0x52004,
  1579. .enable_mask = BIT(15),
  1580. .hw.init = &(struct clk_init_data){
  1581. .name = "gcc_blsp2_ahb_clk",
  1582. .ops = &clk_branch2_ops,
  1583. },
  1584. },
  1585. };
  1586. static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
  1587. .halt_reg = 0x26008,
  1588. .halt_check = BRANCH_HALT,
  1589. .clkr = {
  1590. .enable_reg = 0x26008,
  1591. .enable_mask = BIT(0),
  1592. .hw.init = &(struct clk_init_data){
  1593. .name = "gcc_blsp2_qup1_i2c_apps_clk",
  1594. .parent_hws = (const struct clk_hw *[]) {
  1595. &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
  1596. },
  1597. .num_parents = 1,
  1598. .flags = CLK_SET_RATE_PARENT,
  1599. .ops = &clk_branch2_ops,
  1600. },
  1601. },
  1602. };
  1603. static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
  1604. .halt_reg = 0x26004,
  1605. .halt_check = BRANCH_HALT,
  1606. .clkr = {
  1607. .enable_reg = 0x26004,
  1608. .enable_mask = BIT(0),
  1609. .hw.init = &(struct clk_init_data){
  1610. .name = "gcc_blsp2_qup1_spi_apps_clk",
  1611. .parent_hws = (const struct clk_hw *[]) {
  1612. &blsp2_qup1_spi_apps_clk_src.clkr.hw,
  1613. },
  1614. .num_parents = 1,
  1615. .flags = CLK_SET_RATE_PARENT,
  1616. .ops = &clk_branch2_ops,
  1617. },
  1618. },
  1619. };
  1620. static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
  1621. .halt_reg = 0x28008,
  1622. .halt_check = BRANCH_HALT,
  1623. .clkr = {
  1624. .enable_reg = 0x28008,
  1625. .enable_mask = BIT(0),
  1626. .hw.init = &(struct clk_init_data){
  1627. .name = "gcc_blsp2_qup2_i2c_apps_clk",
  1628. .parent_hws = (const struct clk_hw *[]) {
  1629. &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
  1630. },
  1631. .num_parents = 1,
  1632. .flags = CLK_SET_RATE_PARENT,
  1633. .ops = &clk_branch2_ops,
  1634. },
  1635. },
  1636. };
  1637. static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
  1638. .halt_reg = 0x28004,
  1639. .halt_check = BRANCH_HALT,
  1640. .clkr = {
  1641. .enable_reg = 0x28004,
  1642. .enable_mask = BIT(0),
  1643. .hw.init = &(struct clk_init_data){
  1644. .name = "gcc_blsp2_qup2_spi_apps_clk",
  1645. .parent_hws = (const struct clk_hw *[]) {
  1646. &blsp2_qup2_spi_apps_clk_src.clkr.hw,
  1647. },
  1648. .num_parents = 1,
  1649. .flags = CLK_SET_RATE_PARENT,
  1650. .ops = &clk_branch2_ops,
  1651. },
  1652. },
  1653. };
  1654. static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
  1655. .halt_reg = 0x2a008,
  1656. .halt_check = BRANCH_HALT,
  1657. .clkr = {
  1658. .enable_reg = 0x2a008,
  1659. .enable_mask = BIT(0),
  1660. .hw.init = &(struct clk_init_data){
  1661. .name = "gcc_blsp2_qup3_i2c_apps_clk",
  1662. .parent_hws = (const struct clk_hw *[]) {
  1663. &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
  1664. },
  1665. .num_parents = 1,
  1666. .flags = CLK_SET_RATE_PARENT,
  1667. .ops = &clk_branch2_ops,
  1668. },
  1669. },
  1670. };
  1671. static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
  1672. .halt_reg = 0x2a004,
  1673. .halt_check = BRANCH_HALT,
  1674. .clkr = {
  1675. .enable_reg = 0x2a004,
  1676. .enable_mask = BIT(0),
  1677. .hw.init = &(struct clk_init_data){
  1678. .name = "gcc_blsp2_qup3_spi_apps_clk",
  1679. .parent_hws = (const struct clk_hw *[]) {
  1680. &blsp2_qup3_spi_apps_clk_src.clkr.hw,
  1681. },
  1682. .num_parents = 1,
  1683. .flags = CLK_SET_RATE_PARENT,
  1684. .ops = &clk_branch2_ops,
  1685. },
  1686. },
  1687. };
  1688. static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
  1689. .halt_reg = 0x2c008,
  1690. .halt_check = BRANCH_HALT,
  1691. .clkr = {
  1692. .enable_reg = 0x2c008,
  1693. .enable_mask = BIT(0),
  1694. .hw.init = &(struct clk_init_data){
  1695. .name = "gcc_blsp2_qup4_i2c_apps_clk",
  1696. .parent_hws = (const struct clk_hw *[]) {
  1697. &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
  1698. },
  1699. .num_parents = 1,
  1700. .flags = CLK_SET_RATE_PARENT,
  1701. .ops = &clk_branch2_ops,
  1702. },
  1703. },
  1704. };
  1705. static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
  1706. .halt_reg = 0x2c004,
  1707. .halt_check = BRANCH_HALT,
  1708. .clkr = {
  1709. .enable_reg = 0x2c004,
  1710. .enable_mask = BIT(0),
  1711. .hw.init = &(struct clk_init_data){
  1712. .name = "gcc_blsp2_qup4_spi_apps_clk",
  1713. .parent_hws = (const struct clk_hw *[]) {
  1714. &blsp2_qup4_spi_apps_clk_src.clkr.hw,
  1715. },
  1716. .num_parents = 1,
  1717. .flags = CLK_SET_RATE_PARENT,
  1718. .ops = &clk_branch2_ops,
  1719. },
  1720. },
  1721. };
  1722. static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
  1723. .halt_reg = 0x2e008,
  1724. .halt_check = BRANCH_HALT,
  1725. .clkr = {
  1726. .enable_reg = 0x2e008,
  1727. .enable_mask = BIT(0),
  1728. .hw.init = &(struct clk_init_data){
  1729. .name = "gcc_blsp2_qup5_i2c_apps_clk",
  1730. .parent_hws = (const struct clk_hw *[]) {
  1731. &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
  1732. },
  1733. .num_parents = 1,
  1734. .flags = CLK_SET_RATE_PARENT,
  1735. .ops = &clk_branch2_ops,
  1736. },
  1737. },
  1738. };
  1739. static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
  1740. .halt_reg = 0x2e004,
  1741. .halt_check = BRANCH_HALT,
  1742. .clkr = {
  1743. .enable_reg = 0x2e004,
  1744. .enable_mask = BIT(0),
  1745. .hw.init = &(struct clk_init_data){
  1746. .name = "gcc_blsp2_qup5_spi_apps_clk",
  1747. .parent_hws = (const struct clk_hw *[]) {
  1748. &blsp2_qup5_spi_apps_clk_src.clkr.hw,
  1749. },
  1750. .num_parents = 1,
  1751. .flags = CLK_SET_RATE_PARENT,
  1752. .ops = &clk_branch2_ops,
  1753. },
  1754. },
  1755. };
  1756. static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
  1757. .halt_reg = 0x30008,
  1758. .halt_check = BRANCH_HALT,
  1759. .clkr = {
  1760. .enable_reg = 0x30008,
  1761. .enable_mask = BIT(0),
  1762. .hw.init = &(struct clk_init_data){
  1763. .name = "gcc_blsp2_qup6_i2c_apps_clk",
  1764. .parent_hws = (const struct clk_hw *[]) {
  1765. &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
  1766. },
  1767. .num_parents = 1,
  1768. .flags = CLK_SET_RATE_PARENT,
  1769. .ops = &clk_branch2_ops,
  1770. },
  1771. },
  1772. };
  1773. static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
  1774. .halt_reg = 0x30004,
  1775. .halt_check = BRANCH_HALT,
  1776. .clkr = {
  1777. .enable_reg = 0x30004,
  1778. .enable_mask = BIT(0),
  1779. .hw.init = &(struct clk_init_data){
  1780. .name = "gcc_blsp2_qup6_spi_apps_clk",
  1781. .parent_hws = (const struct clk_hw *[]) {
  1782. &blsp2_qup6_spi_apps_clk_src.clkr.hw,
  1783. },
  1784. .num_parents = 1,
  1785. .flags = CLK_SET_RATE_PARENT,
  1786. .ops = &clk_branch2_ops,
  1787. },
  1788. },
  1789. };
  1790. static struct clk_branch gcc_blsp2_sleep_clk = {
  1791. .halt_reg = 0x25008,
  1792. .halt_check = BRANCH_HALT_VOTED,
  1793. .clkr = {
  1794. .enable_reg = 0x52004,
  1795. .enable_mask = BIT(14),
  1796. .hw.init = &(struct clk_init_data){
  1797. .name = "gcc_blsp2_sleep_clk",
  1798. .ops = &clk_branch2_ops,
  1799. },
  1800. },
  1801. };
  1802. static struct clk_branch gcc_blsp2_uart1_apps_clk = {
  1803. .halt_reg = 0x27004,
  1804. .halt_check = BRANCH_HALT,
  1805. .clkr = {
  1806. .enable_reg = 0x27004,
  1807. .enable_mask = BIT(0),
  1808. .hw.init = &(struct clk_init_data){
  1809. .name = "gcc_blsp2_uart1_apps_clk",
  1810. .parent_hws = (const struct clk_hw *[]) {
  1811. &blsp2_uart1_apps_clk_src.clkr.hw,
  1812. },
  1813. .num_parents = 1,
  1814. .flags = CLK_SET_RATE_PARENT,
  1815. .ops = &clk_branch2_ops,
  1816. },
  1817. },
  1818. };
  1819. static struct clk_branch gcc_blsp2_uart2_apps_clk = {
  1820. .halt_reg = 0x29004,
  1821. .halt_check = BRANCH_HALT,
  1822. .clkr = {
  1823. .enable_reg = 0x29004,
  1824. .enable_mask = BIT(0),
  1825. .hw.init = &(struct clk_init_data){
  1826. .name = "gcc_blsp2_uart2_apps_clk",
  1827. .parent_hws = (const struct clk_hw *[]) {
  1828. &blsp2_uart2_apps_clk_src.clkr.hw,
  1829. },
  1830. .num_parents = 1,
  1831. .flags = CLK_SET_RATE_PARENT,
  1832. .ops = &clk_branch2_ops,
  1833. },
  1834. },
  1835. };
  1836. static struct clk_branch gcc_blsp2_uart3_apps_clk = {
  1837. .halt_reg = 0x2b004,
  1838. .halt_check = BRANCH_HALT,
  1839. .clkr = {
  1840. .enable_reg = 0x2b004,
  1841. .enable_mask = BIT(0),
  1842. .hw.init = &(struct clk_init_data){
  1843. .name = "gcc_blsp2_uart3_apps_clk",
  1844. .parent_hws = (const struct clk_hw *[]) {
  1845. &blsp2_uart3_apps_clk_src.clkr.hw,
  1846. },
  1847. .num_parents = 1,
  1848. .flags = CLK_SET_RATE_PARENT,
  1849. .ops = &clk_branch2_ops,
  1850. },
  1851. },
  1852. };
  1853. static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
  1854. .halt_reg = 0x5018,
  1855. .halt_check = BRANCH_HALT,
  1856. .clkr = {
  1857. .enable_reg = 0x5018,
  1858. .enable_mask = BIT(0),
  1859. .hw.init = &(struct clk_init_data){
  1860. .name = "gcc_cfg_noc_usb3_axi_clk",
  1861. .parent_hws = (const struct clk_hw *[]) {
  1862. &usb30_master_clk_src.clkr.hw,
  1863. },
  1864. .num_parents = 1,
  1865. .flags = CLK_SET_RATE_PARENT,
  1866. .ops = &clk_branch2_ops,
  1867. },
  1868. },
  1869. };
  1870. static struct clk_branch gcc_gp1_clk = {
  1871. .halt_reg = 0x64000,
  1872. .halt_check = BRANCH_HALT,
  1873. .clkr = {
  1874. .enable_reg = 0x64000,
  1875. .enable_mask = BIT(0),
  1876. .hw.init = &(struct clk_init_data){
  1877. .name = "gcc_gp1_clk",
  1878. .parent_hws = (const struct clk_hw *[]) {
  1879. &gp1_clk_src.clkr.hw,
  1880. },
  1881. .num_parents = 1,
  1882. .flags = CLK_SET_RATE_PARENT,
  1883. .ops = &clk_branch2_ops,
  1884. },
  1885. },
  1886. };
  1887. static struct clk_branch gcc_gp2_clk = {
  1888. .halt_reg = 0x65000,
  1889. .halt_check = BRANCH_HALT,
  1890. .clkr = {
  1891. .enable_reg = 0x65000,
  1892. .enable_mask = BIT(0),
  1893. .hw.init = &(struct clk_init_data){
  1894. .name = "gcc_gp2_clk",
  1895. .parent_hws = (const struct clk_hw *[]) {
  1896. &gp2_clk_src.clkr.hw,
  1897. },
  1898. .num_parents = 1,
  1899. .flags = CLK_SET_RATE_PARENT,
  1900. .ops = &clk_branch2_ops,
  1901. },
  1902. },
  1903. };
  1904. static struct clk_branch gcc_gp3_clk = {
  1905. .halt_reg = 0x66000,
  1906. .halt_check = BRANCH_HALT,
  1907. .clkr = {
  1908. .enable_reg = 0x66000,
  1909. .enable_mask = BIT(0),
  1910. .hw.init = &(struct clk_init_data){
  1911. .name = "gcc_gp3_clk",
  1912. .parent_hws = (const struct clk_hw *[]) {
  1913. &gp3_clk_src.clkr.hw,
  1914. },
  1915. .num_parents = 1,
  1916. .flags = CLK_SET_RATE_PARENT,
  1917. .ops = &clk_branch2_ops,
  1918. },
  1919. },
  1920. };
  1921. static struct clk_branch gcc_bimc_gfx_clk = {
  1922. .halt_reg = 0x46040,
  1923. .halt_check = BRANCH_HALT,
  1924. .clkr = {
  1925. .enable_reg = 0x46040,
  1926. .enable_mask = BIT(0),
  1927. .hw.init = &(struct clk_init_data){
  1928. .name = "gcc_bimc_gfx_clk",
  1929. .ops = &clk_branch2_ops,
  1930. },
  1931. },
  1932. };
  1933. static struct clk_branch gcc_gpu_bimc_gfx_clk = {
  1934. .halt_reg = 0x71010,
  1935. .halt_check = BRANCH_HALT,
  1936. .clkr = {
  1937. .enable_reg = 0x71010,
  1938. .enable_mask = BIT(0),
  1939. .hw.init = &(struct clk_init_data){
  1940. .name = "gcc_gpu_bimc_gfx_clk",
  1941. .ops = &clk_branch2_ops,
  1942. },
  1943. },
  1944. };
  1945. static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
  1946. .halt_reg = 0x7100c,
  1947. .halt_check = BRANCH_HALT,
  1948. .clkr = {
  1949. .enable_reg = 0x7100c,
  1950. .enable_mask = BIT(0),
  1951. .hw.init = &(struct clk_init_data){
  1952. .name = "gcc_gpu_bimc_gfx_src_clk",
  1953. .ops = &clk_branch2_ops,
  1954. },
  1955. },
  1956. };
  1957. static struct clk_branch gcc_gpu_cfg_ahb_clk = {
  1958. .halt_reg = 0x71004,
  1959. .halt_check = BRANCH_HALT,
  1960. .clkr = {
  1961. .enable_reg = 0x71004,
  1962. .enable_mask = BIT(0),
  1963. .hw.init = &(struct clk_init_data){
  1964. .name = "gcc_gpu_cfg_ahb_clk",
  1965. .ops = &clk_branch2_ops,
  1966. /*
  1967. * The GPU IOMMU depends on this clock and hypervisor
  1968. * will crash the SoC if this clock goes down, due to
  1969. * secure contexts protection.
  1970. */
  1971. .flags = CLK_IS_CRITICAL,
  1972. },
  1973. },
  1974. };
  1975. static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
  1976. .halt_reg = 0x71018,
  1977. .halt_check = BRANCH_HALT,
  1978. .clkr = {
  1979. .enable_reg = 0x71018,
  1980. .enable_mask = BIT(0),
  1981. .hw.init = &(struct clk_init_data){
  1982. .name = "gcc_gpu_snoc_dvm_gfx_clk",
  1983. .ops = &clk_branch2_ops,
  1984. },
  1985. },
  1986. };
  1987. static struct clk_branch gcc_hmss_ahb_clk = {
  1988. .halt_reg = 0x48000,
  1989. .halt_check = BRANCH_HALT_VOTED,
  1990. .clkr = {
  1991. .enable_reg = 0x52004,
  1992. .enable_mask = BIT(21),
  1993. .hw.init = &(struct clk_init_data){
  1994. .name = "gcc_hmss_ahb_clk",
  1995. .parent_hws = (const struct clk_hw *[]) {
  1996. &hmss_ahb_clk_src.clkr.hw,
  1997. },
  1998. .num_parents = 1,
  1999. .flags = CLK_SET_RATE_PARENT,
  2000. .ops = &clk_branch2_ops,
  2001. },
  2002. },
  2003. };
  2004. static struct clk_branch gcc_hmss_at_clk = {
  2005. .halt_reg = 0x48010,
  2006. .halt_check = BRANCH_HALT,
  2007. .clkr = {
  2008. .enable_reg = 0x48010,
  2009. .enable_mask = BIT(0),
  2010. .hw.init = &(struct clk_init_data){
  2011. .name = "gcc_hmss_at_clk",
  2012. .ops = &clk_branch2_ops,
  2013. },
  2014. },
  2015. };
  2016. static struct clk_branch gcc_hmss_rbcpr_clk = {
  2017. .halt_reg = 0x48008,
  2018. .halt_check = BRANCH_HALT,
  2019. .clkr = {
  2020. .enable_reg = 0x48008,
  2021. .enable_mask = BIT(0),
  2022. .hw.init = &(struct clk_init_data){
  2023. .name = "gcc_hmss_rbcpr_clk",
  2024. .parent_hws = (const struct clk_hw *[]) {
  2025. &hmss_rbcpr_clk_src.clkr.hw,
  2026. },
  2027. .num_parents = 1,
  2028. .flags = CLK_SET_RATE_PARENT,
  2029. .ops = &clk_branch2_ops,
  2030. },
  2031. },
  2032. };
  2033. static struct clk_branch gcc_hmss_trig_clk = {
  2034. .halt_reg = 0x4800c,
  2035. .halt_check = BRANCH_HALT,
  2036. .clkr = {
  2037. .enable_reg = 0x4800c,
  2038. .enable_mask = BIT(0),
  2039. .hw.init = &(struct clk_init_data){
  2040. .name = "gcc_hmss_trig_clk",
  2041. .ops = &clk_branch2_ops,
  2042. },
  2043. },
  2044. };
  2045. static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
  2046. F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
  2047. F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
  2048. { }
  2049. };
  2050. static struct clk_rcg2 hmss_gpll0_clk_src = {
  2051. .cmd_rcgr = 0x4805c,
  2052. .hid_width = 5,
  2053. .parent_map = gcc_parent_map_1,
  2054. .freq_tbl = ftbl_hmss_gpll0_clk_src,
  2055. .clkr.hw.init = &(struct clk_init_data) {
  2056. .name = "hmss_gpll0_clk_src",
  2057. .parent_data = gcc_parent_data_1,
  2058. .num_parents = ARRAY_SIZE(gcc_parent_data_1),
  2059. .ops = &clk_rcg2_ops,
  2060. },
  2061. };
  2062. static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
  2063. .halt_reg = 0x9004,
  2064. .halt_check = BRANCH_HALT,
  2065. .clkr = {
  2066. .enable_reg = 0x9004,
  2067. .enable_mask = BIT(0),
  2068. .hw.init = &(struct clk_init_data){
  2069. .name = "gcc_mmss_noc_cfg_ahb_clk",
  2070. .ops = &clk_branch2_ops,
  2071. /*
  2072. * Any access to mmss depends on this clock.
  2073. * Gating this clock has been shown to crash the system
  2074. * when mmssnoc_axi_rpm_clk is inited in rpmcc.
  2075. */
  2076. .flags = CLK_IS_CRITICAL,
  2077. },
  2078. },
  2079. };
  2080. static struct clk_branch gcc_mmss_qm_ahb_clk = {
  2081. .halt_reg = 0x9030,
  2082. .halt_check = BRANCH_HALT,
  2083. .clkr = {
  2084. .enable_reg = 0x9030,
  2085. .enable_mask = BIT(0),
  2086. .hw.init = &(struct clk_init_data){
  2087. .name = "gcc_mmss_qm_ahb_clk",
  2088. .ops = &clk_branch2_ops,
  2089. },
  2090. },
  2091. };
  2092. static struct clk_branch gcc_mmss_qm_core_clk = {
  2093. .halt_reg = 0x900c,
  2094. .halt_check = BRANCH_HALT,
  2095. .clkr = {
  2096. .enable_reg = 0x900c,
  2097. .enable_mask = BIT(0),
  2098. .hw.init = &(struct clk_init_data){
  2099. .name = "gcc_mmss_qm_core_clk",
  2100. .ops = &clk_branch2_ops,
  2101. },
  2102. },
  2103. };
  2104. static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
  2105. .halt_reg = 0x9000,
  2106. .halt_check = BRANCH_HALT,
  2107. .clkr = {
  2108. .enable_reg = 0x9000,
  2109. .enable_mask = BIT(0),
  2110. .hw.init = &(struct clk_init_data){
  2111. .name = "gcc_mmss_sys_noc_axi_clk",
  2112. .ops = &clk_branch2_ops,
  2113. },
  2114. },
  2115. };
  2116. static struct clk_branch gcc_mss_at_clk = {
  2117. .halt_reg = 0x8a00c,
  2118. .halt_check = BRANCH_HALT,
  2119. .clkr = {
  2120. .enable_reg = 0x8a00c,
  2121. .enable_mask = BIT(0),
  2122. .hw.init = &(struct clk_init_data){
  2123. .name = "gcc_mss_at_clk",
  2124. .ops = &clk_branch2_ops,
  2125. },
  2126. },
  2127. };
  2128. static struct clk_branch gcc_pcie_0_aux_clk = {
  2129. .halt_reg = 0x6b014,
  2130. .halt_check = BRANCH_HALT,
  2131. .clkr = {
  2132. .enable_reg = 0x6b014,
  2133. .enable_mask = BIT(0),
  2134. .hw.init = &(struct clk_init_data){
  2135. .name = "gcc_pcie_0_aux_clk",
  2136. .parent_hws = (const struct clk_hw *[]) {
  2137. &pcie_aux_clk_src.clkr.hw,
  2138. },
  2139. .num_parents = 1,
  2140. .flags = CLK_SET_RATE_PARENT,
  2141. .ops = &clk_branch2_ops,
  2142. },
  2143. },
  2144. };
  2145. static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
  2146. .halt_reg = 0x6b010,
  2147. .halt_check = BRANCH_HALT,
  2148. .clkr = {
  2149. .enable_reg = 0x6b010,
  2150. .enable_mask = BIT(0),
  2151. .hw.init = &(struct clk_init_data){
  2152. .name = "gcc_pcie_0_cfg_ahb_clk",
  2153. .ops = &clk_branch2_ops,
  2154. },
  2155. },
  2156. };
  2157. static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
  2158. .halt_reg = 0x6b00c,
  2159. .halt_check = BRANCH_HALT,
  2160. .clkr = {
  2161. .enable_reg = 0x6b00c,
  2162. .enable_mask = BIT(0),
  2163. .hw.init = &(struct clk_init_data){
  2164. .name = "gcc_pcie_0_mstr_axi_clk",
  2165. .ops = &clk_branch2_ops,
  2166. },
  2167. },
  2168. };
  2169. static struct clk_branch gcc_pcie_0_pipe_clk = {
  2170. .halt_reg = 0x6b018,
  2171. .halt_check = BRANCH_HALT_SKIP,
  2172. .clkr = {
  2173. .enable_reg = 0x6b018,
  2174. .enable_mask = BIT(0),
  2175. .hw.init = &(struct clk_init_data){
  2176. .name = "gcc_pcie_0_pipe_clk",
  2177. .ops = &clk_branch2_ops,
  2178. },
  2179. },
  2180. };
  2181. static struct clk_branch gcc_pcie_0_slv_axi_clk = {
  2182. .halt_reg = 0x6b008,
  2183. .halt_check = BRANCH_HALT,
  2184. .clkr = {
  2185. .enable_reg = 0x6b008,
  2186. .enable_mask = BIT(0),
  2187. .hw.init = &(struct clk_init_data){
  2188. .name = "gcc_pcie_0_slv_axi_clk",
  2189. .ops = &clk_branch2_ops,
  2190. },
  2191. },
  2192. };
  2193. static struct clk_branch gcc_pcie_phy_aux_clk = {
  2194. .halt_reg = 0x6f004,
  2195. .halt_check = BRANCH_HALT,
  2196. .clkr = {
  2197. .enable_reg = 0x6f004,
  2198. .enable_mask = BIT(0),
  2199. .hw.init = &(struct clk_init_data){
  2200. .name = "gcc_pcie_phy_aux_clk",
  2201. .parent_hws = (const struct clk_hw *[]) {
  2202. &pcie_aux_clk_src.clkr.hw,
  2203. },
  2204. .num_parents = 1,
  2205. .flags = CLK_SET_RATE_PARENT,
  2206. .ops = &clk_branch2_ops,
  2207. },
  2208. },
  2209. };
  2210. static struct clk_branch gcc_pdm2_clk = {
  2211. .halt_reg = 0x3300c,
  2212. .halt_check = BRANCH_HALT,
  2213. .clkr = {
  2214. .enable_reg = 0x3300c,
  2215. .enable_mask = BIT(0),
  2216. .hw.init = &(struct clk_init_data){
  2217. .name = "gcc_pdm2_clk",
  2218. .parent_hws = (const struct clk_hw *[]) {
  2219. &pdm2_clk_src.clkr.hw,
  2220. },
  2221. .num_parents = 1,
  2222. .flags = CLK_SET_RATE_PARENT,
  2223. .ops = &clk_branch2_ops,
  2224. },
  2225. },
  2226. };
  2227. static struct clk_branch gcc_pdm_ahb_clk = {
  2228. .halt_reg = 0x33004,
  2229. .halt_check = BRANCH_HALT,
  2230. .clkr = {
  2231. .enable_reg = 0x33004,
  2232. .enable_mask = BIT(0),
  2233. .hw.init = &(struct clk_init_data){
  2234. .name = "gcc_pdm_ahb_clk",
  2235. .ops = &clk_branch2_ops,
  2236. },
  2237. },
  2238. };
  2239. static struct clk_branch gcc_pdm_xo4_clk = {
  2240. .halt_reg = 0x33008,
  2241. .halt_check = BRANCH_HALT,
  2242. .clkr = {
  2243. .enable_reg = 0x33008,
  2244. .enable_mask = BIT(0),
  2245. .hw.init = &(struct clk_init_data){
  2246. .name = "gcc_pdm_xo4_clk",
  2247. .ops = &clk_branch2_ops,
  2248. },
  2249. },
  2250. };
  2251. static struct clk_branch gcc_prng_ahb_clk = {
  2252. .halt_reg = 0x34004,
  2253. .halt_check = BRANCH_HALT_VOTED,
  2254. .clkr = {
  2255. .enable_reg = 0x52004,
  2256. .enable_mask = BIT(13),
  2257. .hw.init = &(struct clk_init_data){
  2258. .name = "gcc_prng_ahb_clk",
  2259. .ops = &clk_branch2_ops,
  2260. },
  2261. },
  2262. };
  2263. static struct clk_branch gcc_sdcc2_ahb_clk = {
  2264. .halt_reg = 0x14008,
  2265. .halt_check = BRANCH_HALT,
  2266. .clkr = {
  2267. .enable_reg = 0x14008,
  2268. .enable_mask = BIT(0),
  2269. .hw.init = &(struct clk_init_data){
  2270. .name = "gcc_sdcc2_ahb_clk",
  2271. .ops = &clk_branch2_ops,
  2272. },
  2273. },
  2274. };
  2275. static struct clk_branch gcc_sdcc2_apps_clk = {
  2276. .halt_reg = 0x14004,
  2277. .halt_check = BRANCH_HALT,
  2278. .clkr = {
  2279. .enable_reg = 0x14004,
  2280. .enable_mask = BIT(0),
  2281. .hw.init = &(struct clk_init_data){
  2282. .name = "gcc_sdcc2_apps_clk",
  2283. .parent_hws = (const struct clk_hw *[]) {
  2284. &sdcc2_apps_clk_src.clkr.hw,
  2285. },
  2286. .num_parents = 1,
  2287. .flags = CLK_SET_RATE_PARENT,
  2288. .ops = &clk_branch2_ops,
  2289. },
  2290. },
  2291. };
  2292. static struct clk_branch gcc_sdcc4_ahb_clk = {
  2293. .halt_reg = 0x16008,
  2294. .halt_check = BRANCH_HALT,
  2295. .clkr = {
  2296. .enable_reg = 0x16008,
  2297. .enable_mask = BIT(0),
  2298. .hw.init = &(struct clk_init_data){
  2299. .name = "gcc_sdcc4_ahb_clk",
  2300. .ops = &clk_branch2_ops,
  2301. },
  2302. },
  2303. };
  2304. static struct clk_branch gcc_sdcc4_apps_clk = {
  2305. .halt_reg = 0x16004,
  2306. .halt_check = BRANCH_HALT,
  2307. .clkr = {
  2308. .enable_reg = 0x16004,
  2309. .enable_mask = BIT(0),
  2310. .hw.init = &(struct clk_init_data){
  2311. .name = "gcc_sdcc4_apps_clk",
  2312. .parent_hws = (const struct clk_hw *[]) {
  2313. &sdcc4_apps_clk_src.clkr.hw,
  2314. },
  2315. .num_parents = 1,
  2316. .flags = CLK_SET_RATE_PARENT,
  2317. .ops = &clk_branch2_ops,
  2318. },
  2319. },
  2320. };
  2321. static struct clk_branch gcc_tsif_ahb_clk = {
  2322. .halt_reg = 0x36004,
  2323. .halt_check = BRANCH_HALT,
  2324. .clkr = {
  2325. .enable_reg = 0x36004,
  2326. .enable_mask = BIT(0),
  2327. .hw.init = &(struct clk_init_data){
  2328. .name = "gcc_tsif_ahb_clk",
  2329. .ops = &clk_branch2_ops,
  2330. },
  2331. },
  2332. };
  2333. static struct clk_branch gcc_tsif_inactivity_timers_clk = {
  2334. .halt_reg = 0x3600c,
  2335. .halt_check = BRANCH_HALT,
  2336. .clkr = {
  2337. .enable_reg = 0x3600c,
  2338. .enable_mask = BIT(0),
  2339. .hw.init = &(struct clk_init_data){
  2340. .name = "gcc_tsif_inactivity_timers_clk",
  2341. .ops = &clk_branch2_ops,
  2342. },
  2343. },
  2344. };
  2345. static struct clk_branch gcc_tsif_ref_clk = {
  2346. .halt_reg = 0x36008,
  2347. .halt_check = BRANCH_HALT,
  2348. .clkr = {
  2349. .enable_reg = 0x36008,
  2350. .enable_mask = BIT(0),
  2351. .hw.init = &(struct clk_init_data){
  2352. .name = "gcc_tsif_ref_clk",
  2353. .parent_hws = (const struct clk_hw *[]) {
  2354. &tsif_ref_clk_src.clkr.hw,
  2355. },
  2356. .num_parents = 1,
  2357. .flags = CLK_SET_RATE_PARENT,
  2358. .ops = &clk_branch2_ops,
  2359. },
  2360. },
  2361. };
  2362. static struct clk_branch gcc_ufs_ahb_clk = {
  2363. .halt_reg = 0x7500c,
  2364. .halt_check = BRANCH_HALT,
  2365. .clkr = {
  2366. .enable_reg = 0x7500c,
  2367. .enable_mask = BIT(0),
  2368. .hw.init = &(struct clk_init_data){
  2369. .name = "gcc_ufs_ahb_clk",
  2370. .ops = &clk_branch2_ops,
  2371. },
  2372. },
  2373. };
  2374. static struct clk_branch gcc_ufs_axi_clk = {
  2375. .halt_reg = 0x75008,
  2376. .halt_check = BRANCH_HALT,
  2377. .clkr = {
  2378. .enable_reg = 0x75008,
  2379. .enable_mask = BIT(0),
  2380. .hw.init = &(struct clk_init_data){
  2381. .name = "gcc_ufs_axi_clk",
  2382. .parent_hws = (const struct clk_hw *[]) {
  2383. &ufs_axi_clk_src.clkr.hw,
  2384. },
  2385. .num_parents = 1,
  2386. .flags = CLK_SET_RATE_PARENT,
  2387. .ops = &clk_branch2_ops,
  2388. },
  2389. },
  2390. };
  2391. static struct clk_branch gcc_ufs_ice_core_clk = {
  2392. .halt_reg = 0x7600c,
  2393. .halt_check = BRANCH_HALT,
  2394. .clkr = {
  2395. .enable_reg = 0x7600c,
  2396. .enable_mask = BIT(0),
  2397. .hw.init = &(struct clk_init_data){
  2398. .name = "gcc_ufs_ice_core_clk",
  2399. .ops = &clk_branch2_ops,
  2400. },
  2401. },
  2402. };
  2403. static struct clk_branch gcc_ufs_phy_aux_clk = {
  2404. .halt_reg = 0x76040,
  2405. .halt_check = BRANCH_HALT,
  2406. .clkr = {
  2407. .enable_reg = 0x76040,
  2408. .enable_mask = BIT(0),
  2409. .hw.init = &(struct clk_init_data){
  2410. .name = "gcc_ufs_phy_aux_clk",
  2411. .ops = &clk_branch2_ops,
  2412. },
  2413. },
  2414. };
  2415. static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
  2416. .halt_reg = 0x75014,
  2417. .halt_check = BRANCH_HALT_SKIP,
  2418. .clkr = {
  2419. .enable_reg = 0x75014,
  2420. .enable_mask = BIT(0),
  2421. .hw.init = &(struct clk_init_data){
  2422. .name = "gcc_ufs_rx_symbol_0_clk",
  2423. .ops = &clk_branch2_ops,
  2424. },
  2425. },
  2426. };
  2427. static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
  2428. .halt_reg = 0x7605c,
  2429. .halt_check = BRANCH_HALT_SKIP,
  2430. .clkr = {
  2431. .enable_reg = 0x7605c,
  2432. .enable_mask = BIT(0),
  2433. .hw.init = &(struct clk_init_data){
  2434. .name = "gcc_ufs_rx_symbol_1_clk",
  2435. .ops = &clk_branch2_ops,
  2436. },
  2437. },
  2438. };
  2439. static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
  2440. .halt_reg = 0x75010,
  2441. .halt_check = BRANCH_HALT_SKIP,
  2442. .clkr = {
  2443. .enable_reg = 0x75010,
  2444. .enable_mask = BIT(0),
  2445. .hw.init = &(struct clk_init_data){
  2446. .name = "gcc_ufs_tx_symbol_0_clk",
  2447. .ops = &clk_branch2_ops,
  2448. },
  2449. },
  2450. };
  2451. static struct clk_branch gcc_ufs_unipro_core_clk = {
  2452. .halt_reg = 0x76008,
  2453. .halt_check = BRANCH_HALT,
  2454. .clkr = {
  2455. .enable_reg = 0x76008,
  2456. .enable_mask = BIT(0),
  2457. .hw.init = &(struct clk_init_data){
  2458. .name = "gcc_ufs_unipro_core_clk",
  2459. .parent_hws = (const struct clk_hw *[]) {
  2460. &ufs_unipro_core_clk_src.clkr.hw,
  2461. },
  2462. .num_parents = 1,
  2463. .flags = CLK_SET_RATE_PARENT,
  2464. .ops = &clk_branch2_ops,
  2465. },
  2466. },
  2467. };
  2468. static struct clk_branch gcc_usb30_master_clk = {
  2469. .halt_reg = 0xf008,
  2470. .halt_check = BRANCH_HALT,
  2471. .clkr = {
  2472. .enable_reg = 0xf008,
  2473. .enable_mask = BIT(0),
  2474. .hw.init = &(struct clk_init_data){
  2475. .name = "gcc_usb30_master_clk",
  2476. .parent_hws = (const struct clk_hw *[]) {
  2477. &usb30_master_clk_src.clkr.hw,
  2478. },
  2479. .num_parents = 1,
  2480. .flags = CLK_SET_RATE_PARENT,
  2481. .ops = &clk_branch2_ops,
  2482. },
  2483. },
  2484. };
  2485. static struct clk_branch gcc_usb30_mock_utmi_clk = {
  2486. .halt_reg = 0xf010,
  2487. .halt_check = BRANCH_HALT,
  2488. .clkr = {
  2489. .enable_reg = 0xf010,
  2490. .enable_mask = BIT(0),
  2491. .hw.init = &(struct clk_init_data){
  2492. .name = "gcc_usb30_mock_utmi_clk",
  2493. .parent_hws = (const struct clk_hw *[]) {
  2494. &usb30_mock_utmi_clk_src.clkr.hw,
  2495. },
  2496. .num_parents = 1,
  2497. .flags = CLK_SET_RATE_PARENT,
  2498. .ops = &clk_branch2_ops,
  2499. },
  2500. },
  2501. };
  2502. static struct clk_branch gcc_usb30_sleep_clk = {
  2503. .halt_reg = 0xf00c,
  2504. .halt_check = BRANCH_HALT,
  2505. .clkr = {
  2506. .enable_reg = 0xf00c,
  2507. .enable_mask = BIT(0),
  2508. .hw.init = &(struct clk_init_data){
  2509. .name = "gcc_usb30_sleep_clk",
  2510. .ops = &clk_branch2_ops,
  2511. },
  2512. },
  2513. };
  2514. static struct clk_branch gcc_usb3_phy_aux_clk = {
  2515. .halt_reg = 0x50000,
  2516. .halt_check = BRANCH_HALT,
  2517. .clkr = {
  2518. .enable_reg = 0x50000,
  2519. .enable_mask = BIT(0),
  2520. .hw.init = &(struct clk_init_data){
  2521. .name = "gcc_usb3_phy_aux_clk",
  2522. .parent_hws = (const struct clk_hw *[]) {
  2523. &usb3_phy_aux_clk_src.clkr.hw,
  2524. },
  2525. .num_parents = 1,
  2526. .flags = CLK_SET_RATE_PARENT,
  2527. .ops = &clk_branch2_ops,
  2528. },
  2529. },
  2530. };
  2531. static struct clk_branch gcc_usb3_phy_pipe_clk = {
  2532. .halt_reg = 0x50004,
  2533. .halt_check = BRANCH_HALT_SKIP,
  2534. .clkr = {
  2535. .enable_reg = 0x50004,
  2536. .enable_mask = BIT(0),
  2537. .hw.init = &(struct clk_init_data){
  2538. .name = "gcc_usb3_phy_pipe_clk",
  2539. .ops = &clk_branch2_ops,
  2540. },
  2541. },
  2542. };
  2543. static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
  2544. .halt_reg = 0x6a004,
  2545. .halt_check = BRANCH_HALT,
  2546. .clkr = {
  2547. .enable_reg = 0x6a004,
  2548. .enable_mask = BIT(0),
  2549. .hw.init = &(struct clk_init_data){
  2550. .name = "gcc_usb_phy_cfg_ahb2phy_clk",
  2551. .ops = &clk_branch2_ops,
  2552. },
  2553. },
  2554. };
  2555. static struct clk_branch gcc_hdmi_clkref_clk = {
  2556. .halt_reg = 0x88000,
  2557. .clkr = {
  2558. .enable_reg = 0x88000,
  2559. .enable_mask = BIT(0),
  2560. .hw.init = &(struct clk_init_data){
  2561. .name = "gcc_hdmi_clkref_clk",
  2562. .parent_data = (const struct clk_parent_data []) {
  2563. { .fw_name = "xo" },
  2564. },
  2565. .num_parents = 1,
  2566. .ops = &clk_branch2_ops,
  2567. },
  2568. },
  2569. };
  2570. static struct clk_branch gcc_ufs_clkref_clk = {
  2571. .halt_reg = 0x88004,
  2572. .clkr = {
  2573. .enable_reg = 0x88004,
  2574. .enable_mask = BIT(0),
  2575. .hw.init = &(struct clk_init_data){
  2576. .name = "gcc_ufs_clkref_clk",
  2577. .parent_data = (const struct clk_parent_data []) {
  2578. { .fw_name = "xo" },
  2579. },
  2580. .num_parents = 1,
  2581. .ops = &clk_branch2_ops,
  2582. },
  2583. },
  2584. };
  2585. static struct clk_branch gcc_usb3_clkref_clk = {
  2586. .halt_reg = 0x88008,
  2587. .clkr = {
  2588. .enable_reg = 0x88008,
  2589. .enable_mask = BIT(0),
  2590. .hw.init = &(struct clk_init_data){
  2591. .name = "gcc_usb3_clkref_clk",
  2592. .parent_data = (const struct clk_parent_data []) {
  2593. { .fw_name = "xo" },
  2594. },
  2595. .num_parents = 1,
  2596. .ops = &clk_branch2_ops,
  2597. },
  2598. },
  2599. };
  2600. static struct clk_branch gcc_pcie_clkref_clk = {
  2601. .halt_reg = 0x8800c,
  2602. .clkr = {
  2603. .enable_reg = 0x8800c,
  2604. .enable_mask = BIT(0),
  2605. .hw.init = &(struct clk_init_data){
  2606. .name = "gcc_pcie_clkref_clk",
  2607. .parent_data = (const struct clk_parent_data []) {
  2608. { .fw_name = "xo" },
  2609. },
  2610. .num_parents = 1,
  2611. .ops = &clk_branch2_ops,
  2612. },
  2613. },
  2614. };
  2615. static struct clk_branch gcc_rx1_usb2_clkref_clk = {
  2616. .halt_reg = 0x88014,
  2617. .clkr = {
  2618. .enable_reg = 0x88014,
  2619. .enable_mask = BIT(0),
  2620. .hw.init = &(struct clk_init_data){
  2621. .name = "gcc_rx1_usb2_clkref_clk",
  2622. .parent_data = (const struct clk_parent_data []) {
  2623. { .fw_name = "xo" },
  2624. },
  2625. .num_parents = 1,
  2626. .ops = &clk_branch2_ops,
  2627. },
  2628. },
  2629. };
  2630. static struct clk_branch gcc_im_sleep_clk = {
  2631. .halt_reg = 0x4300c,
  2632. .halt_check = BRANCH_HALT,
  2633. .clkr = {
  2634. .enable_reg = 0x4300c,
  2635. .enable_mask = BIT(0),
  2636. .hw.init = &(const struct clk_init_data){
  2637. .name = "gcc_im_sleep_clk",
  2638. .ops = &clk_branch2_ops,
  2639. },
  2640. },
  2641. };
  2642. static struct clk_branch aggre2_snoc_north_axi_clk = {
  2643. .halt_reg = 0x83010,
  2644. .halt_check = BRANCH_HALT,
  2645. .clkr = {
  2646. .enable_reg = 0x83010,
  2647. .enable_mask = BIT(0),
  2648. .hw.init = &(const struct clk_init_data){
  2649. .name = "aggre2_snoc_north_axi_clk",
  2650. .ops = &clk_branch2_ops,
  2651. },
  2652. },
  2653. };
  2654. static struct clk_branch ssc_xo_clk = {
  2655. .halt_reg = 0x63018,
  2656. .halt_check = BRANCH_HALT,
  2657. .clkr = {
  2658. .enable_reg = 0x63018,
  2659. .enable_mask = BIT(0),
  2660. .hw.init = &(const struct clk_init_data){
  2661. .name = "ssc_xo_clk",
  2662. .ops = &clk_branch2_ops,
  2663. },
  2664. },
  2665. };
  2666. static struct clk_branch ssc_cnoc_ahbs_clk = {
  2667. .halt_reg = 0x6300c,
  2668. .halt_check = BRANCH_HALT,
  2669. .clkr = {
  2670. .enable_reg = 0x6300c,
  2671. .enable_mask = BIT(0),
  2672. .hw.init = &(const struct clk_init_data){
  2673. .name = "ssc_cnoc_ahbs_clk",
  2674. .ops = &clk_branch2_ops,
  2675. },
  2676. },
  2677. };
  2678. static struct gdsc pcie_0_gdsc = {
  2679. .gdscr = 0x6b004,
  2680. .gds_hw_ctrl = 0x0,
  2681. .pd = {
  2682. .name = "pcie_0_gdsc",
  2683. },
  2684. .pwrsts = PWRSTS_OFF_ON,
  2685. .flags = VOTABLE,
  2686. };
  2687. static struct gdsc ufs_gdsc = {
  2688. .gdscr = 0x75004,
  2689. .gds_hw_ctrl = 0x0,
  2690. .pd = {
  2691. .name = "ufs_gdsc",
  2692. },
  2693. .pwrsts = PWRSTS_OFF_ON,
  2694. .flags = VOTABLE,
  2695. };
  2696. static struct gdsc usb_30_gdsc = {
  2697. .gdscr = 0xf004,
  2698. .gds_hw_ctrl = 0x0,
  2699. .pd = {
  2700. .name = "usb_30_gdsc",
  2701. },
  2702. .pwrsts = PWRSTS_OFF_ON,
  2703. .flags = VOTABLE,
  2704. };
  2705. static struct clk_regmap *gcc_msm8998_clocks[] = {
  2706. [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
  2707. [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
  2708. [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
  2709. [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
  2710. [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
  2711. [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
  2712. [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
  2713. [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
  2714. [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
  2715. [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
  2716. [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
  2717. [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
  2718. [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
  2719. [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
  2720. [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
  2721. [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
  2722. [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
  2723. [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
  2724. [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
  2725. [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
  2726. [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
  2727. [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
  2728. [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
  2729. [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
  2730. [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
  2731. [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
  2732. [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
  2733. [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
  2734. [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
  2735. [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
  2736. [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
  2737. [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
  2738. [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
  2739. [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
  2740. [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
  2741. [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
  2742. [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
  2743. [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
  2744. [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
  2745. [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
  2746. [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
  2747. [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
  2748. [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
  2749. [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
  2750. [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
  2751. [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
  2752. [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
  2753. [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
  2754. [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
  2755. [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
  2756. [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
  2757. [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  2758. [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
  2759. [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
  2760. [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
  2761. [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
  2762. [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
  2763. [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
  2764. [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
  2765. [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
  2766. [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
  2767. [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
  2768. [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
  2769. [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
  2770. [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
  2771. [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
  2772. [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
  2773. [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
  2774. [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
  2775. [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
  2776. [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
  2777. [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
  2778. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  2779. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  2780. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  2781. [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
  2782. [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
  2783. [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
  2784. [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
  2785. [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
  2786. [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
  2787. [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
  2788. [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
  2789. [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
  2790. [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
  2791. [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
  2792. [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
  2793. [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
  2794. [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
  2795. [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
  2796. [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
  2797. [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
  2798. [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
  2799. [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
  2800. [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
  2801. [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  2802. [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
  2803. [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
  2804. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  2805. [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
  2806. [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  2807. [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
  2808. [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
  2809. [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
  2810. [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
  2811. [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
  2812. [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
  2813. [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
  2814. [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
  2815. [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
  2816. [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
  2817. [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
  2818. [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
  2819. [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
  2820. [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
  2821. [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
  2822. [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
  2823. [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
  2824. [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
  2825. [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
  2826. [GP1_CLK_SRC] = &gp1_clk_src.clkr,
  2827. [GP2_CLK_SRC] = &gp2_clk_src.clkr,
  2828. [GP3_CLK_SRC] = &gp3_clk_src.clkr,
  2829. [GPLL0] = &gpll0.clkr,
  2830. [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
  2831. [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
  2832. [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
  2833. [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
  2834. [GPLL1] = &gpll1.clkr,
  2835. [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
  2836. [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
  2837. [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
  2838. [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
  2839. [GPLL2] = &gpll2.clkr,
  2840. [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
  2841. [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
  2842. [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
  2843. [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
  2844. [GPLL3] = &gpll3.clkr,
  2845. [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
  2846. [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
  2847. [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
  2848. [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
  2849. [GPLL4] = &gpll4.clkr,
  2850. [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
  2851. [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
  2852. [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
  2853. [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
  2854. [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
  2855. [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
  2856. [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
  2857. [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
  2858. [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
  2859. [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
  2860. [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
  2861. [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
  2862. [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
  2863. [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
  2864. [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
  2865. [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
  2866. [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
  2867. [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
  2868. [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
  2869. [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
  2870. [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
  2871. [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
  2872. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  2873. [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
  2874. [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
  2875. [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
  2876. [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
  2877. [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
  2878. [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
  2879. [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
  2880. [SSC_XO] = &ssc_xo_clk.clkr,
  2881. [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
  2882. };
  2883. static struct gdsc *gcc_msm8998_gdscs[] = {
  2884. [PCIE_0_GDSC] = &pcie_0_gdsc,
  2885. [UFS_GDSC] = &ufs_gdsc,
  2886. [USB_30_GDSC] = &usb_30_gdsc,
  2887. };
  2888. static const struct qcom_reset_map gcc_msm8998_resets[] = {
  2889. [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
  2890. [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
  2891. [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
  2892. [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
  2893. [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
  2894. [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
  2895. [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
  2896. [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
  2897. [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
  2898. [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
  2899. [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
  2900. [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
  2901. [GCC_PCIE_0_BCR] = { 0x6b000 },
  2902. [GCC_PDM_BCR] = { 0x33000 },
  2903. [GCC_SDCC2_BCR] = { 0x14000 },
  2904. [GCC_SDCC4_BCR] = { 0x16000 },
  2905. [GCC_TSIF_BCR] = { 0x36000 },
  2906. [GCC_UFS_BCR] = { 0x75000 },
  2907. [GCC_USB_30_BCR] = { 0xf000 },
  2908. [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
  2909. [GCC_CONFIG_NOC_BCR] = { 0x5000 },
  2910. [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
  2911. [GCC_IMEM_BCR] = { 0x8000 },
  2912. [GCC_PIMEM_BCR] = { 0xa000 },
  2913. [GCC_MMSS_BCR] = { 0xb000 },
  2914. [GCC_QDSS_BCR] = { 0xc000 },
  2915. [GCC_WCSS_BCR] = { 0x11000 },
  2916. [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
  2917. [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
  2918. [GCC_BLSP1_BCR] = { 0x17000 },
  2919. [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
  2920. [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
  2921. [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
  2922. [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
  2923. [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
  2924. [GCC_BLSP2_BCR] = { 0x25000 },
  2925. [GCC_BLSP2_UART1_BCR] = { 0x27000 },
  2926. [GCC_BLSP2_UART2_BCR] = { 0x29000 },
  2927. [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
  2928. [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
  2929. [GCC_PRNG_BCR] = { 0x34000 },
  2930. [GCC_TSIF_0_RESET] = { 0x36024 },
  2931. [GCC_TSIF_1_RESET] = { 0x36028 },
  2932. [GCC_TCSR_BCR] = { 0x37000 },
  2933. [GCC_BOOT_ROM_BCR] = { 0x38000 },
  2934. [GCC_MSG_RAM_BCR] = { 0x39000 },
  2935. [GCC_TLMM_BCR] = { 0x3a000 },
  2936. [GCC_MPM_BCR] = { 0x3b000 },
  2937. [GCC_SEC_CTRL_BCR] = { 0x3d000 },
  2938. [GCC_SPMI_BCR] = { 0x3f000 },
  2939. [GCC_SPDM_BCR] = { 0x40000 },
  2940. [GCC_CE1_BCR] = { 0x41000 },
  2941. [GCC_BIMC_BCR] = { 0x44000 },
  2942. [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
  2943. [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
  2944. [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
  2945. [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
  2946. [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
  2947. [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
  2948. [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
  2949. [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
  2950. [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
  2951. [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
  2952. [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
  2953. [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
  2954. [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
  2955. [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
  2956. [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
  2957. [GCC_APB2JTAG_BCR] = { 0x4c000 },
  2958. [GCC_RBCPR_CX_BCR] = { 0x4e000 },
  2959. [GCC_RBCPR_MX_BCR] = { 0x4f000 },
  2960. [GCC_USB3_PHY_BCR] = { 0x50020 },
  2961. [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
  2962. [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
  2963. [GCC_SSC_BCR] = { 0x63000 },
  2964. [GCC_SSC_RESET] = { 0x63020 },
  2965. [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
  2966. [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
  2967. [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
  2968. [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
  2969. [GCC_PCIE_PHY_BCR] = { 0x6f000 },
  2970. [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
  2971. [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
  2972. [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
  2973. [GCC_GPU_BCR] = { 0x71000 },
  2974. [GCC_SPSS_BCR] = { 0x72000 },
  2975. [GCC_OBT_ODT_BCR] = { 0x73000 },
  2976. [GCC_MSS_RESTART] = { 0x79000 },
  2977. [GCC_VS_BCR] = { 0x7a000 },
  2978. [GCC_MSS_VS_RESET] = { 0x7a100 },
  2979. [GCC_GPU_VS_RESET] = { 0x7a104 },
  2980. [GCC_APC0_VS_RESET] = { 0x7a108 },
  2981. [GCC_APC1_VS_RESET] = { 0x7a10c },
  2982. [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
  2983. [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
  2984. [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
  2985. [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
  2986. [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
  2987. [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
  2988. [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
  2989. [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
  2990. [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
  2991. [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
  2992. [GCC_DCC_BCR] = { 0x84000 },
  2993. [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
  2994. [GCC_IPA_BCR] = { 0x89000 },
  2995. [GCC_GLM_BCR] = { 0x8b000 },
  2996. [GCC_SKL_BCR] = { 0x8c000 },
  2997. [GCC_MSMPU_BCR] = { 0x8d000 },
  2998. };
  2999. static const struct regmap_config gcc_msm8998_regmap_config = {
  3000. .reg_bits = 32,
  3001. .reg_stride = 4,
  3002. .val_bits = 32,
  3003. .max_register = 0x8f000,
  3004. .fast_io = true,
  3005. };
  3006. static const struct qcom_cc_desc gcc_msm8998_desc = {
  3007. .config = &gcc_msm8998_regmap_config,
  3008. .clks = gcc_msm8998_clocks,
  3009. .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
  3010. .resets = gcc_msm8998_resets,
  3011. .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
  3012. .gdscs = gcc_msm8998_gdscs,
  3013. .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
  3014. };
  3015. static int gcc_msm8998_probe(struct platform_device *pdev)
  3016. {
  3017. struct regmap *regmap;
  3018. int ret;
  3019. regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
  3020. if (IS_ERR(regmap))
  3021. return PTR_ERR(regmap);
  3022. /*
  3023. * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
  3024. * turned off by hardware during certain apps low power modes.
  3025. */
  3026. ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
  3027. if (ret)
  3028. return ret;
  3029. return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
  3030. }
  3031. static const struct of_device_id gcc_msm8998_match_table[] = {
  3032. { .compatible = "qcom,gcc-msm8998" },
  3033. { }
  3034. };
  3035. MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
  3036. static struct platform_driver gcc_msm8998_driver = {
  3037. .probe = gcc_msm8998_probe,
  3038. .driver = {
  3039. .name = "gcc-msm8998",
  3040. .of_match_table = gcc_msm8998_match_table,
  3041. .sync_state = clk_sync_state,
  3042. },
  3043. };
  3044. static int __init gcc_msm8998_init(void)
  3045. {
  3046. return platform_driver_register(&gcc_msm8998_driver);
  3047. }
  3048. core_initcall(gcc_msm8998_init);
  3049. static void __exit gcc_msm8998_exit(void)
  3050. {
  3051. platform_driver_unregister(&gcc_msm8998_driver);
  3052. }
  3053. module_exit(gcc_msm8998_exit);
  3054. MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
  3055. MODULE_LICENSE("GPL v2");
  3056. MODULE_ALIAS("platform:gcc-msm8998");