debugcc-mdm9607.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "clk: %s: " fmt, __func__
  6. #include <linux/clk.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/err.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include "clk-debug.h"
  17. #include "common.h"
  18. static struct measure_clk_data debug_mux_priv = {
  19. .ctl_reg = 0x74004,
  20. .status_reg = 0x74008,
  21. .xo_div4_cbcr = 0x30034,
  22. };
  23. static const char *const apss_cc_debug_mux_parent_names[] = {
  24. "measure_only_apcs_clk",
  25. };
  26. static int apss_cc_debug_mux_sels[] = {
  27. 0x3, /* measure_only_apcs_clk */
  28. };
  29. static int apss_cc_debug_mux_pre_divs[] = {
  30. 0x1, /* measure_only_apcs_clk */
  31. };
  32. static struct clk_debug_mux apss_cc_debug_mux = {
  33. .priv = &debug_mux_priv,
  34. .debug_offset = 0x0,
  35. .post_div_offset = 0x0,
  36. .cbcr_offset = U32_MAX,
  37. .src_sel_mask = 0x38,
  38. .src_sel_shift = 0x3,
  39. .post_div_mask = 0x0,
  40. .post_div_shift = 0x0,
  41. .post_div_val = 0x1,
  42. .mux_sels = apss_cc_debug_mux_sels,
  43. .pre_div_vals = apss_cc_debug_mux_pre_divs,
  44. .hw.init = &(struct clk_init_data){
  45. .name = "apss_cc_debug_mux",
  46. .ops = &clk_debug_mux_ops,
  47. .parent_names = apss_cc_debug_mux_parent_names,
  48. .num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names),
  49. },
  50. };
  51. static const char *const gcc_debug_mux_parent_names[] = {
  52. "apss_cc_debug_mux",
  53. "gcc_apss_ahb_clk",
  54. "gcc_apss_axi_clk",
  55. "gcc_apss_tcu_clk",
  56. "gcc_blsp1_ahb_clk",
  57. "gcc_blsp1_qup1_i2c_apps_clk",
  58. "gcc_blsp1_qup1_spi_apps_clk",
  59. "gcc_blsp1_qup2_i2c_apps_clk",
  60. "gcc_blsp1_qup2_spi_apps_clk",
  61. "gcc_blsp1_qup3_i2c_apps_clk",
  62. "gcc_blsp1_qup3_spi_apps_clk",
  63. "gcc_blsp1_qup4_i2c_apps_clk",
  64. "gcc_blsp1_qup4_spi_apps_clk",
  65. "gcc_blsp1_qup5_i2c_apps_clk",
  66. "gcc_blsp1_qup5_spi_apps_clk",
  67. "gcc_blsp1_qup6_i2c_apps_clk",
  68. "gcc_blsp1_qup6_spi_apps_clk",
  69. "gcc_blsp1_uart1_apps_clk",
  70. "gcc_blsp1_uart2_apps_clk",
  71. "gcc_blsp1_uart3_apps_clk",
  72. "gcc_blsp1_uart4_apps_clk",
  73. "gcc_blsp1_uart5_apps_clk",
  74. "gcc_blsp1_uart6_apps_clk",
  75. "gcc_boot_rom_ahb_clk",
  76. "gcc_crypto_clk",
  77. "gcc_crypto_ahb_clk",
  78. "gcc_crypto_axi_clk",
  79. "gcc_dcc_clk",
  80. "gcc_emac_0_125m_clk",
  81. "gcc_emac_0_ahb_clk",
  82. "gcc_emac_0_axi_clk",
  83. "gcc_emac_0_rx_clk",
  84. "gcc_emac_0_sys_25m_clk",
  85. "gcc_emac_0_sys_clk",
  86. "gcc_emac_0_tx_clk",
  87. "gcc_gp1_clk",
  88. "gcc_gp2_clk",
  89. "gcc_gp3_clk",
  90. "gcc_mss_cfg_ahb_clk",
  91. "gcc_mss_q6_bimc_axi_clk",
  92. "gcc_pdm2_clk",
  93. "gcc_pdm_ahb_clk",
  94. "gcc_prng_ahb_clk",
  95. "gcc_qdss_dap_clk",
  96. "gcc_sdcc1_apps_clk",
  97. "gcc_sdcc1_ahb_clk",
  98. "gcc_sdcc2_apps_clk",
  99. "gcc_sdcc2_ahb_clk",
  100. "gcc_smmu_cfg_clk",
  101. "gcc_usb_hs_system_clk",
  102. "gcc_usb_hs_ahb_clk",
  103. "gcc_usb_hsic_ahb_clk",
  104. "gcc_usb_hsic_clk",
  105. "gcc_usb_hsic_io_cal_clk",
  106. "gcc_usb_hsic_io_cal_sleep_clk",
  107. "gcc_usb_hsic_system_clk",
  108. "gcc_usb2a_phy_sleep_clk",
  109. "gcc_usb_hs_phy_cfg_ahb_clk",
  110. "measure_only_bimc_clk",
  111. "measure_only_pcnoc_clk",
  112. "measure_only_qpic_clk",
  113. };
  114. static int gcc_debug_mux_sels[] = {
  115. 0x16A, /* apss_cc_debug_mux */
  116. 0x168, /* gcc_apss_ahb_clk */
  117. 0x169, /* gcc_apss_axi_clk */
  118. 0x50, /* gcc_apss_tcu_clk */
  119. 0x88, /* gcc_blsp1_ahb_clk */
  120. 0x8B, /* gcc_blsp1_qup1_i2c_apps_clk */
  121. 0x8A, /* gcc_blsp1_qup1_spi_apps_clk */
  122. 0x90, /* gcc_blsp1_qup2_i2c_apps_clk */
  123. 0x8E, /* gcc_blsp1_qup2_spi_apps_clk */
  124. 0x94, /* gcc_blsp1_qup3_i2c_apps_clk */
  125. 0x93, /* gcc_blsp1_qup3_spi_apps_clk */
  126. 0x99, /* gcc_blsp1_qup4_i2c_apps_clk */
  127. 0x98, /* gcc_blsp1_qup4_spi_apps_clk */
  128. 0x9D, /* gcc_blsp1_qup5_i2c_apps_clk */
  129. 0x9C, /* gcc_blsp1_qup5_spi_apps_clk */
  130. 0xA2, /* gcc_blsp1_qup6_i2c_apps_clk */
  131. 0xA1, /* gcc_blsp1_qup6_spi_apps_clk */
  132. 0x8C, /* gcc_blsp1_uart1_apps_clk */
  133. 0x91, /* gcc_blsp1_uart2_apps_clk */
  134. 0x95, /* gcc_blsp1_uart3_apps_clk */
  135. 0x9A, /* gcc_blsp1_uart4_apps_clk */
  136. 0x9E, /* gcc_blsp1_uart5_apps_clk */
  137. 0xA3, /* gcc_blsp1_uart6_apps_clk */
  138. 0xF8, /* gcc_boot_rom_ahb_clk */
  139. 0x138, /* gcc_crypto_clk */
  140. 0x13a, /* gcc_crypto_ahb_clk */
  141. 0x139, /* gcc_crypto_axi_clk */
  142. 0x278, /* gcc_dcc_clk */
  143. 0x01BC, /* gcc_emac_0_125m_clk */
  144. 0x1B9, /* gcc_emac_0_ahb_clk */
  145. 0x1B8, /* gcc_emac_0_axi_clk */
  146. 0x1BD, /* gcc_emac_0_rx_clk */
  147. 0x1BA, /* gcc_emac_0_sys_25m_clk */
  148. 0x1BE, /* gcc_emac_0_sys_clk */
  149. 0x1BB, /* gcc_emac_0_tx_clk */
  150. 0x10, /* gcc_gp1_clk */
  151. 0x11, /* gcc_gp2_clk */
  152. 0x12, /* gcc_gp3_clk */
  153. 0x30, /* gcc_mss_cfg_ahb_clk */
  154. 0x31, /* gcc_mss_q6_bimc_axi_clk */
  155. 0xD2, /* gcc_pdm2_clk */
  156. 0xD0, /* gcc_pdm_ahb_clk */
  157. 0xD8, /* gcc_prng_ahb_clk */
  158. 0x49, /* gcc_qdss_dap_clk */
  159. 0x68, /* gcc_sdcc1_apps_clk */
  160. 0x69, /* gcc_sdcc1_ahb_clk */
  161. 0x70, /* gcc_sdcc2_apps_clk */
  162. 0x71, /* gcc_sdcc2_ahb_clk */
  163. 0x5B, /* gcc_smmu_cfg_clk */
  164. 0x60, /* gcc_usb_hs_system_clk */
  165. 0x61, /* gcc_usb_hs_ahb_clk */
  166. 0x198, /* gcc_usb_hsic_ahb_clk */
  167. 0x19A, /* gcc_usb_hsic_clk */
  168. 0x19B, /* gcc_usb_hsic_io_cal_clk */
  169. 0x19C, /* gcc_usb_hsic_io_cal_sleep_clk */
  170. 0x199, /* gcc_usb_hsic_system_clk */
  171. 0x63, /* gcc_usb2a_phy_sleep_clk */
  172. 0x64, /* gcc_usb_hs_phy_cfg_ahb_clk */
  173. 0x155, /* measure_only_bimc_clk */
  174. 0x8, /* measure_only_pcnoc_clk */
  175. 0x78, /* measure_only_qpic_clk */
  176. };
  177. static struct clk_debug_mux gcc_debug_mux = {
  178. .priv = &debug_mux_priv,
  179. .debug_offset = 0x74000,
  180. .post_div_offset = 0x74000,
  181. .cbcr_offset = 0x74000,
  182. .en_mask = BIT(16),
  183. .src_sel_mask = 0x3FF,
  184. .src_sel_shift = 0x0,
  185. .post_div_mask = 0xF000,
  186. .post_div_shift = 12,
  187. .post_div_val = 0x4, /*post_dev_val 0x3: DIV4*/
  188. .mux_sels = gcc_debug_mux_sels,
  189. .hw.init = &(struct clk_init_data){
  190. .name = "gcc_debug_mux",
  191. .ops = &clk_debug_mux_ops,
  192. .parent_names = gcc_debug_mux_parent_names,
  193. .num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names),
  194. },
  195. };
  196. static struct mux_regmap_names mux_list[] = {
  197. { .mux = &apss_cc_debug_mux, .regmap_name = "qcom,cpucc" },
  198. { .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
  199. };
  200. static struct clk_dummy measure_only_bimc_clk = {
  201. .rrate = 1000,
  202. .hw.init = &(struct clk_init_data){
  203. .name = "measure_only_bimc_clk",
  204. .ops = &clk_dummy_ops,
  205. },
  206. };
  207. static struct clk_dummy measure_only_pcnoc_clk = {
  208. .rrate = 1000,
  209. .hw.init = &(struct clk_init_data){
  210. .name = "measure_only_pcnoc_clk",
  211. .ops = &clk_dummy_ops,
  212. },
  213. };
  214. static struct clk_dummy measure_only_apcs_clk = {
  215. .rrate = 1000,
  216. .hw.init = &(struct clk_init_data){
  217. .name = "measure_only_apcs_clk",
  218. .ops = &clk_dummy_ops,
  219. },
  220. };
  221. static struct clk_dummy measure_only_qpic_clk = {
  222. .rrate = 1000,
  223. .hw.init = &(struct clk_init_data){
  224. .name = "measure_only_qpic_clk",
  225. .ops = &clk_dummy_ops,
  226. },
  227. };
  228. static struct clk_hw *debugcc_mdm9607_hws[] = {
  229. &measure_only_bimc_clk.hw,
  230. &measure_only_pcnoc_clk.hw,
  231. &measure_only_apcs_clk.hw,
  232. &measure_only_qpic_clk.hw,
  233. };
  234. static const struct of_device_id clk_debug_match_table[] = {
  235. { .compatible = "qcom,mdm9607-debugcc" },
  236. { }
  237. };
  238. static int clk_debug_mdm9607_probe(struct platform_device *pdev)
  239. {
  240. struct clk *clk;
  241. int ret, i;
  242. BUILD_BUG_ON(ARRAY_SIZE(apss_cc_debug_mux_parent_names) !=
  243. ARRAY_SIZE(apss_cc_debug_mux_sels));
  244. BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) !=
  245. ARRAY_SIZE(gcc_debug_mux_sels));
  246. clk = devm_clk_get(&pdev->dev, "xo_clk_src");
  247. if (IS_ERR(clk)) {
  248. if (PTR_ERR(clk) != -EPROBE_DEFER)
  249. dev_err(&pdev->dev, "Unable to get xo clock\n");
  250. return PTR_ERR(clk);
  251. }
  252. debug_mux_priv.cxo = clk;
  253. for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
  254. if (IS_ERR_OR_NULL(mux_list[i].mux->regmap)) {
  255. ret = map_debug_bases(pdev, mux_list[i].regmap_name,
  256. mux_list[i].mux);
  257. if (ret == -EBADR)
  258. continue;
  259. else if (ret)
  260. return ret;
  261. }
  262. }
  263. for (i = 0; i < ARRAY_SIZE(debugcc_mdm9607_hws); i++) {
  264. clk = devm_clk_register(&pdev->dev, debugcc_mdm9607_hws[i]);
  265. if (IS_ERR(clk)) {
  266. dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
  267. clk_hw_get_name(debugcc_mdm9607_hws[i]),
  268. PTR_ERR(clk));
  269. return PTR_ERR(clk);
  270. }
  271. }
  272. for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
  273. ret = devm_clk_register_debug_mux(&pdev->dev, mux_list[i].mux);
  274. if (ret) {
  275. dev_err(&pdev->dev, "Unable to register mux clk %s, err:(%d)\n",
  276. qcom_clk_hw_get_name(&mux_list[i].mux->hw),
  277. ret);
  278. return ret;
  279. }
  280. }
  281. ret = clk_debug_measure_register(&gcc_debug_mux.hw);
  282. if (ret) {
  283. dev_err(&pdev->dev, "Could not register Measure clocks\n");
  284. return ret;
  285. }
  286. dev_info(&pdev->dev, "Registered debug measure clocks\n");
  287. return ret;
  288. }
  289. static struct platform_driver clk_debug_driver = {
  290. .probe = clk_debug_mdm9607_probe,
  291. .driver = {
  292. .name = "mdm9607-debugcc",
  293. .of_match_table = clk_debug_match_table,
  294. },
  295. };
  296. static int __init clk_debug_mdm9607_init(void)
  297. {
  298. return platform_driver_register(&clk_debug_driver);
  299. }
  300. fs_initcall(clk_debug_mdm9607_init);
  301. MODULE_DESCRIPTION("QTI DEBUG CC MDM9607 Driver");
  302. MODULE_LICENSE("GPL");