clk-pxa.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell PXA family clocks
  4. *
  5. * Copyright (C) 2014 Robert Jarzmik
  6. *
  7. * Common clock code for PXA clocks ("CKEN" type clocks + DT)
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/io.h>
  13. #include <linux/of.h>
  14. #include <linux/soc/pxa/smemc.h>
  15. #include <dt-bindings/clock/pxa-clock.h>
  16. #include "clk-pxa.h"
  17. #define KHz 1000
  18. #define MHz (1000 * 1000)
  19. #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
  20. #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
  21. #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
  22. #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
  23. #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
  24. #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
  25. #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
  26. #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
  27. #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
  28. #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
  29. #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
  30. #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
  31. #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
  32. #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
  33. #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
  34. #define MDREFR_DRI_MASK 0xFFF
  35. static DEFINE_SPINLOCK(pxa_clk_lock);
  36. static struct clk *pxa_clocks[CLK_MAX];
  37. static struct clk_onecell_data onecell_data = {
  38. .clks = pxa_clocks,
  39. .clk_num = CLK_MAX,
  40. };
  41. struct pxa_clk {
  42. struct clk_hw hw;
  43. struct clk_fixed_factor lp;
  44. struct clk_fixed_factor hp;
  45. struct clk_gate gate;
  46. bool (*is_in_low_power)(void);
  47. };
  48. #define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
  49. static unsigned long cken_recalc_rate(struct clk_hw *hw,
  50. unsigned long parent_rate)
  51. {
  52. struct pxa_clk *pclk = to_pxa_clk(hw);
  53. struct clk_fixed_factor *fix;
  54. if (!pclk->is_in_low_power || pclk->is_in_low_power())
  55. fix = &pclk->lp;
  56. else
  57. fix = &pclk->hp;
  58. __clk_hw_set_clk(&fix->hw, hw);
  59. return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
  60. }
  61. static const struct clk_ops cken_rate_ops = {
  62. .recalc_rate = cken_recalc_rate,
  63. };
  64. static u8 cken_get_parent(struct clk_hw *hw)
  65. {
  66. struct pxa_clk *pclk = to_pxa_clk(hw);
  67. if (!pclk->is_in_low_power)
  68. return 0;
  69. return pclk->is_in_low_power() ? 0 : 1;
  70. }
  71. static const struct clk_ops cken_mux_ops = {
  72. .get_parent = cken_get_parent,
  73. .set_parent = dummy_clk_set_parent,
  74. };
  75. void __init clkdev_pxa_register(int ckid, const char *con_id,
  76. const char *dev_id, struct clk *clk)
  77. {
  78. if (!IS_ERR(clk) && (ckid != CLK_NONE))
  79. pxa_clocks[ckid] = clk;
  80. if (!IS_ERR(clk))
  81. clk_register_clkdev(clk, con_id, dev_id);
  82. }
  83. int __init clk_pxa_cken_init(const struct desc_clk_cken *clks,
  84. int nb_clks, void __iomem *clk_regs)
  85. {
  86. int i;
  87. struct pxa_clk *pxa_clk;
  88. struct clk *clk;
  89. for (i = 0; i < nb_clks; i++) {
  90. pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
  91. if (!pxa_clk)
  92. return -ENOMEM;
  93. pxa_clk->is_in_low_power = clks[i].is_in_low_power;
  94. pxa_clk->lp = clks[i].lp;
  95. pxa_clk->hp = clks[i].hp;
  96. pxa_clk->gate = clks[i].gate;
  97. pxa_clk->gate.reg = clk_regs + clks[i].cken_reg;
  98. pxa_clk->gate.lock = &pxa_clk_lock;
  99. clk = clk_register_composite(NULL, clks[i].name,
  100. clks[i].parent_names, 2,
  101. &pxa_clk->hw, &cken_mux_ops,
  102. &pxa_clk->hw, &cken_rate_ops,
  103. &pxa_clk->gate.hw, &clk_gate_ops,
  104. clks[i].flags);
  105. clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
  106. clks[i].dev_id, clk);
  107. }
  108. return 0;
  109. }
  110. void __init clk_pxa_dt_common_init(struct device_node *np)
  111. {
  112. of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
  113. }
  114. void pxa2xx_core_turbo_switch(bool on)
  115. {
  116. unsigned long flags;
  117. unsigned int unused, clkcfg;
  118. local_irq_save(flags);
  119. asm("mrc p14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
  120. clkcfg &= ~CLKCFG_TURBO & ~CLKCFG_HALFTURBO;
  121. if (on)
  122. clkcfg |= CLKCFG_TURBO;
  123. clkcfg |= CLKCFG_FCS;
  124. asm volatile(
  125. " b 2f\n"
  126. " .align 5\n"
  127. "1: mcr p14, 0, %1, c6, c0, 0\n"
  128. " b 3f\n"
  129. "2: b 1b\n"
  130. "3: nop\n"
  131. : "=&r" (unused) : "r" (clkcfg));
  132. local_irq_restore(flags);
  133. }
  134. void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
  135. u32 (*mdrefr_dri)(unsigned int),
  136. void __iomem *cccr)
  137. {
  138. unsigned int clkcfg = freq->clkcfg;
  139. unsigned int unused, preset_mdrefr, postset_mdrefr;
  140. unsigned long flags;
  141. void __iomem *mdrefr = pxa_smemc_get_mdrefr();
  142. local_irq_save(flags);
  143. /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
  144. * we need to preset the smaller DRI before the change. If we're
  145. * speeding up we need to set the larger DRI value after the change.
  146. */
  147. preset_mdrefr = postset_mdrefr = readl(mdrefr);
  148. if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) {
  149. preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
  150. preset_mdrefr |= mdrefr_dri(freq->membus_khz);
  151. }
  152. postset_mdrefr =
  153. (postset_mdrefr & ~MDREFR_DRI_MASK) |
  154. mdrefr_dri(freq->membus_khz);
  155. /* If we're dividing the memory clock by two for the SDRAM clock, this
  156. * must be set prior to the change. Clearing the divide must be done
  157. * after the change.
  158. */
  159. if (freq->div2) {
  160. preset_mdrefr |= MDREFR_DB2_MASK;
  161. postset_mdrefr |= MDREFR_DB2_MASK;
  162. } else {
  163. postset_mdrefr &= ~MDREFR_DB2_MASK;
  164. }
  165. /* Set new the CCCR and prepare CLKCFG */
  166. writel(freq->cccr, cccr);
  167. asm volatile(
  168. " ldr r4, [%1]\n"
  169. " b 2f\n"
  170. " .align 5\n"
  171. "1: str %3, [%1] /* preset the MDREFR */\n"
  172. " mcr p14, 0, %2, c6, c0, 0 /* set CLKCFG[FCS] */\n"
  173. " str %4, [%1] /* postset the MDREFR */\n"
  174. " b 3f\n"
  175. "2: b 1b\n"
  176. "3: nop\n"
  177. : "=&r" (unused)
  178. : "r" (mdrefr), "r" (clkcfg), "r" (preset_mdrefr),
  179. "r" (postset_mdrefr)
  180. : "r4", "r5");
  181. local_irq_restore(flags);
  182. }
  183. int pxa2xx_determine_rate(struct clk_rate_request *req,
  184. struct pxa2xx_freq *freqs, int nb_freqs)
  185. {
  186. int i, closest_below = -1, closest_above = -1;
  187. unsigned long rate;
  188. for (i = 0; i < nb_freqs; i++) {
  189. rate = freqs[i].cpll;
  190. if (rate == req->rate)
  191. break;
  192. if (rate < req->min_rate)
  193. continue;
  194. if (rate > req->max_rate)
  195. continue;
  196. if (rate <= req->rate)
  197. closest_below = i;
  198. if ((rate >= req->rate) && (closest_above == -1))
  199. closest_above = i;
  200. }
  201. req->best_parent_hw = NULL;
  202. if (i < nb_freqs) {
  203. rate = req->rate;
  204. } else if (closest_below >= 0) {
  205. rate = freqs[closest_below].cpll;
  206. } else if (closest_above >= 0) {
  207. rate = freqs[closest_above].cpll;
  208. } else {
  209. pr_debug("%s(rate=%lu) no match\n", __func__, req->rate);
  210. return -EINVAL;
  211. }
  212. pr_debug("%s(rate=%lu) rate=%lu\n", __func__, req->rate, rate);
  213. req->rate = rate;
  214. return 0;
  215. }