common.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell EBU SoC common clock handling
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Gregory CLEMENT <[email protected]>
  8. * Sebastian Hesselbarth <[email protected]>
  9. * Andrew Lunn <[email protected]>
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/clk.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/io.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/syscore_ops.h>
  20. #include "common.h"
  21. /*
  22. * Core Clocks
  23. */
  24. #define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3)
  25. #define SSCG_SPREAD_DOWN 0x0
  26. #define SSCG_SPREAD_UP 0x1
  27. #define SSCG_SPREAD_CENTRAL 0x2
  28. #define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF)
  29. #define SSCG_CONF_HIGH(reg) ((reg) & 0xFF)
  30. static struct clk_onecell_data clk_data;
  31. /*
  32. * This function can be used by the Kirkwood, the Armada 370, the
  33. * Armada XP and the Armada 375 SoC. The name of the function was
  34. * chosen following the dt convention: using the first known SoC
  35. * compatible with it.
  36. */
  37. u32 kirkwood_fix_sscg_deviation(u32 system_clk)
  38. {
  39. struct device_node *sscg_np = NULL;
  40. void __iomem *sscg_map;
  41. u32 sscg_reg;
  42. s32 low_bound, high_bound;
  43. u64 freq_swing_half;
  44. sscg_np = of_find_node_by_name(NULL, "sscg");
  45. if (sscg_np == NULL) {
  46. pr_err("cannot get SSCG register node\n");
  47. return system_clk;
  48. }
  49. sscg_map = of_iomap(sscg_np, 0);
  50. if (sscg_map == NULL) {
  51. pr_err("cannot map SSCG register\n");
  52. goto out;
  53. }
  54. sscg_reg = readl(sscg_map);
  55. high_bound = SSCG_CONF_HIGH(sscg_reg);
  56. low_bound = SSCG_CONF_LOW(sscg_reg);
  57. if ((high_bound - low_bound) <= 0)
  58. goto out;
  59. /*
  60. * From Marvell engineer we got the following formula (when
  61. * this code was written, the datasheet was erroneous)
  62. * Spread percentage = 1/96 * (H - L) / H
  63. * H = SSCG_High_Boundary
  64. * L = SSCG_Low_Boundary
  65. *
  66. * As the deviation is half of spread then it lead to the
  67. * following formula in the code.
  68. *
  69. * To avoid an overflow and not lose any significant digit in
  70. * the same time we have to use a 64 bit integer.
  71. */
  72. freq_swing_half = (((u64)high_bound - (u64)low_bound)
  73. * (u64)system_clk);
  74. do_div(freq_swing_half, (2 * 96 * high_bound));
  75. switch (SSCG_CONF_MODE(sscg_reg)) {
  76. case SSCG_SPREAD_DOWN:
  77. system_clk -= freq_swing_half;
  78. break;
  79. case SSCG_SPREAD_UP:
  80. system_clk += freq_swing_half;
  81. break;
  82. case SSCG_SPREAD_CENTRAL:
  83. default:
  84. break;
  85. }
  86. iounmap(sscg_map);
  87. out:
  88. of_node_put(sscg_np);
  89. return system_clk;
  90. }
  91. void __init mvebu_coreclk_setup(struct device_node *np,
  92. const struct coreclk_soc_desc *desc)
  93. {
  94. const char *tclk_name = "tclk";
  95. const char *cpuclk_name = "cpuclk";
  96. void __iomem *base;
  97. unsigned long rate;
  98. int n;
  99. base = of_iomap(np, 0);
  100. if (WARN_ON(!base))
  101. return;
  102. /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
  103. clk_data.clk_num = 2 + desc->num_ratios;
  104. /* One more clock for the optional refclk */
  105. if (desc->get_refclk_freq)
  106. clk_data.clk_num += 1;
  107. clk_data.clks = kcalloc(clk_data.clk_num, sizeof(*clk_data.clks),
  108. GFP_KERNEL);
  109. if (WARN_ON(!clk_data.clks)) {
  110. iounmap(base);
  111. return;
  112. }
  113. /* Register TCLK */
  114. of_property_read_string_index(np, "clock-output-names", 0,
  115. &tclk_name);
  116. rate = desc->get_tclk_freq(base);
  117. clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0,
  118. rate);
  119. WARN_ON(IS_ERR(clk_data.clks[0]));
  120. /* Register CPU clock */
  121. of_property_read_string_index(np, "clock-output-names", 1,
  122. &cpuclk_name);
  123. rate = desc->get_cpu_freq(base);
  124. if (desc->is_sscg_enabled && desc->fix_sscg_deviation
  125. && desc->is_sscg_enabled(base))
  126. rate = desc->fix_sscg_deviation(rate);
  127. clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0,
  128. rate);
  129. WARN_ON(IS_ERR(clk_data.clks[1]));
  130. /* Register fixed-factor clocks derived from CPU clock */
  131. for (n = 0; n < desc->num_ratios; n++) {
  132. const char *rclk_name = desc->ratios[n].name;
  133. int mult, div;
  134. of_property_read_string_index(np, "clock-output-names",
  135. 2+n, &rclk_name);
  136. desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
  137. clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
  138. cpuclk_name, 0, mult, div);
  139. WARN_ON(IS_ERR(clk_data.clks[2+n]));
  140. }
  141. /* Register optional refclk */
  142. if (desc->get_refclk_freq) {
  143. const char *name = "refclk";
  144. of_property_read_string_index(np, "clock-output-names",
  145. 2 + desc->num_ratios, &name);
  146. rate = desc->get_refclk_freq(base);
  147. clk_data.clks[2 + desc->num_ratios] =
  148. clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  149. WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
  150. }
  151. /* SAR register isn't needed anymore */
  152. iounmap(base);
  153. of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  154. }
  155. /*
  156. * Clock Gating Control
  157. */
  158. DEFINE_SPINLOCK(ctrl_gating_lock);
  159. struct clk_gating_ctrl {
  160. spinlock_t *lock;
  161. struct clk **gates;
  162. int num_gates;
  163. void __iomem *base;
  164. u32 saved_reg;
  165. };
  166. static struct clk_gating_ctrl *ctrl;
  167. static struct clk *clk_gating_get_src(
  168. struct of_phandle_args *clkspec, void *data)
  169. {
  170. int n;
  171. if (clkspec->args_count < 1)
  172. return ERR_PTR(-EINVAL);
  173. for (n = 0; n < ctrl->num_gates; n++) {
  174. struct clk_gate *gate =
  175. to_clk_gate(__clk_get_hw(ctrl->gates[n]));
  176. if (clkspec->args[0] == gate->bit_idx)
  177. return ctrl->gates[n];
  178. }
  179. return ERR_PTR(-ENODEV);
  180. }
  181. static int mvebu_clk_gating_suspend(void)
  182. {
  183. ctrl->saved_reg = readl(ctrl->base);
  184. return 0;
  185. }
  186. static void mvebu_clk_gating_resume(void)
  187. {
  188. writel(ctrl->saved_reg, ctrl->base);
  189. }
  190. static struct syscore_ops clk_gate_syscore_ops = {
  191. .suspend = mvebu_clk_gating_suspend,
  192. .resume = mvebu_clk_gating_resume,
  193. };
  194. void __init mvebu_clk_gating_setup(struct device_node *np,
  195. const struct clk_gating_soc_desc *desc)
  196. {
  197. struct clk *clk;
  198. void __iomem *base;
  199. const char *default_parent = NULL;
  200. int n;
  201. if (ctrl) {
  202. pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n");
  203. return;
  204. }
  205. base = of_iomap(np, 0);
  206. if (WARN_ON(!base))
  207. return;
  208. clk = of_clk_get(np, 0);
  209. if (!IS_ERR(clk)) {
  210. default_parent = __clk_get_name(clk);
  211. clk_put(clk);
  212. }
  213. ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
  214. if (WARN_ON(!ctrl))
  215. goto ctrl_out;
  216. /* lock must already be initialized */
  217. ctrl->lock = &ctrl_gating_lock;
  218. ctrl->base = base;
  219. /* Count, allocate, and register clock gates */
  220. for (n = 0; desc[n].name;)
  221. n++;
  222. ctrl->num_gates = n;
  223. ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates),
  224. GFP_KERNEL);
  225. if (WARN_ON(!ctrl->gates))
  226. goto gates_out;
  227. for (n = 0; n < ctrl->num_gates; n++) {
  228. const char *parent =
  229. (desc[n].parent) ? desc[n].parent : default_parent;
  230. ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
  231. desc[n].flags, base, desc[n].bit_idx,
  232. 0, ctrl->lock);
  233. WARN_ON(IS_ERR(ctrl->gates[n]));
  234. }
  235. of_clk_add_provider(np, clk_gating_get_src, ctrl);
  236. register_syscore_ops(&clk_gate_syscore_ops);
  237. return;
  238. gates_out:
  239. kfree(ctrl);
  240. ctrl_out:
  241. iounmap(base);
  242. }