clk-mix.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * mmp mix(div and mux) clock operation source file
  4. *
  5. * Copyright (C) 2014 Marvell
  6. * Chao Xie <[email protected]>
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/slab.h>
  10. #include <linux/io.h>
  11. #include <linux/err.h>
  12. #include "clk.h"
  13. /*
  14. * The mix clock is a clock combined mux and div type clock.
  15. * Because the div field and mux field need to be set at same
  16. * time, we can not divide it into 2 types of clock
  17. */
  18. #define to_clk_mix(hw) container_of(hw, struct mmp_clk_mix, hw)
  19. static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
  20. {
  21. unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
  22. unsigned int maxdiv = 0;
  23. struct clk_div_table *clkt;
  24. if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
  25. return div_mask;
  26. if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
  27. return 1 << div_mask;
  28. if (mix->div_table) {
  29. for (clkt = mix->div_table; clkt->div; clkt++)
  30. if (clkt->div > maxdiv)
  31. maxdiv = clkt->div;
  32. return maxdiv;
  33. }
  34. return div_mask + 1;
  35. }
  36. static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
  37. {
  38. struct clk_div_table *clkt;
  39. if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
  40. return val;
  41. if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
  42. return 1 << val;
  43. if (mix->div_table) {
  44. for (clkt = mix->div_table; clkt->div; clkt++)
  45. if (clkt->val == val)
  46. return clkt->div;
  47. if (clkt->div == 0)
  48. return 0;
  49. }
  50. return val + 1;
  51. }
  52. static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val)
  53. {
  54. int num_parents = clk_hw_get_num_parents(&mix->hw);
  55. int i;
  56. if (mix->mux_flags & CLK_MUX_INDEX_BIT)
  57. return ffs(val) - 1;
  58. if (mix->mux_flags & CLK_MUX_INDEX_ONE)
  59. return val - 1;
  60. if (mix->mux_table) {
  61. for (i = 0; i < num_parents; i++)
  62. if (mix->mux_table[i] == val)
  63. return i;
  64. if (i == num_parents)
  65. return 0;
  66. }
  67. return val;
  68. }
  69. static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div)
  70. {
  71. struct clk_div_table *clkt;
  72. if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
  73. return div;
  74. if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
  75. return __ffs(div);
  76. if (mix->div_table) {
  77. for (clkt = mix->div_table; clkt->div; clkt++)
  78. if (clkt->div == div)
  79. return clkt->val;
  80. if (clkt->div == 0)
  81. return 0;
  82. }
  83. return div - 1;
  84. }
  85. static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux)
  86. {
  87. if (mix->mux_table)
  88. return mix->mux_table[mux];
  89. return mux;
  90. }
  91. static void _filter_clk_table(struct mmp_clk_mix *mix,
  92. struct mmp_clk_mix_clk_table *table,
  93. unsigned int table_size)
  94. {
  95. int i;
  96. struct mmp_clk_mix_clk_table *item;
  97. struct clk_hw *parent, *hw;
  98. unsigned long parent_rate;
  99. hw = &mix->hw;
  100. for (i = 0; i < table_size; i++) {
  101. item = &table[i];
  102. parent = clk_hw_get_parent_by_index(hw, item->parent_index);
  103. parent_rate = clk_hw_get_rate(parent);
  104. if (parent_rate % item->rate) {
  105. item->valid = 0;
  106. } else {
  107. item->divisor = parent_rate / item->rate;
  108. item->valid = 1;
  109. }
  110. }
  111. }
  112. static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,
  113. unsigned int change_mux, unsigned int change_div)
  114. {
  115. struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
  116. u8 width, shift;
  117. u32 mux_div, fc_req;
  118. int ret, timeout = 50;
  119. unsigned long flags = 0;
  120. if (!change_mux && !change_div)
  121. return -EINVAL;
  122. if (mix->lock)
  123. spin_lock_irqsave(mix->lock, flags);
  124. if (mix->type == MMP_CLK_MIX_TYPE_V1
  125. || mix->type == MMP_CLK_MIX_TYPE_V2)
  126. mux_div = readl(ri->reg_clk_ctrl);
  127. else
  128. mux_div = readl(ri->reg_clk_sel);
  129. if (change_div) {
  130. width = ri->width_div;
  131. shift = ri->shift_div;
  132. mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
  133. mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift);
  134. }
  135. if (change_mux) {
  136. width = ri->width_mux;
  137. shift = ri->shift_mux;
  138. mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
  139. mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift);
  140. }
  141. if (mix->type == MMP_CLK_MIX_TYPE_V1) {
  142. writel(mux_div, ri->reg_clk_ctrl);
  143. } else if (mix->type == MMP_CLK_MIX_TYPE_V2) {
  144. mux_div |= (1 << ri->bit_fc);
  145. writel(mux_div, ri->reg_clk_ctrl);
  146. do {
  147. fc_req = readl(ri->reg_clk_ctrl);
  148. timeout--;
  149. if (!(fc_req & (1 << ri->bit_fc)))
  150. break;
  151. } while (timeout);
  152. if (timeout == 0) {
  153. pr_err("%s:%s cannot do frequency change\n",
  154. __func__, clk_hw_get_name(&mix->hw));
  155. ret = -EBUSY;
  156. goto error;
  157. }
  158. } else {
  159. fc_req = readl(ri->reg_clk_ctrl);
  160. fc_req |= 1 << ri->bit_fc;
  161. writel(fc_req, ri->reg_clk_ctrl);
  162. writel(mux_div, ri->reg_clk_sel);
  163. fc_req &= ~(1 << ri->bit_fc);
  164. }
  165. ret = 0;
  166. error:
  167. if (mix->lock)
  168. spin_unlock_irqrestore(mix->lock, flags);
  169. return ret;
  170. }
  171. static int mmp_clk_mix_determine_rate(struct clk_hw *hw,
  172. struct clk_rate_request *req)
  173. {
  174. struct mmp_clk_mix *mix = to_clk_mix(hw);
  175. struct mmp_clk_mix_clk_table *item;
  176. struct clk_hw *parent, *parent_best;
  177. unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;
  178. unsigned long gap, gap_best;
  179. u32 div_val_max;
  180. unsigned int div;
  181. int i, j;
  182. mix_rate_best = 0;
  183. parent_rate_best = 0;
  184. gap_best = ULONG_MAX;
  185. parent_best = NULL;
  186. if (mix->table) {
  187. for (i = 0; i < mix->table_size; i++) {
  188. item = &mix->table[i];
  189. if (item->valid == 0)
  190. continue;
  191. parent = clk_hw_get_parent_by_index(hw,
  192. item->parent_index);
  193. parent_rate = clk_hw_get_rate(parent);
  194. mix_rate = parent_rate / item->divisor;
  195. gap = abs(mix_rate - req->rate);
  196. if (!parent_best || gap < gap_best) {
  197. parent_best = parent;
  198. parent_rate_best = parent_rate;
  199. mix_rate_best = mix_rate;
  200. gap_best = gap;
  201. if (gap_best == 0)
  202. goto found;
  203. }
  204. }
  205. } else {
  206. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  207. parent = clk_hw_get_parent_by_index(hw, i);
  208. parent_rate = clk_hw_get_rate(parent);
  209. div_val_max = _get_maxdiv(mix);
  210. for (j = 0; j < div_val_max; j++) {
  211. div = _get_div(mix, j);
  212. mix_rate = parent_rate / div;
  213. gap = abs(mix_rate - req->rate);
  214. if (!parent_best || gap < gap_best) {
  215. parent_best = parent;
  216. parent_rate_best = parent_rate;
  217. mix_rate_best = mix_rate;
  218. gap_best = gap;
  219. if (gap_best == 0)
  220. goto found;
  221. }
  222. }
  223. }
  224. }
  225. found:
  226. if (!parent_best)
  227. return -EINVAL;
  228. req->best_parent_rate = parent_rate_best;
  229. req->best_parent_hw = parent_best;
  230. req->rate = mix_rate_best;
  231. return 0;
  232. }
  233. static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw,
  234. unsigned long rate,
  235. unsigned long parent_rate,
  236. u8 index)
  237. {
  238. struct mmp_clk_mix *mix = to_clk_mix(hw);
  239. unsigned int div;
  240. u32 div_val, mux_val;
  241. div = parent_rate / rate;
  242. div_val = _get_div_val(mix, div);
  243. mux_val = _get_mux_val(mix, index);
  244. return _set_rate(mix, mux_val, div_val, 1, 1);
  245. }
  246. static u8 mmp_clk_mix_get_parent(struct clk_hw *hw)
  247. {
  248. struct mmp_clk_mix *mix = to_clk_mix(hw);
  249. struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
  250. unsigned long flags = 0;
  251. u32 mux_div = 0;
  252. u8 width, shift;
  253. u32 mux_val;
  254. if (mix->lock)
  255. spin_lock_irqsave(mix->lock, flags);
  256. if (mix->type == MMP_CLK_MIX_TYPE_V1
  257. || mix->type == MMP_CLK_MIX_TYPE_V2)
  258. mux_div = readl(ri->reg_clk_ctrl);
  259. else
  260. mux_div = readl(ri->reg_clk_sel);
  261. if (mix->lock)
  262. spin_unlock_irqrestore(mix->lock, flags);
  263. width = mix->reg_info.width_mux;
  264. shift = mix->reg_info.shift_mux;
  265. mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift);
  266. return _get_mux(mix, mux_val);
  267. }
  268. static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw,
  269. unsigned long parent_rate)
  270. {
  271. struct mmp_clk_mix *mix = to_clk_mix(hw);
  272. struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
  273. unsigned long flags = 0;
  274. u32 mux_div = 0;
  275. u8 width, shift;
  276. unsigned int div;
  277. if (mix->lock)
  278. spin_lock_irqsave(mix->lock, flags);
  279. if (mix->type == MMP_CLK_MIX_TYPE_V1
  280. || mix->type == MMP_CLK_MIX_TYPE_V2)
  281. mux_div = readl(ri->reg_clk_ctrl);
  282. else
  283. mux_div = readl(ri->reg_clk_sel);
  284. if (mix->lock)
  285. spin_unlock_irqrestore(mix->lock, flags);
  286. width = mix->reg_info.width_div;
  287. shift = mix->reg_info.shift_div;
  288. div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift));
  289. return parent_rate / div;
  290. }
  291. static int mmp_clk_set_parent(struct clk_hw *hw, u8 index)
  292. {
  293. struct mmp_clk_mix *mix = to_clk_mix(hw);
  294. struct mmp_clk_mix_clk_table *item;
  295. int i;
  296. u32 div_val, mux_val;
  297. if (mix->table) {
  298. for (i = 0; i < mix->table_size; i++) {
  299. item = &mix->table[i];
  300. if (item->valid == 0)
  301. continue;
  302. if (item->parent_index == index)
  303. break;
  304. }
  305. if (i < mix->table_size) {
  306. div_val = _get_div_val(mix, item->divisor);
  307. mux_val = _get_mux_val(mix, item->parent_index);
  308. } else
  309. return -EINVAL;
  310. } else {
  311. mux_val = _get_mux_val(mix, index);
  312. div_val = 0;
  313. }
  314. return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0);
  315. }
  316. static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  317. unsigned long best_parent_rate)
  318. {
  319. struct mmp_clk_mix *mix = to_clk_mix(hw);
  320. struct mmp_clk_mix_clk_table *item;
  321. unsigned long parent_rate;
  322. unsigned int best_divisor;
  323. struct clk_hw *parent;
  324. int i;
  325. best_divisor = best_parent_rate / rate;
  326. if (mix->table) {
  327. for (i = 0; i < mix->table_size; i++) {
  328. item = &mix->table[i];
  329. if (item->valid == 0)
  330. continue;
  331. parent = clk_hw_get_parent_by_index(hw,
  332. item->parent_index);
  333. parent_rate = clk_hw_get_rate(parent);
  334. if (parent_rate == best_parent_rate
  335. && item->divisor == best_divisor)
  336. break;
  337. }
  338. if (i < mix->table_size)
  339. return _set_rate(mix,
  340. _get_mux_val(mix, item->parent_index),
  341. _get_div_val(mix, item->divisor),
  342. 1, 1);
  343. else
  344. return -EINVAL;
  345. } else {
  346. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  347. parent = clk_hw_get_parent_by_index(hw, i);
  348. parent_rate = clk_hw_get_rate(parent);
  349. if (parent_rate == best_parent_rate)
  350. break;
  351. }
  352. if (i < clk_hw_get_num_parents(hw))
  353. return _set_rate(mix, _get_mux_val(mix, i),
  354. _get_div_val(mix, best_divisor), 1, 1);
  355. else
  356. return -EINVAL;
  357. }
  358. }
  359. static int mmp_clk_mix_init(struct clk_hw *hw)
  360. {
  361. struct mmp_clk_mix *mix = to_clk_mix(hw);
  362. if (mix->table)
  363. _filter_clk_table(mix, mix->table, mix->table_size);
  364. return 0;
  365. }
  366. const struct clk_ops mmp_clk_mix_ops = {
  367. .determine_rate = mmp_clk_mix_determine_rate,
  368. .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
  369. .set_rate = mmp_clk_set_rate,
  370. .set_parent = mmp_clk_set_parent,
  371. .get_parent = mmp_clk_mix_get_parent,
  372. .recalc_rate = mmp_clk_mix_recalc_rate,
  373. .init = mmp_clk_mix_init,
  374. };
  375. struct clk *mmp_clk_register_mix(struct device *dev,
  376. const char *name,
  377. const char * const *parent_names,
  378. u8 num_parents,
  379. unsigned long flags,
  380. struct mmp_clk_mix_config *config,
  381. spinlock_t *lock)
  382. {
  383. struct mmp_clk_mix *mix;
  384. struct clk *clk;
  385. struct clk_init_data init;
  386. size_t table_bytes;
  387. mix = kzalloc(sizeof(*mix), GFP_KERNEL);
  388. if (!mix)
  389. return ERR_PTR(-ENOMEM);
  390. init.name = name;
  391. init.flags = flags | CLK_GET_RATE_NOCACHE;
  392. init.parent_names = parent_names;
  393. init.num_parents = num_parents;
  394. init.ops = &mmp_clk_mix_ops;
  395. memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
  396. if (config->table) {
  397. table_bytes = sizeof(*config->table) * config->table_size;
  398. mix->table = kmemdup(config->table, table_bytes, GFP_KERNEL);
  399. if (!mix->table)
  400. goto free_mix;
  401. mix->table_size = config->table_size;
  402. }
  403. if (config->mux_table) {
  404. table_bytes = sizeof(u32) * num_parents;
  405. mix->mux_table = kmemdup(config->mux_table, table_bytes,
  406. GFP_KERNEL);
  407. if (!mix->mux_table) {
  408. kfree(mix->table);
  409. goto free_mix;
  410. }
  411. }
  412. mix->div_flags = config->div_flags;
  413. mix->mux_flags = config->mux_flags;
  414. mix->lock = lock;
  415. mix->hw.init = &init;
  416. if (config->reg_info.bit_fc >= 32)
  417. mix->type = MMP_CLK_MIX_TYPE_V1;
  418. else if (config->reg_info.reg_clk_sel)
  419. mix->type = MMP_CLK_MIX_TYPE_V3;
  420. else
  421. mix->type = MMP_CLK_MIX_TYPE_V2;
  422. clk = clk_register(dev, &mix->hw);
  423. if (IS_ERR(clk)) {
  424. kfree(mix->mux_table);
  425. kfree(mix->table);
  426. kfree(mix);
  427. }
  428. return clk;
  429. free_mix:
  430. kfree(mix);
  431. return ERR_PTR(-ENOMEM);
  432. }