clk-mux.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Owen Chen <[email protected]>
  5. */
  6. #ifndef __DRV_CLK_MTK_MUX_H
  7. #define __DRV_CLK_MTK_MUX_H
  8. #include <linux/notifier.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/types.h>
  11. struct clk;
  12. struct clk_hw_onecell_data;
  13. struct clk_ops;
  14. struct device;
  15. struct device_node;
  16. struct mtk_mux {
  17. int id;
  18. const char *name;
  19. const char * const *parent_names;
  20. unsigned int flags;
  21. u32 mux_ofs;
  22. u32 set_ofs;
  23. u32 clr_ofs;
  24. u32 upd_ofs;
  25. u8 mux_shift;
  26. u8 mux_width;
  27. u8 gate_shift;
  28. s8 upd_shift;
  29. const struct clk_ops *ops;
  30. signed char num_parents;
  31. };
  32. #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
  33. _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
  34. _gate, _upd_ofs, _upd, _flags, _ops) { \
  35. .id = _id, \
  36. .name = _name, \
  37. .mux_ofs = _mux_ofs, \
  38. .set_ofs = _mux_set_ofs, \
  39. .clr_ofs = _mux_clr_ofs, \
  40. .upd_ofs = _upd_ofs, \
  41. .mux_shift = _shift, \
  42. .mux_width = _width, \
  43. .gate_shift = _gate, \
  44. .upd_shift = _upd, \
  45. .parent_names = _parents, \
  46. .num_parents = ARRAY_SIZE(_parents), \
  47. .flags = _flags, \
  48. .ops = &_ops, \
  49. }
  50. extern const struct clk_ops mtk_mux_clr_set_upd_ops;
  51. extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
  52. #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
  53. _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
  54. _gate, _upd_ofs, _upd, _flags) \
  55. GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
  56. _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
  57. _gate, _upd_ofs, _upd, _flags, \
  58. mtk_mux_gate_clr_set_upd_ops)
  59. #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
  60. _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
  61. _gate, _upd_ofs, _upd) \
  62. MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
  63. _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
  64. _width, _gate, _upd_ofs, _upd, \
  65. CLK_SET_RATE_PARENT)
  66. #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
  67. _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
  68. _upd_ofs, _upd) \
  69. GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
  70. _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
  71. 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
  72. mtk_mux_clr_set_upd_ops)
  73. int mtk_clk_register_muxes(const struct mtk_mux *muxes,
  74. int num, struct device_node *node,
  75. spinlock_t *lock,
  76. struct clk_hw_onecell_data *clk_data);
  77. void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
  78. struct clk_hw_onecell_data *clk_data);
  79. struct mtk_mux_nb {
  80. struct notifier_block nb;
  81. const struct clk_ops *ops;
  82. u8 bypass_index; /* Which parent to temporarily use */
  83. u8 original_index; /* Set by notifier callback */
  84. };
  85. #define to_mtk_mux_nb(_nb) container_of(_nb, struct mtk_mux_nb, nb)
  86. int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk,
  87. struct mtk_mux_nb *mux_nb);
  88. #endif /* __DRV_CLK_MTK_MUX_H */