clk-mt8192-vdec.c 2.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright (c) 2021 MediaTek Inc.
  4. // Author: Chun-Jie Chen <[email protected]>
  5. #include <linux/clk-provider.h>
  6. #include <linux/of_device.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt8192-clk.h>
  11. static const struct mtk_gate_regs vdec0_cg_regs = {
  12. .set_ofs = 0x0,
  13. .clr_ofs = 0x4,
  14. .sta_ofs = 0x0,
  15. };
  16. static const struct mtk_gate_regs vdec1_cg_regs = {
  17. .set_ofs = 0x200,
  18. .clr_ofs = 0x204,
  19. .sta_ofs = 0x200,
  20. };
  21. static const struct mtk_gate_regs vdec2_cg_regs = {
  22. .set_ofs = 0x8,
  23. .clr_ofs = 0xc,
  24. .sta_ofs = 0x8,
  25. };
  26. #define GATE_VDEC0(_id, _name, _parent, _shift) \
  27. GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  28. #define GATE_VDEC1(_id, _name, _parent, _shift) \
  29. GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  30. #define GATE_VDEC2(_id, _name, _parent, _shift) \
  31. GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  32. static const struct mtk_gate vdec_clks[] = {
  33. /* VDEC0 */
  34. GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
  35. GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
  36. /* VDEC1 */
  37. GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
  38. GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
  39. /* VDEC2 */
  40. GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
  41. };
  42. static const struct mtk_gate vdec_soc_clks[] = {
  43. /* VDEC_SOC0 */
  44. GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
  45. GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
  46. /* VDEC_SOC1 */
  47. GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
  48. GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
  49. /* VDEC_SOC2 */
  50. GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
  51. };
  52. static const struct mtk_clk_desc vdec_desc = {
  53. .clks = vdec_clks,
  54. .num_clks = ARRAY_SIZE(vdec_clks),
  55. };
  56. static const struct mtk_clk_desc vdec_soc_desc = {
  57. .clks = vdec_soc_clks,
  58. .num_clks = ARRAY_SIZE(vdec_soc_clks),
  59. };
  60. static const struct of_device_id of_match_clk_mt8192_vdec[] = {
  61. {
  62. .compatible = "mediatek,mt8192-vdecsys",
  63. .data = &vdec_desc,
  64. }, {
  65. .compatible = "mediatek,mt8192-vdecsys_soc",
  66. .data = &vdec_soc_desc,
  67. }, {
  68. /* sentinel */
  69. }
  70. };
  71. static struct platform_driver clk_mt8192_vdec_drv = {
  72. .probe = mtk_clk_simple_probe,
  73. .remove = mtk_clk_simple_remove,
  74. .driver = {
  75. .name = "clk-mt8192-vdec",
  76. .of_match_table = of_match_clk_mt8192_vdec,
  77. },
  78. };
  79. builtin_platform_driver(clk_mt8192_vdec_drv);