clk-mt8186-apmixedsys.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright (c) 2022 MediaTek Inc.
  4. // Author: Chun-Jie Chen <[email protected]>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include <dt-bindings/clock/mt8186-clk.h>
  8. #include "clk-mtk.h"
  9. #include "clk-pll.h"
  10. #define MT8186_PLL_FMAX (3800UL * MHZ)
  11. #define MT8186_PLL_FMIN (1500UL * MHZ)
  12. #define MT8186_INTEGER_BITS (8)
  13. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  14. _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
  15. _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
  16. _pcw_reg) { \
  17. .id = _id, \
  18. .name = _name, \
  19. .reg = _reg, \
  20. .pwr_reg = _pwr_reg, \
  21. .en_mask = _en_mask, \
  22. .flags = _flags, \
  23. .rst_bar_mask = _rst_bar_mask, \
  24. .fmax = MT8186_PLL_FMAX, \
  25. .fmin = MT8186_PLL_FMIN, \
  26. .pcwbits = _pcwbits, \
  27. .pcwibits = MT8186_INTEGER_BITS, \
  28. .pd_reg = _pd_reg, \
  29. .pd_shift = _pd_shift, \
  30. .tuner_reg = _tuner_reg, \
  31. .tuner_en_reg = _tuner_en_reg, \
  32. .tuner_en_bit = _tuner_en_bit, \
  33. .pcw_reg = _pcw_reg, \
  34. .pcw_shift = 0, \
  35. .pcw_chg_reg = 0, \
  36. .en_reg = 0, \
  37. .pll_en_bit = 0, \
  38. }
  39. static const struct mtk_pll_data plls[] = {
  40. /*
  41. * armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
  42. * should not be closed in Linux world.
  43. */
  44. PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0,
  45. PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208),
  46. PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0,
  47. PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218),
  48. PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
  49. PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228),
  50. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
  51. HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248),
  52. PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000,
  53. HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328),
  54. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
  55. 0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390),
  56. PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
  57. 0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258),
  58. PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
  59. 0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360),
  60. PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
  61. 0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370),
  62. PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
  63. 0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308),
  64. PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
  65. 0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318),
  66. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
  67. 0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268),
  68. PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
  69. 0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C),
  70. PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
  71. 0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
  72. };
  73. static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
  74. { .compatible = "mediatek,mt8186-apmixedsys", },
  75. {}
  76. };
  77. static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
  78. {
  79. struct clk_hw_onecell_data *clk_data;
  80. struct device_node *node = pdev->dev.of_node;
  81. int r;
  82. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  83. if (!clk_data)
  84. return -ENOMEM;
  85. r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  86. if (r)
  87. goto free_apmixed_data;
  88. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  89. if (r)
  90. goto unregister_plls;
  91. platform_set_drvdata(pdev, clk_data);
  92. return r;
  93. unregister_plls:
  94. mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
  95. free_apmixed_data:
  96. mtk_free_clk_data(clk_data);
  97. return r;
  98. }
  99. static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
  100. {
  101. struct device_node *node = pdev->dev.of_node;
  102. struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
  103. of_clk_del_provider(node);
  104. mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
  105. mtk_free_clk_data(clk_data);
  106. return 0;
  107. }
  108. static struct platform_driver clk_mt8186_apmixed_drv = {
  109. .probe = clk_mt8186_apmixed_probe,
  110. .remove = clk_mt8186_apmixed_remove,
  111. .driver = {
  112. .name = "clk-mt8186-apmixed",
  113. .of_match_table = of_match_clk_mt8186_apmixed,
  114. },
  115. };
  116. builtin_platform_driver(clk_mt8186_apmixed_drv);