clk-mt8183-ipu_conn.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <[email protected]>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include "clk-mtk.h"
  8. #include "clk-gate.h"
  9. #include <dt-bindings/clock/mt8183-clk.h>
  10. static const struct mtk_gate_regs ipu_conn_cg_regs = {
  11. .set_ofs = 0x4,
  12. .clr_ofs = 0x8,
  13. .sta_ofs = 0x0,
  14. };
  15. static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
  16. .set_ofs = 0x10,
  17. .clr_ofs = 0x10,
  18. .sta_ofs = 0x10,
  19. };
  20. static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
  21. .set_ofs = 0x18,
  22. .clr_ofs = 0x18,
  23. .sta_ofs = 0x18,
  24. };
  25. static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
  26. .set_ofs = 0x1c,
  27. .clr_ofs = 0x1c,
  28. .sta_ofs = 0x1c,
  29. };
  30. static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
  31. .set_ofs = 0x20,
  32. .clr_ofs = 0x20,
  33. .sta_ofs = 0x20,
  34. };
  35. #define GATE_IPU_CONN(_id, _name, _parent, _shift) \
  36. GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
  37. &mtk_clk_gate_ops_setclr)
  38. #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
  39. GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
  40. &mtk_clk_gate_ops_no_setclr)
  41. #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
  42. GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
  43. &mtk_clk_gate_ops_no_setclr_inv)
  44. #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
  45. GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
  46. &mtk_clk_gate_ops_no_setclr_inv)
  47. #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
  48. GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
  49. &mtk_clk_gate_ops_no_setclr_inv)
  50. static const struct mtk_gate ipu_conn_clks[] = {
  51. GATE_IPU_CONN(CLK_IPU_CONN_IPU,
  52. "ipu_conn_ipu", "dsp_sel", 0),
  53. GATE_IPU_CONN(CLK_IPU_CONN_AHB,
  54. "ipu_conn_ahb", "dsp_sel", 1),
  55. GATE_IPU_CONN(CLK_IPU_CONN_AXI,
  56. "ipu_conn_axi", "dsp_sel", 2),
  57. GATE_IPU_CONN(CLK_IPU_CONN_ISP,
  58. "ipu_conn_isp", "dsp_sel", 3),
  59. GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
  60. "ipu_conn_cam_adl", "dsp_sel", 4),
  61. GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
  62. "ipu_conn_img_adl", "dsp_sel", 5),
  63. GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
  64. "ipu_conn_dap_rx", "dsp1_sel", 0),
  65. GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
  66. "ipu_conn_apb2axi", "dsp1_sel", 3),
  67. GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
  68. "ipu_conn_apb2ahb", "dsp1_sel", 20),
  69. GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
  70. "ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
  71. GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
  72. "ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
  73. GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
  74. "ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
  75. GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
  76. "ipu_conn_cab3to3", "dsp1_sel", 0),
  77. GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
  78. "ipu_conn_cab2to1", "dsp1_sel", 14),
  79. GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
  80. "ipu_conn_cab3to1_slice", "dsp1_sel", 17),
  81. };
  82. static const struct mtk_clk_desc ipu_conn_desc = {
  83. .clks = ipu_conn_clks,
  84. .num_clks = ARRAY_SIZE(ipu_conn_clks),
  85. };
  86. static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
  87. {
  88. .compatible = "mediatek,mt8183-ipu_conn",
  89. .data = &ipu_conn_desc,
  90. }, {
  91. /* sentinel */
  92. }
  93. };
  94. static struct platform_driver clk_mt8183_ipu_conn_drv = {
  95. .probe = mtk_clk_simple_probe,
  96. .remove = mtk_clk_simple_remove,
  97. .driver = {
  98. .name = "clk-mt8183-ipu_conn",
  99. .of_match_table = of_match_clk_mt8183_ipu_conn,
  100. },
  101. };
  102. builtin_platform_driver(clk_mt8183_ipu_conn_drv);