clk-mt6795-mfg.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022 Collabora Ltd.
  4. * Author: AngeloGioacchino Del Regno <[email protected]>
  5. */
  6. #include <dt-bindings/clock/mediatek,mt6795-clk.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include "clk-gate.h"
  10. #include "clk-mtk.h"
  11. static const struct mtk_gate_regs mfg_cg_regs = {
  12. .set_ofs = 0x4,
  13. .clr_ofs = 0x8,
  14. .sta_ofs = 0x0,
  15. };
  16. #define GATE_MFG(_id, _name, _parent, _shift) \
  17. GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  18. static const struct mtk_gate mfg_clks[] = {
  19. GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "axi_mfg_in_sel", 0),
  20. GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "mem_mfg_in_sel", 1),
  21. GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 2),
  22. GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m", 3),
  23. };
  24. static const struct mtk_clk_desc mfg_desc = {
  25. .clks = mfg_clks,
  26. .num_clks = ARRAY_SIZE(mfg_clks),
  27. };
  28. static const struct of_device_id of_match_clk_mt6795_mfg[] = {
  29. { .compatible = "mediatek,mt6795-mfgcfg", .data = &mfg_desc },
  30. { /* sentinel */ }
  31. };
  32. static struct platform_driver clk_mt6795_mfg_drv = {
  33. .driver = {
  34. .name = "clk-mt6795-mfg",
  35. .of_match_table = of_match_clk_mt6795_mfg,
  36. },
  37. .probe = mtk_clk_simple_probe,
  38. .remove = mtk_clk_simple_remove,
  39. };
  40. module_platform_driver(clk_mt6795_mfg_drv);
  41. MODULE_DESCRIPTION("MediaTek MT6795 mfg clocks driver");
  42. MODULE_LICENSE("GPL");