clk-mt6795-apmixedsys.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022 Collabora Ltd.
  4. * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  5. */
  6. #include <dt-bindings/clock/mediatek,mt6795-clk.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include "clk-mtk.h"
  10. #include "clk-pll.h"
  11. #define REG_REF2USB 0x8
  12. #define REG_AP_PLL_CON7 0x1c
  13. #define MD1_MTCMOS_OFF BIT(0)
  14. #define MD1_MEM_OFF BIT(1)
  15. #define MD1_CLK_OFF BIT(4)
  16. #define MD1_ISO_OFF BIT(8)
  17. #define MT6795_PLL_FMAX (3000UL * MHZ)
  18. #define MT6795_CON0_EN BIT(0)
  19. #define MT6795_CON0_RST_BAR BIT(24)
  20. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  21. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
  22. .id = _id, \
  23. .name = _name, \
  24. .reg = _reg, \
  25. .pwr_reg = _pwr_reg, \
  26. .en_mask = MT6795_CON0_EN | _en_mask, \
  27. .flags = _flags, \
  28. .rst_bar_mask = MT6795_CON0_RST_BAR, \
  29. .fmax = MT6795_PLL_FMAX, \
  30. .pcwbits = _pcwbits, \
  31. .pd_reg = _pd_reg, \
  32. .pd_shift = _pd_shift, \
  33. .tuner_reg = _tuner_reg, \
  34. .pcw_reg = _pcw_reg, \
  35. .pcw_shift = _pcw_shift, \
  36. .div_table = NULL, \
  37. .pll_en_bit = 0, \
  38. }
  39. static const struct mtk_pll_data plls[] = {
  40. PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
  41. 21, 0x204, 24, 0x0, 0x204, 0),
  42. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
  43. 21, 0x220, 4, 0x0, 0x224, 0),
  44. PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
  45. 7, 0x230, 4, 0x0, 0x234, 14),
  46. PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
  47. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
  48. PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
  49. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
  50. PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
  51. PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
  52. PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
  53. PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
  54. };
  55. static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
  56. {
  57. void __iomem *reg = base + REG_AP_PLL_CON7;
  58. /* Turn on MD1 internal clock */
  59. writel(readl(reg) & ~MD1_CLK_OFF, reg);
  60. /* Unlock MD1's MTCMOS power path */
  61. writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);
  62. /* Turn on ISO */
  63. writel(readl(reg) & ~MD1_ISO_OFF, reg);
  64. /* Turn on memory */
  65. writel(readl(reg) & ~MD1_MEM_OFF, reg);
  66. }
  67. static const struct of_device_id of_match_clk_mt6795_apmixed[] = {
  68. { .compatible = "mediatek,mt6795-apmixedsys" },
  69. { /* sentinel */ }
  70. };
  71. static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
  72. {
  73. struct clk_hw_onecell_data *clk_data;
  74. struct device *dev = &pdev->dev;
  75. struct device_node *node = dev->of_node;
  76. void __iomem *base;
  77. struct clk_hw *hw;
  78. int ret;
  79. base = devm_platform_ioremap_resource(pdev, 0);
  80. if (IS_ERR(base))
  81. return PTR_ERR(base);
  82. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  83. if (!clk_data)
  84. return -ENOMEM;
  85. ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  86. if (ret)
  87. goto free_clk_data;
  88. hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB);
  89. if (IS_ERR(hw)) {
  90. ret = PTR_ERR(hw);
  91. dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret);
  92. goto unregister_plls;
  93. }
  94. clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
  95. ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  96. if (ret) {
  97. dev_err(dev, "Cannot register clock provider: %d\n", ret);
  98. goto unregister_ref2usb;
  99. }
  100. /* Setup MD1 to avoid random crashes */
  101. dev_dbg(dev, "Performing initial setup for MD1\n");
  102. clk_mt6795_apmixed_setup_md1(base);
  103. return 0;
  104. unregister_ref2usb:
  105. mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
  106. unregister_plls:
  107. mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
  108. free_clk_data:
  109. mtk_free_clk_data(clk_data);
  110. return ret;
  111. }
  112. static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
  113. {
  114. struct device_node *node = pdev->dev.of_node;
  115. struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
  116. of_clk_del_provider(node);
  117. mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
  118. mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
  119. mtk_free_clk_data(clk_data);
  120. return 0;
  121. }
  122. static struct platform_driver clk_mt6795_apmixed_drv = {
  123. .probe = clk_mt6795_apmixed_probe,
  124. .remove = clk_mt6795_apmixed_remove,
  125. .driver = {
  126. .name = "clk-mt6795-apmixed",
  127. .of_match_table = of_match_clk_mt6795_apmixed,
  128. },
  129. };
  130. module_platform_driver(clk_mt6795_apmixed_drv);
  131. MODULE_DESCRIPTION("MediaTek MT6795 apmixed clocks driver");
  132. MODULE_LICENSE("GPL");