clk-imx8dxl-rsrc.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019~2020 NXP
  4. */
  5. #include <dt-bindings/firmware/imx/rsrc.h>
  6. #include "clk-scu.h"
  7. /* Keep sorted in the ascending order */
  8. static u32 imx8dxl_clk_scu_rsrc_table[] = {
  9. IMX_SC_R_SPI_0,
  10. IMX_SC_R_SPI_1,
  11. IMX_SC_R_SPI_2,
  12. IMX_SC_R_SPI_3,
  13. IMX_SC_R_UART_0,
  14. IMX_SC_R_UART_1,
  15. IMX_SC_R_UART_2,
  16. IMX_SC_R_UART_3,
  17. IMX_SC_R_I2C_0,
  18. IMX_SC_R_I2C_1,
  19. IMX_SC_R_I2C_2,
  20. IMX_SC_R_I2C_3,
  21. IMX_SC_R_ADC_0,
  22. IMX_SC_R_FTM_0,
  23. IMX_SC_R_FTM_1,
  24. IMX_SC_R_CAN_0,
  25. IMX_SC_R_LCD_0,
  26. IMX_SC_R_LCD_0_PWM_0,
  27. IMX_SC_R_PWM_0,
  28. IMX_SC_R_PWM_1,
  29. IMX_SC_R_PWM_2,
  30. IMX_SC_R_PWM_3,
  31. IMX_SC_R_PWM_4,
  32. IMX_SC_R_PWM_5,
  33. IMX_SC_R_PWM_6,
  34. IMX_SC_R_PWM_7,
  35. IMX_SC_R_GPT_0,
  36. IMX_SC_R_GPT_1,
  37. IMX_SC_R_GPT_2,
  38. IMX_SC_R_GPT_3,
  39. IMX_SC_R_GPT_4,
  40. IMX_SC_R_FSPI_0,
  41. IMX_SC_R_FSPI_1,
  42. IMX_SC_R_SDHC_0,
  43. IMX_SC_R_SDHC_1,
  44. IMX_SC_R_SDHC_2,
  45. IMX_SC_R_ENET_0,
  46. IMX_SC_R_ENET_1,
  47. IMX_SC_R_MLB_0,
  48. IMX_SC_R_USB_1,
  49. IMX_SC_R_NAND,
  50. IMX_SC_R_M4_0_I2C,
  51. IMX_SC_R_M4_0_UART,
  52. IMX_SC_R_ELCDIF_PLL,
  53. IMX_SC_R_AUDIO_PLL_0,
  54. IMX_SC_R_AUDIO_PLL_1,
  55. IMX_SC_R_AUDIO_CLK_0,
  56. IMX_SC_R_AUDIO_CLK_1,
  57. IMX_SC_R_A35
  58. };
  59. const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = {
  60. .rsrc = imx8dxl_clk_scu_rsrc_table,
  61. .num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table),
  62. };