clk-qoriq.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. * Copyright 2021 NXP
  5. *
  6. * clock driver for Freescale QorIQ SoCs.
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/fsl/guts.h>
  14. #include <linux/io.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/of.h>
  20. #include <linux/slab.h>
  21. #define PLL_DIV1 0
  22. #define PLL_DIV2 1
  23. #define PLL_DIV3 2
  24. #define PLL_DIV4 3
  25. #define PLATFORM_PLL 0
  26. #define CGA_PLL1 1
  27. #define CGA_PLL2 2
  28. #define CGA_PLL3 3
  29. #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
  30. #define CGB_PLL1 4
  31. #define CGB_PLL2 5
  32. #define MAX_PLL_DIV 32
  33. struct clockgen_pll_div {
  34. struct clk *clk;
  35. char name[32];
  36. };
  37. struct clockgen_pll {
  38. struct clockgen_pll_div div[MAX_PLL_DIV];
  39. };
  40. #define CLKSEL_VALID 1
  41. #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
  42. struct clockgen_sourceinfo {
  43. u32 flags; /* CLKSEL_xxx */
  44. int pll; /* CGx_PLLn */
  45. int div; /* PLL_DIVn */
  46. };
  47. #define NUM_MUX_PARENTS 16
  48. struct clockgen_muxinfo {
  49. struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
  50. };
  51. #define NUM_HWACCEL 5
  52. #define NUM_CMUX 8
  53. struct clockgen;
  54. /*
  55. * cmux freq must be >= platform pll.
  56. * If not set, cmux freq must be >= platform pll/2
  57. */
  58. #define CG_CMUX_GE_PLAT 1
  59. #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
  60. #define CG_VER3 4 /* version 3 cg: reg layout different */
  61. #define CG_LITTLE_ENDIAN 8
  62. struct clockgen_chipinfo {
  63. const char *compat, *guts_compat;
  64. const struct clockgen_muxinfo *cmux_groups[2];
  65. const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
  66. void (*init_periph)(struct clockgen *cg);
  67. int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
  68. u32 pll_mask; /* 1 << n bit set if PLL n is valid */
  69. u32 flags; /* CG_xxx */
  70. };
  71. struct clockgen {
  72. struct device_node *node;
  73. void __iomem *regs;
  74. struct clockgen_chipinfo info; /* mutable copy */
  75. struct clk *sysclk, *coreclk;
  76. struct clockgen_pll pll[6];
  77. struct clk *cmux[NUM_CMUX];
  78. struct clk *hwaccel[NUM_HWACCEL];
  79. struct clk *fman[2];
  80. struct ccsr_guts __iomem *guts;
  81. };
  82. static struct clockgen clockgen;
  83. static bool add_cpufreq_dev __initdata;
  84. static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
  85. {
  86. if (cg->info.flags & CG_LITTLE_ENDIAN)
  87. iowrite32(val, reg);
  88. else
  89. iowrite32be(val, reg);
  90. }
  91. static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
  92. {
  93. u32 val;
  94. if (cg->info.flags & CG_LITTLE_ENDIAN)
  95. val = ioread32(reg);
  96. else
  97. val = ioread32be(reg);
  98. return val;
  99. }
  100. static const struct clockgen_muxinfo p2041_cmux_grp1 = {
  101. {
  102. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  103. [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  104. [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  105. }
  106. };
  107. static const struct clockgen_muxinfo p2041_cmux_grp2 = {
  108. {
  109. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  110. [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  111. [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  112. }
  113. };
  114. static const struct clockgen_muxinfo p5020_cmux_grp1 = {
  115. {
  116. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  117. [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  118. [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
  119. }
  120. };
  121. static const struct clockgen_muxinfo p5020_cmux_grp2 = {
  122. {
  123. [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
  124. [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  125. [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  126. }
  127. };
  128. static const struct clockgen_muxinfo p5040_cmux_grp1 = {
  129. {
  130. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  131. [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  132. [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
  133. [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
  134. }
  135. };
  136. static const struct clockgen_muxinfo p5040_cmux_grp2 = {
  137. {
  138. [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
  139. [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
  140. [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  141. [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  142. }
  143. };
  144. static const struct clockgen_muxinfo p4080_cmux_grp1 = {
  145. {
  146. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  147. [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  148. [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  149. [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  150. [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
  151. }
  152. };
  153. static const struct clockgen_muxinfo p4080_cmux_grp2 = {
  154. {
  155. [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
  156. [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
  157. [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
  158. [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
  159. [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
  160. }
  161. };
  162. static const struct clockgen_muxinfo t1023_cmux = {
  163. {
  164. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  165. [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  166. }
  167. };
  168. static const struct clockgen_muxinfo t1040_cmux = {
  169. {
  170. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  171. [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  172. [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  173. [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  174. }
  175. };
  176. static const struct clockgen_muxinfo clockgen2_cmux_cga = {
  177. {
  178. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  179. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  180. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  181. {},
  182. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  183. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  184. { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
  185. {},
  186. { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
  187. { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
  188. { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
  189. },
  190. };
  191. static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
  192. {
  193. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  194. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  195. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  196. {},
  197. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  198. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  199. { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
  200. },
  201. };
  202. static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
  203. {
  204. { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
  205. { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
  206. { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
  207. {},
  208. { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
  209. { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
  210. { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
  211. },
  212. };
  213. static const struct clockgen_muxinfo ls1021a_cmux = {
  214. {
  215. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  216. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  217. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  218. }
  219. };
  220. static const struct clockgen_muxinfo ls1028a_hwa1 = {
  221. {
  222. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  223. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  224. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  225. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  226. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  227. {},
  228. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  229. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  230. },
  231. };
  232. static const struct clockgen_muxinfo ls1028a_hwa2 = {
  233. {
  234. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  235. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  236. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  237. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  238. { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
  239. {},
  240. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  241. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  242. },
  243. };
  244. static const struct clockgen_muxinfo ls1028a_hwa3 = {
  245. {
  246. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  247. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  248. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  249. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  250. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  251. {},
  252. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  253. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  254. },
  255. };
  256. static const struct clockgen_muxinfo ls1028a_hwa4 = {
  257. {
  258. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  259. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  260. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  261. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  262. { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
  263. {},
  264. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  265. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  266. },
  267. };
  268. static const struct clockgen_muxinfo ls1043a_hwa1 = {
  269. {
  270. {},
  271. {},
  272. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  273. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  274. {},
  275. {},
  276. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  277. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  278. },
  279. };
  280. static const struct clockgen_muxinfo ls1043a_hwa2 = {
  281. {
  282. {},
  283. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  284. {},
  285. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  286. },
  287. };
  288. static const struct clockgen_muxinfo ls1046a_hwa1 = {
  289. {
  290. {},
  291. {},
  292. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  293. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  294. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  295. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  296. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  297. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  298. },
  299. };
  300. static const struct clockgen_muxinfo ls1046a_hwa2 = {
  301. {
  302. {},
  303. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  304. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  305. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  306. {},
  307. {},
  308. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  309. },
  310. };
  311. static const struct clockgen_muxinfo ls1088a_hwa1 = {
  312. {
  313. {},
  314. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  315. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  316. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  317. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  318. {},
  319. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  320. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  321. },
  322. };
  323. static const struct clockgen_muxinfo ls1088a_hwa2 = {
  324. {
  325. {},
  326. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  327. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  328. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  329. { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
  330. {},
  331. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  332. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  333. },
  334. };
  335. static const struct clockgen_muxinfo ls1012a_cmux = {
  336. {
  337. [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  338. {},
  339. [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  340. }
  341. };
  342. static const struct clockgen_muxinfo t1023_hwa1 = {
  343. {
  344. {},
  345. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  346. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  347. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  348. },
  349. };
  350. static const struct clockgen_muxinfo t1023_hwa2 = {
  351. {
  352. [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  353. },
  354. };
  355. static const struct clockgen_muxinfo t2080_hwa1 = {
  356. {
  357. {},
  358. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  359. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  360. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  361. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  362. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  363. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  364. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  365. },
  366. };
  367. static const struct clockgen_muxinfo t2080_hwa2 = {
  368. {
  369. {},
  370. { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  371. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  372. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  373. { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
  374. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  375. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  376. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  377. },
  378. };
  379. static const struct clockgen_muxinfo t4240_hwa1 = {
  380. {
  381. { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
  382. { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
  383. { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  384. { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  385. { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  386. {},
  387. { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  388. { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  389. },
  390. };
  391. static const struct clockgen_muxinfo t4240_hwa4 = {
  392. {
  393. [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
  394. [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
  395. [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
  396. [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  397. [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
  398. },
  399. };
  400. static const struct clockgen_muxinfo t4240_hwa5 = {
  401. {
  402. [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
  403. [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
  404. [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
  405. [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  406. [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
  407. [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
  408. },
  409. };
  410. #define RCWSR7_FM1_CLK_SEL 0x40000000
  411. #define RCWSR7_FM2_CLK_SEL 0x20000000
  412. #define RCWSR7_HWA_ASYNC_DIV 0x04000000
  413. static void __init p2041_init_periph(struct clockgen *cg)
  414. {
  415. u32 reg;
  416. reg = ioread32be(&cg->guts->rcwsr[7]);
  417. if (reg & RCWSR7_FM1_CLK_SEL)
  418. cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
  419. else
  420. cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
  421. }
  422. static void __init p4080_init_periph(struct clockgen *cg)
  423. {
  424. u32 reg;
  425. reg = ioread32be(&cg->guts->rcwsr[7]);
  426. if (reg & RCWSR7_FM1_CLK_SEL)
  427. cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
  428. else
  429. cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
  430. if (reg & RCWSR7_FM2_CLK_SEL)
  431. cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
  432. else
  433. cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
  434. }
  435. static void __init p5020_init_periph(struct clockgen *cg)
  436. {
  437. u32 reg;
  438. int div = PLL_DIV2;
  439. reg = ioread32be(&cg->guts->rcwsr[7]);
  440. if (reg & RCWSR7_HWA_ASYNC_DIV)
  441. div = PLL_DIV4;
  442. if (reg & RCWSR7_FM1_CLK_SEL)
  443. cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
  444. else
  445. cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
  446. }
  447. static void __init p5040_init_periph(struct clockgen *cg)
  448. {
  449. u32 reg;
  450. int div = PLL_DIV2;
  451. reg = ioread32be(&cg->guts->rcwsr[7]);
  452. if (reg & RCWSR7_HWA_ASYNC_DIV)
  453. div = PLL_DIV4;
  454. if (reg & RCWSR7_FM1_CLK_SEL)
  455. cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
  456. else
  457. cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
  458. if (reg & RCWSR7_FM2_CLK_SEL)
  459. cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
  460. else
  461. cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
  462. }
  463. static void __init t1023_init_periph(struct clockgen *cg)
  464. {
  465. cg->fman[0] = cg->hwaccel[1];
  466. }
  467. static void __init t1040_init_periph(struct clockgen *cg)
  468. {
  469. cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
  470. }
  471. static void __init t2080_init_periph(struct clockgen *cg)
  472. {
  473. cg->fman[0] = cg->hwaccel[0];
  474. }
  475. static void __init t4240_init_periph(struct clockgen *cg)
  476. {
  477. cg->fman[0] = cg->hwaccel[3];
  478. cg->fman[1] = cg->hwaccel[4];
  479. }
  480. static const struct clockgen_chipinfo chipinfo[] = {
  481. {
  482. .compat = "fsl,b4420-clockgen",
  483. .guts_compat = "fsl,b4860-device-config",
  484. .init_periph = t2080_init_periph,
  485. .cmux_groups = {
  486. &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
  487. },
  488. .hwaccel = {
  489. &t2080_hwa1
  490. },
  491. .cmux_to_group = {
  492. 0, 1, 1, 1, -1
  493. },
  494. .pll_mask = BIT(PLATFORM_PLL) |
  495. BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
  496. BIT(CGB_PLL1) | BIT(CGB_PLL2),
  497. .flags = CG_PLL_8BIT,
  498. },
  499. {
  500. .compat = "fsl,b4860-clockgen",
  501. .guts_compat = "fsl,b4860-device-config",
  502. .init_periph = t2080_init_periph,
  503. .cmux_groups = {
  504. &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
  505. },
  506. .hwaccel = {
  507. &t2080_hwa1
  508. },
  509. .cmux_to_group = {
  510. 0, 1, 1, 1, -1
  511. },
  512. .pll_mask = BIT(PLATFORM_PLL) |
  513. BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
  514. BIT(CGB_PLL1) | BIT(CGB_PLL2),
  515. .flags = CG_PLL_8BIT,
  516. },
  517. {
  518. .compat = "fsl,ls1021a-clockgen",
  519. .cmux_groups = {
  520. &ls1021a_cmux
  521. },
  522. .cmux_to_group = {
  523. 0, -1
  524. },
  525. .pll_mask = BIT(PLATFORM_PLL) |
  526. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  527. },
  528. {
  529. .compat = "fsl,ls1028a-clockgen",
  530. .cmux_groups = {
  531. &clockgen2_cmux_cga12
  532. },
  533. .hwaccel = {
  534. &ls1028a_hwa1, &ls1028a_hwa2,
  535. &ls1028a_hwa3, &ls1028a_hwa4
  536. },
  537. .cmux_to_group = {
  538. 0, 0, 0, 0, -1
  539. },
  540. .pll_mask = BIT(PLATFORM_PLL) |
  541. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  542. .flags = CG_VER3 | CG_LITTLE_ENDIAN,
  543. },
  544. {
  545. .compat = "fsl,ls1043a-clockgen",
  546. .init_periph = t2080_init_periph,
  547. .cmux_groups = {
  548. &t1040_cmux
  549. },
  550. .hwaccel = {
  551. &ls1043a_hwa1, &ls1043a_hwa2
  552. },
  553. .cmux_to_group = {
  554. 0, -1
  555. },
  556. .pll_mask = BIT(PLATFORM_PLL) |
  557. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  558. .flags = CG_PLL_8BIT,
  559. },
  560. {
  561. .compat = "fsl,ls1046a-clockgen",
  562. .init_periph = t2080_init_periph,
  563. .cmux_groups = {
  564. &t1040_cmux
  565. },
  566. .hwaccel = {
  567. &ls1046a_hwa1, &ls1046a_hwa2
  568. },
  569. .cmux_to_group = {
  570. 0, -1
  571. },
  572. .pll_mask = BIT(PLATFORM_PLL) |
  573. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  574. .flags = CG_PLL_8BIT,
  575. },
  576. {
  577. .compat = "fsl,ls1088a-clockgen",
  578. .cmux_groups = {
  579. &clockgen2_cmux_cga12
  580. },
  581. .hwaccel = {
  582. &ls1088a_hwa1, &ls1088a_hwa2
  583. },
  584. .cmux_to_group = {
  585. 0, 0, -1
  586. },
  587. .pll_mask = BIT(PLATFORM_PLL) |
  588. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  589. .flags = CG_VER3 | CG_LITTLE_ENDIAN,
  590. },
  591. {
  592. .compat = "fsl,ls1012a-clockgen",
  593. .cmux_groups = {
  594. &ls1012a_cmux
  595. },
  596. .cmux_to_group = {
  597. 0, -1
  598. },
  599. .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
  600. },
  601. {
  602. .compat = "fsl,ls2080a-clockgen",
  603. .cmux_groups = {
  604. &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
  605. },
  606. .cmux_to_group = {
  607. 0, 0, 1, 1, -1
  608. },
  609. .pll_mask = BIT(PLATFORM_PLL) |
  610. BIT(CGA_PLL1) | BIT(CGA_PLL2) |
  611. BIT(CGB_PLL1) | BIT(CGB_PLL2),
  612. .flags = CG_VER3 | CG_LITTLE_ENDIAN,
  613. },
  614. {
  615. .compat = "fsl,lx2160a-clockgen",
  616. .cmux_groups = {
  617. &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
  618. },
  619. .cmux_to_group = {
  620. 0, 0, 0, 0, 1, 1, 1, 1, -1
  621. },
  622. .pll_mask = BIT(PLATFORM_PLL) |
  623. BIT(CGA_PLL1) | BIT(CGA_PLL2) |
  624. BIT(CGB_PLL1) | BIT(CGB_PLL2),
  625. .flags = CG_VER3 | CG_LITTLE_ENDIAN,
  626. },
  627. {
  628. .compat = "fsl,p2041-clockgen",
  629. .guts_compat = "fsl,qoriq-device-config-1.0",
  630. .init_periph = p2041_init_periph,
  631. .cmux_groups = {
  632. &p2041_cmux_grp1, &p2041_cmux_grp2
  633. },
  634. .cmux_to_group = {
  635. 0, 0, 1, 1, -1
  636. },
  637. .pll_mask = BIT(PLATFORM_PLL) |
  638. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  639. },
  640. {
  641. .compat = "fsl,p3041-clockgen",
  642. .guts_compat = "fsl,qoriq-device-config-1.0",
  643. .init_periph = p2041_init_periph,
  644. .cmux_groups = {
  645. &p2041_cmux_grp1, &p2041_cmux_grp2
  646. },
  647. .cmux_to_group = {
  648. 0, 0, 1, 1, -1
  649. },
  650. .pll_mask = BIT(PLATFORM_PLL) |
  651. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  652. },
  653. {
  654. .compat = "fsl,p4080-clockgen",
  655. .guts_compat = "fsl,qoriq-device-config-1.0",
  656. .init_periph = p4080_init_periph,
  657. .cmux_groups = {
  658. &p4080_cmux_grp1, &p4080_cmux_grp2
  659. },
  660. .cmux_to_group = {
  661. 0, 0, 0, 0, 1, 1, 1, 1, -1
  662. },
  663. .pll_mask = BIT(PLATFORM_PLL) |
  664. BIT(CGA_PLL1) | BIT(CGA_PLL2) |
  665. BIT(CGA_PLL3) | BIT(CGA_PLL4),
  666. },
  667. {
  668. .compat = "fsl,p5020-clockgen",
  669. .guts_compat = "fsl,qoriq-device-config-1.0",
  670. .init_periph = p5020_init_periph,
  671. .cmux_groups = {
  672. &p5020_cmux_grp1, &p5020_cmux_grp2
  673. },
  674. .cmux_to_group = {
  675. 0, 1, -1
  676. },
  677. .pll_mask = BIT(PLATFORM_PLL) |
  678. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  679. },
  680. {
  681. .compat = "fsl,p5040-clockgen",
  682. .guts_compat = "fsl,p5040-device-config",
  683. .init_periph = p5040_init_periph,
  684. .cmux_groups = {
  685. &p5040_cmux_grp1, &p5040_cmux_grp2
  686. },
  687. .cmux_to_group = {
  688. 0, 0, 1, 1, -1
  689. },
  690. .pll_mask = BIT(PLATFORM_PLL) |
  691. BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
  692. },
  693. {
  694. .compat = "fsl,t1023-clockgen",
  695. .guts_compat = "fsl,t1023-device-config",
  696. .init_periph = t1023_init_periph,
  697. .cmux_groups = {
  698. &t1023_cmux
  699. },
  700. .hwaccel = {
  701. &t1023_hwa1, &t1023_hwa2
  702. },
  703. .cmux_to_group = {
  704. 0, 0, -1
  705. },
  706. .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
  707. .flags = CG_PLL_8BIT,
  708. },
  709. {
  710. .compat = "fsl,t1040-clockgen",
  711. .guts_compat = "fsl,t1040-device-config",
  712. .init_periph = t1040_init_periph,
  713. .cmux_groups = {
  714. &t1040_cmux
  715. },
  716. .cmux_to_group = {
  717. 0, 0, 0, 0, -1
  718. },
  719. .pll_mask = BIT(PLATFORM_PLL) |
  720. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  721. .flags = CG_PLL_8BIT,
  722. },
  723. {
  724. .compat = "fsl,t2080-clockgen",
  725. .guts_compat = "fsl,t2080-device-config",
  726. .init_periph = t2080_init_periph,
  727. .cmux_groups = {
  728. &clockgen2_cmux_cga12
  729. },
  730. .hwaccel = {
  731. &t2080_hwa1, &t2080_hwa2
  732. },
  733. .cmux_to_group = {
  734. 0, -1
  735. },
  736. .pll_mask = BIT(PLATFORM_PLL) |
  737. BIT(CGA_PLL1) | BIT(CGA_PLL2),
  738. .flags = CG_PLL_8BIT,
  739. },
  740. {
  741. .compat = "fsl,t4240-clockgen",
  742. .guts_compat = "fsl,t4240-device-config",
  743. .init_periph = t4240_init_periph,
  744. .cmux_groups = {
  745. &clockgen2_cmux_cga, &clockgen2_cmux_cgb
  746. },
  747. .hwaccel = {
  748. &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
  749. },
  750. .cmux_to_group = {
  751. 0, 0, 1, -1
  752. },
  753. .pll_mask = BIT(PLATFORM_PLL) |
  754. BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
  755. BIT(CGB_PLL1) | BIT(CGB_PLL2),
  756. .flags = CG_PLL_8BIT,
  757. },
  758. {},
  759. };
  760. struct mux_hwclock {
  761. struct clk_hw hw;
  762. struct clockgen *cg;
  763. const struct clockgen_muxinfo *info;
  764. u32 __iomem *reg;
  765. u8 parent_to_clksel[NUM_MUX_PARENTS];
  766. s8 clksel_to_parent[NUM_MUX_PARENTS];
  767. int num_parents;
  768. };
  769. #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
  770. #define CLKSEL_MASK 0x78000000
  771. #define CLKSEL_SHIFT 27
  772. static int mux_set_parent(struct clk_hw *hw, u8 idx)
  773. {
  774. struct mux_hwclock *hwc = to_mux_hwclock(hw);
  775. u32 clksel;
  776. if (idx >= hwc->num_parents)
  777. return -EINVAL;
  778. clksel = hwc->parent_to_clksel[idx];
  779. cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
  780. return 0;
  781. }
  782. static u8 mux_get_parent(struct clk_hw *hw)
  783. {
  784. struct mux_hwclock *hwc = to_mux_hwclock(hw);
  785. u32 clksel;
  786. s8 ret;
  787. clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
  788. ret = hwc->clksel_to_parent[clksel];
  789. if (ret < 0) {
  790. pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
  791. return 0;
  792. }
  793. return ret;
  794. }
  795. static const struct clk_ops cmux_ops = {
  796. .get_parent = mux_get_parent,
  797. .set_parent = mux_set_parent,
  798. };
  799. /*
  800. * Don't allow setting for now, as the clock options haven't been
  801. * sanitized for additional restrictions.
  802. */
  803. static const struct clk_ops hwaccel_ops = {
  804. .get_parent = mux_get_parent,
  805. };
  806. static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
  807. struct mux_hwclock *hwc,
  808. int idx)
  809. {
  810. int pll, div;
  811. if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
  812. return NULL;
  813. pll = hwc->info->clksel[idx].pll;
  814. div = hwc->info->clksel[idx].div;
  815. return &cg->pll[pll].div[div];
  816. }
  817. static struct clk * __init create_mux_common(struct clockgen *cg,
  818. struct mux_hwclock *hwc,
  819. const struct clk_ops *ops,
  820. unsigned long min_rate,
  821. unsigned long max_rate,
  822. unsigned long pct80_rate,
  823. const char *fmt, int idx)
  824. {
  825. struct clk_init_data init = {};
  826. struct clk *clk;
  827. const struct clockgen_pll_div *div;
  828. const char *parent_names[NUM_MUX_PARENTS];
  829. char name[32];
  830. int i, j;
  831. snprintf(name, sizeof(name), fmt, idx);
  832. for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
  833. unsigned long rate;
  834. hwc->clksel_to_parent[i] = -1;
  835. div = get_pll_div(cg, hwc, i);
  836. if (!div)
  837. continue;
  838. rate = clk_get_rate(div->clk);
  839. if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
  840. rate > pct80_rate)
  841. continue;
  842. if (rate < min_rate)
  843. continue;
  844. if (rate > max_rate)
  845. continue;
  846. parent_names[j] = div->name;
  847. hwc->parent_to_clksel[j] = i;
  848. hwc->clksel_to_parent[i] = j;
  849. j++;
  850. }
  851. init.name = name;
  852. init.ops = ops;
  853. init.parent_names = parent_names;
  854. init.num_parents = hwc->num_parents = j;
  855. init.flags = 0;
  856. hwc->hw.init = &init;
  857. hwc->cg = cg;
  858. clk = clk_register(NULL, &hwc->hw);
  859. if (IS_ERR(clk)) {
  860. pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
  861. PTR_ERR(clk));
  862. kfree(hwc);
  863. return NULL;
  864. }
  865. return clk;
  866. }
  867. static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
  868. {
  869. struct mux_hwclock *hwc;
  870. const struct clockgen_pll_div *div;
  871. unsigned long plat_rate, min_rate;
  872. u64 max_rate, pct80_rate;
  873. u32 clksel;
  874. hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
  875. if (!hwc)
  876. return NULL;
  877. if (cg->info.flags & CG_VER3)
  878. hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
  879. else
  880. hwc->reg = cg->regs + 0x20 * idx;
  881. hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
  882. /*
  883. * Find the rate for the default clksel, and treat it as the
  884. * maximum rated core frequency. If this is an incorrect
  885. * assumption, certain clock options (possibly including the
  886. * default clksel) may be inappropriately excluded on certain
  887. * chips.
  888. */
  889. clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
  890. div = get_pll_div(cg, hwc, clksel);
  891. if (!div) {
  892. kfree(hwc);
  893. return NULL;
  894. }
  895. max_rate = clk_get_rate(div->clk);
  896. pct80_rate = max_rate * 8;
  897. do_div(pct80_rate, 10);
  898. plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
  899. if (cg->info.flags & CG_CMUX_GE_PLAT)
  900. min_rate = plat_rate;
  901. else
  902. min_rate = plat_rate / 2;
  903. return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
  904. pct80_rate, "cg-cmux%d", idx);
  905. }
  906. static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
  907. {
  908. struct mux_hwclock *hwc;
  909. hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
  910. if (!hwc)
  911. return NULL;
  912. hwc->reg = cg->regs + 0x20 * idx + 0x10;
  913. hwc->info = cg->info.hwaccel[idx];
  914. return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
  915. "cg-hwaccel%d", idx);
  916. }
  917. static void __init create_muxes(struct clockgen *cg)
  918. {
  919. int i;
  920. for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
  921. if (cg->info.cmux_to_group[i] < 0)
  922. break;
  923. if (cg->info.cmux_to_group[i] >=
  924. ARRAY_SIZE(cg->info.cmux_groups)) {
  925. WARN_ON_ONCE(1);
  926. continue;
  927. }
  928. cg->cmux[i] = create_one_cmux(cg, i);
  929. }
  930. for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
  931. if (!cg->info.hwaccel[i])
  932. continue;
  933. cg->hwaccel[i] = create_one_hwaccel(cg, i);
  934. }
  935. }
  936. static void __init _clockgen_init(struct device_node *np, bool legacy);
  937. /*
  938. * Legacy nodes may get probed before the parent clockgen node.
  939. * It is assumed that device trees with legacy nodes will not
  940. * contain a "clocks" property -- otherwise the input clocks may
  941. * not be initialized at this point.
  942. */
  943. static void __init legacy_init_clockgen(struct device_node *np)
  944. {
  945. if (!clockgen.node) {
  946. struct device_node *parent_np;
  947. parent_np = of_get_parent(np);
  948. _clockgen_init(parent_np, true);
  949. of_node_put(parent_np);
  950. }
  951. }
  952. /* Legacy node */
  953. static void __init core_mux_init(struct device_node *np)
  954. {
  955. struct clk *clk;
  956. struct resource res;
  957. int idx, rc;
  958. legacy_init_clockgen(np);
  959. if (of_address_to_resource(np, 0, &res))
  960. return;
  961. idx = (res.start & 0xf0) >> 5;
  962. clk = clockgen.cmux[idx];
  963. rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
  964. if (rc) {
  965. pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
  966. __func__, np, rc);
  967. return;
  968. }
  969. }
  970. static struct clk __init
  971. *sysclk_from_fixed(struct device_node *node, const char *name)
  972. {
  973. u32 rate;
  974. if (of_property_read_u32(node, "clock-frequency", &rate))
  975. return ERR_PTR(-ENODEV);
  976. return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  977. }
  978. static struct clk __init *input_clock(const char *name, struct clk *clk)
  979. {
  980. const char *input_name;
  981. /* Register the input clock under the desired name. */
  982. input_name = __clk_get_name(clk);
  983. clk = clk_register_fixed_factor(NULL, name, input_name,
  984. 0, 1, 1);
  985. if (IS_ERR(clk))
  986. pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
  987. PTR_ERR(clk));
  988. return clk;
  989. }
  990. static struct clk __init *input_clock_by_name(const char *name,
  991. const char *dtname)
  992. {
  993. struct clk *clk;
  994. clk = of_clk_get_by_name(clockgen.node, dtname);
  995. if (IS_ERR(clk))
  996. return clk;
  997. return input_clock(name, clk);
  998. }
  999. static struct clk __init *input_clock_by_index(const char *name, int idx)
  1000. {
  1001. struct clk *clk;
  1002. clk = of_clk_get(clockgen.node, 0);
  1003. if (IS_ERR(clk))
  1004. return clk;
  1005. return input_clock(name, clk);
  1006. }
  1007. static struct clk * __init create_sysclk(const char *name)
  1008. {
  1009. struct device_node *sysclk;
  1010. struct clk *clk;
  1011. clk = sysclk_from_fixed(clockgen.node, name);
  1012. if (!IS_ERR(clk))
  1013. return clk;
  1014. clk = input_clock_by_name(name, "sysclk");
  1015. if (!IS_ERR(clk))
  1016. return clk;
  1017. clk = input_clock_by_index(name, 0);
  1018. if (!IS_ERR(clk))
  1019. return clk;
  1020. sysclk = of_get_child_by_name(clockgen.node, "sysclk");
  1021. if (sysclk) {
  1022. clk = sysclk_from_fixed(sysclk, name);
  1023. of_node_put(sysclk);
  1024. if (!IS_ERR(clk))
  1025. return clk;
  1026. }
  1027. pr_err("%s: No input sysclk\n", __func__);
  1028. return NULL;
  1029. }
  1030. static struct clk * __init create_coreclk(const char *name)
  1031. {
  1032. struct clk *clk;
  1033. clk = input_clock_by_name(name, "coreclk");
  1034. if (!IS_ERR(clk))
  1035. return clk;
  1036. /*
  1037. * This indicates a mix of legacy nodes with the new coreclk
  1038. * mechanism, which should never happen. If this error occurs,
  1039. * don't use the wrong input clock just because coreclk isn't
  1040. * ready yet.
  1041. */
  1042. if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
  1043. return clk;
  1044. return NULL;
  1045. }
  1046. /* Legacy node */
  1047. static void __init sysclk_init(struct device_node *node)
  1048. {
  1049. struct clk *clk;
  1050. legacy_init_clockgen(node);
  1051. clk = clockgen.sysclk;
  1052. if (clk)
  1053. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  1054. }
  1055. #define PLL_KILL BIT(31)
  1056. static void __init create_one_pll(struct clockgen *cg, int idx)
  1057. {
  1058. u32 __iomem *reg;
  1059. u32 mult;
  1060. struct clockgen_pll *pll = &cg->pll[idx];
  1061. const char *input = "cg-sysclk";
  1062. int i;
  1063. if (!(cg->info.pll_mask & (1 << idx)))
  1064. return;
  1065. if (cg->coreclk && idx != PLATFORM_PLL) {
  1066. if (IS_ERR(cg->coreclk))
  1067. return;
  1068. input = "cg-coreclk";
  1069. }
  1070. if (cg->info.flags & CG_VER3) {
  1071. switch (idx) {
  1072. case PLATFORM_PLL:
  1073. reg = cg->regs + 0x60080;
  1074. break;
  1075. case CGA_PLL1:
  1076. reg = cg->regs + 0x80;
  1077. break;
  1078. case CGA_PLL2:
  1079. reg = cg->regs + 0xa0;
  1080. break;
  1081. case CGB_PLL1:
  1082. reg = cg->regs + 0x10080;
  1083. break;
  1084. case CGB_PLL2:
  1085. reg = cg->regs + 0x100a0;
  1086. break;
  1087. default:
  1088. WARN_ONCE(1, "index %d\n", idx);
  1089. return;
  1090. }
  1091. } else {
  1092. if (idx == PLATFORM_PLL)
  1093. reg = cg->regs + 0xc00;
  1094. else
  1095. reg = cg->regs + 0x800 + 0x20 * (idx - 1);
  1096. }
  1097. /* Get the multiple of PLL */
  1098. mult = cg_in(cg, reg);
  1099. /* Check if this PLL is disabled */
  1100. if (mult & PLL_KILL) {
  1101. pr_debug("%s(): pll %p disabled\n", __func__, reg);
  1102. return;
  1103. }
  1104. if ((cg->info.flags & CG_VER3) ||
  1105. ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
  1106. mult = (mult & GENMASK(8, 1)) >> 1;
  1107. else
  1108. mult = (mult & GENMASK(6, 1)) >> 1;
  1109. for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
  1110. struct clk *clk;
  1111. int ret;
  1112. /*
  1113. * For platform PLL, there are MAX_PLL_DIV divider clocks.
  1114. * For core PLL, there are 4 divider clocks at most.
  1115. */
  1116. if (idx != PLATFORM_PLL && i >= 4)
  1117. break;
  1118. snprintf(pll->div[i].name, sizeof(pll->div[i].name),
  1119. "cg-pll%d-div%d", idx, i + 1);
  1120. clk = clk_register_fixed_factor(NULL,
  1121. pll->div[i].name, input, 0, mult, i + 1);
  1122. if (IS_ERR(clk)) {
  1123. pr_err("%s: %s: register failed %ld\n",
  1124. __func__, pll->div[i].name, PTR_ERR(clk));
  1125. continue;
  1126. }
  1127. pll->div[i].clk = clk;
  1128. ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
  1129. if (ret != 0)
  1130. pr_err("%s: %s: register to lookup table failed %d\n",
  1131. __func__, pll->div[i].name, ret);
  1132. }
  1133. }
  1134. static void __init create_plls(struct clockgen *cg)
  1135. {
  1136. int i;
  1137. for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
  1138. create_one_pll(cg, i);
  1139. }
  1140. static void __init legacy_pll_init(struct device_node *np, int idx)
  1141. {
  1142. struct clockgen_pll *pll;
  1143. struct clk_onecell_data *onecell_data;
  1144. struct clk **subclks;
  1145. int count, rc;
  1146. legacy_init_clockgen(np);
  1147. pll = &clockgen.pll[idx];
  1148. count = of_property_count_strings(np, "clock-output-names");
  1149. BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
  1150. subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
  1151. if (!subclks)
  1152. return;
  1153. onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
  1154. if (!onecell_data)
  1155. goto err_clks;
  1156. if (count <= 3) {
  1157. subclks[0] = pll->div[0].clk;
  1158. subclks[1] = pll->div[1].clk;
  1159. subclks[2] = pll->div[3].clk;
  1160. } else {
  1161. subclks[0] = pll->div[0].clk;
  1162. subclks[1] = pll->div[1].clk;
  1163. subclks[2] = pll->div[2].clk;
  1164. subclks[3] = pll->div[3].clk;
  1165. }
  1166. onecell_data->clks = subclks;
  1167. onecell_data->clk_num = count;
  1168. rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
  1169. if (rc) {
  1170. pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
  1171. __func__, np, rc);
  1172. goto err_cell;
  1173. }
  1174. return;
  1175. err_cell:
  1176. kfree(onecell_data);
  1177. err_clks:
  1178. kfree(subclks);
  1179. }
  1180. /* Legacy node */
  1181. static void __init pltfrm_pll_init(struct device_node *np)
  1182. {
  1183. legacy_pll_init(np, PLATFORM_PLL);
  1184. }
  1185. /* Legacy node */
  1186. static void __init core_pll_init(struct device_node *np)
  1187. {
  1188. struct resource res;
  1189. int idx;
  1190. if (of_address_to_resource(np, 0, &res))
  1191. return;
  1192. if ((res.start & 0xfff) == 0xc00) {
  1193. /*
  1194. * ls1021a devtree labels the platform PLL
  1195. * with the core PLL compatible
  1196. */
  1197. pltfrm_pll_init(np);
  1198. } else {
  1199. idx = (res.start & 0xf0) >> 5;
  1200. legacy_pll_init(np, CGA_PLL1 + idx);
  1201. }
  1202. }
  1203. static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
  1204. {
  1205. struct clockgen *cg = data;
  1206. struct clk *clk;
  1207. struct clockgen_pll *pll;
  1208. u32 type, idx;
  1209. if (clkspec->args_count < 2) {
  1210. pr_err("%s: insufficient phandle args\n", __func__);
  1211. return ERR_PTR(-EINVAL);
  1212. }
  1213. type = clkspec->args[0];
  1214. idx = clkspec->args[1];
  1215. switch (type) {
  1216. case QORIQ_CLK_SYSCLK:
  1217. if (idx != 0)
  1218. goto bad_args;
  1219. clk = cg->sysclk;
  1220. break;
  1221. case QORIQ_CLK_CMUX:
  1222. if (idx >= ARRAY_SIZE(cg->cmux))
  1223. goto bad_args;
  1224. clk = cg->cmux[idx];
  1225. break;
  1226. case QORIQ_CLK_HWACCEL:
  1227. if (idx >= ARRAY_SIZE(cg->hwaccel))
  1228. goto bad_args;
  1229. clk = cg->hwaccel[idx];
  1230. break;
  1231. case QORIQ_CLK_FMAN:
  1232. if (idx >= ARRAY_SIZE(cg->fman))
  1233. goto bad_args;
  1234. clk = cg->fman[idx];
  1235. break;
  1236. case QORIQ_CLK_PLATFORM_PLL:
  1237. pll = &cg->pll[PLATFORM_PLL];
  1238. if (idx >= ARRAY_SIZE(pll->div))
  1239. goto bad_args;
  1240. clk = pll->div[idx].clk;
  1241. break;
  1242. case QORIQ_CLK_CORECLK:
  1243. if (idx != 0)
  1244. goto bad_args;
  1245. clk = cg->coreclk;
  1246. if (IS_ERR(clk))
  1247. clk = NULL;
  1248. break;
  1249. default:
  1250. goto bad_args;
  1251. }
  1252. if (!clk)
  1253. return ERR_PTR(-ENOENT);
  1254. return clk;
  1255. bad_args:
  1256. pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
  1257. return ERR_PTR(-EINVAL);
  1258. }
  1259. #ifdef CONFIG_PPC
  1260. #include <asm/mpc85xx.h>
  1261. static const u32 a4510_svrs[] __initconst = {
  1262. (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
  1263. (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
  1264. (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
  1265. (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
  1266. (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
  1267. (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
  1268. (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
  1269. (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
  1270. (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
  1271. (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
  1272. (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
  1273. (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
  1274. (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
  1275. };
  1276. #define SVR_SECURITY 0x80000 /* The Security (E) bit */
  1277. static bool __init has_erratum_a4510(void)
  1278. {
  1279. u32 svr = mfspr(SPRN_SVR);
  1280. int i;
  1281. svr &= ~SVR_SECURITY;
  1282. for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
  1283. if (svr == a4510_svrs[i])
  1284. return true;
  1285. }
  1286. return false;
  1287. }
  1288. #else
  1289. static bool __init has_erratum_a4510(void)
  1290. {
  1291. return false;
  1292. }
  1293. #endif
  1294. static void __init _clockgen_init(struct device_node *np, bool legacy)
  1295. {
  1296. int i, ret;
  1297. bool is_old_ls1021a = false;
  1298. /* May have already been called by a legacy probe */
  1299. if (clockgen.node)
  1300. return;
  1301. clockgen.node = np;
  1302. clockgen.regs = of_iomap(np, 0);
  1303. if (!clockgen.regs &&
  1304. of_device_is_compatible(of_root, "fsl,ls1021a")) {
  1305. /* Compatibility hack for old, broken device trees */
  1306. clockgen.regs = ioremap(0x1ee1000, 0x1000);
  1307. is_old_ls1021a = true;
  1308. }
  1309. if (!clockgen.regs) {
  1310. pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
  1311. return;
  1312. }
  1313. for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
  1314. if (of_device_is_compatible(np, chipinfo[i].compat))
  1315. break;
  1316. if (is_old_ls1021a &&
  1317. !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
  1318. break;
  1319. }
  1320. if (i == ARRAY_SIZE(chipinfo)) {
  1321. pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
  1322. goto err;
  1323. }
  1324. clockgen.info = chipinfo[i];
  1325. if (clockgen.info.guts_compat) {
  1326. struct device_node *guts;
  1327. guts = of_find_compatible_node(NULL, NULL,
  1328. clockgen.info.guts_compat);
  1329. if (guts) {
  1330. clockgen.guts = of_iomap(guts, 0);
  1331. if (!clockgen.guts) {
  1332. pr_err("%s: Couldn't map %pOF regs\n", __func__,
  1333. guts);
  1334. }
  1335. of_node_put(guts);
  1336. }
  1337. }
  1338. if (has_erratum_a4510())
  1339. clockgen.info.flags |= CG_CMUX_GE_PLAT;
  1340. clockgen.sysclk = create_sysclk("cg-sysclk");
  1341. clockgen.coreclk = create_coreclk("cg-coreclk");
  1342. create_plls(&clockgen);
  1343. create_muxes(&clockgen);
  1344. if (clockgen.info.init_periph)
  1345. clockgen.info.init_periph(&clockgen);
  1346. ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
  1347. if (ret) {
  1348. pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
  1349. __func__, np, ret);
  1350. }
  1351. /* Don't create cpufreq device for legacy clockgen blocks */
  1352. add_cpufreq_dev = !legacy;
  1353. return;
  1354. err:
  1355. iounmap(clockgen.regs);
  1356. clockgen.regs = NULL;
  1357. }
  1358. static void __init clockgen_init(struct device_node *np)
  1359. {
  1360. _clockgen_init(np, false);
  1361. }
  1362. static int __init clockgen_cpufreq_init(void)
  1363. {
  1364. struct platform_device *pdev;
  1365. if (add_cpufreq_dev) {
  1366. pdev = platform_device_register_simple("qoriq-cpufreq", -1,
  1367. NULL, 0);
  1368. if (IS_ERR(pdev))
  1369. pr_err("Couldn't register qoriq-cpufreq err=%ld\n",
  1370. PTR_ERR(pdev));
  1371. }
  1372. return 0;
  1373. }
  1374. device_initcall(clockgen_cpufreq_init);
  1375. CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
  1376. CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
  1377. CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
  1378. CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
  1379. CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
  1380. CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
  1381. CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
  1382. CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
  1383. CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
  1384. CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
  1385. CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
  1386. CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
  1387. CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
  1388. CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
  1389. CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
  1390. CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
  1391. CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
  1392. CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
  1393. CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
  1394. CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
  1395. CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
  1396. /* Legacy nodes */
  1397. CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
  1398. CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
  1399. CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
  1400. CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
  1401. CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
  1402. CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
  1403. CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
  1404. CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);