clk-palmas.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Clock driver for Palmas device.
  4. *
  5. * Copyright (c) 2013, NVIDIA Corporation.
  6. * Copyright (c) 2013-2014 Texas Instruments, Inc.
  7. *
  8. * Author: Laxman Dewangan <[email protected]>
  9. * Peter Ujfalusi <[email protected]>
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/mfd/palmas.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1 1
  20. #define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2 2
  21. #define PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP 3
  22. struct palmas_clk32k_desc {
  23. const char *clk_name;
  24. unsigned int control_reg;
  25. unsigned int enable_mask;
  26. unsigned int sleep_mask;
  27. unsigned int sleep_reqstr_id;
  28. int delay;
  29. };
  30. struct palmas_clock_info {
  31. struct device *dev;
  32. struct clk_hw hw;
  33. struct palmas *palmas;
  34. const struct palmas_clk32k_desc *clk_desc;
  35. int ext_control_pin;
  36. };
  37. static inline struct palmas_clock_info *to_palmas_clks_info(struct clk_hw *hw)
  38. {
  39. return container_of(hw, struct palmas_clock_info, hw);
  40. }
  41. static unsigned long palmas_clks_recalc_rate(struct clk_hw *hw,
  42. unsigned long parent_rate)
  43. {
  44. return 32768;
  45. }
  46. static int palmas_clks_prepare(struct clk_hw *hw)
  47. {
  48. struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
  49. int ret;
  50. ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
  51. cinfo->clk_desc->control_reg,
  52. cinfo->clk_desc->enable_mask,
  53. cinfo->clk_desc->enable_mask);
  54. if (ret < 0)
  55. dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
  56. cinfo->clk_desc->control_reg, ret);
  57. else if (cinfo->clk_desc->delay)
  58. udelay(cinfo->clk_desc->delay);
  59. return ret;
  60. }
  61. static void palmas_clks_unprepare(struct clk_hw *hw)
  62. {
  63. struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
  64. int ret;
  65. /*
  66. * Clock can be disabled through external pin if it is externally
  67. * controlled.
  68. */
  69. if (cinfo->ext_control_pin)
  70. return;
  71. ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
  72. cinfo->clk_desc->control_reg,
  73. cinfo->clk_desc->enable_mask, 0);
  74. if (ret < 0)
  75. dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
  76. cinfo->clk_desc->control_reg, ret);
  77. }
  78. static int palmas_clks_is_prepared(struct clk_hw *hw)
  79. {
  80. struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
  81. int ret;
  82. u32 val;
  83. if (cinfo->ext_control_pin)
  84. return 1;
  85. ret = palmas_read(cinfo->palmas, PALMAS_RESOURCE_BASE,
  86. cinfo->clk_desc->control_reg, &val);
  87. if (ret < 0) {
  88. dev_err(cinfo->dev, "Reg 0x%02x read failed, %d\n",
  89. cinfo->clk_desc->control_reg, ret);
  90. return ret;
  91. }
  92. return !!(val & cinfo->clk_desc->enable_mask);
  93. }
  94. static const struct clk_ops palmas_clks_ops = {
  95. .prepare = palmas_clks_prepare,
  96. .unprepare = palmas_clks_unprepare,
  97. .is_prepared = palmas_clks_is_prepared,
  98. .recalc_rate = palmas_clks_recalc_rate,
  99. };
  100. struct palmas_clks_of_match_data {
  101. struct clk_init_data init;
  102. const struct palmas_clk32k_desc desc;
  103. };
  104. static const struct palmas_clks_of_match_data palmas_of_clk32kg = {
  105. .init = {
  106. .name = "clk32kg",
  107. .ops = &palmas_clks_ops,
  108. .flags = CLK_IGNORE_UNUSED,
  109. },
  110. .desc = {
  111. .clk_name = "clk32kg",
  112. .control_reg = PALMAS_CLK32KG_CTRL,
  113. .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
  114. .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
  115. .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
  116. .delay = 200,
  117. },
  118. };
  119. static const struct palmas_clks_of_match_data palmas_of_clk32kgaudio = {
  120. .init = {
  121. .name = "clk32kgaudio",
  122. .ops = &palmas_clks_ops,
  123. .flags = CLK_IGNORE_UNUSED,
  124. },
  125. .desc = {
  126. .clk_name = "clk32kgaudio",
  127. .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
  128. .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
  129. .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
  130. .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
  131. .delay = 200,
  132. },
  133. };
  134. static const struct of_device_id palmas_clks_of_match[] = {
  135. {
  136. .compatible = "ti,palmas-clk32kg",
  137. .data = &palmas_of_clk32kg,
  138. },
  139. {
  140. .compatible = "ti,palmas-clk32kgaudio",
  141. .data = &palmas_of_clk32kgaudio,
  142. },
  143. { },
  144. };
  145. MODULE_DEVICE_TABLE(of, palmas_clks_of_match);
  146. static void palmas_clks_get_clk_data(struct platform_device *pdev,
  147. struct palmas_clock_info *cinfo)
  148. {
  149. struct device_node *node = pdev->dev.of_node;
  150. unsigned int prop;
  151. int ret;
  152. ret = of_property_read_u32(node, "ti,external-sleep-control",
  153. &prop);
  154. if (ret)
  155. return;
  156. switch (prop) {
  157. case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1:
  158. prop = PALMAS_EXT_CONTROL_ENABLE1;
  159. break;
  160. case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2:
  161. prop = PALMAS_EXT_CONTROL_ENABLE2;
  162. break;
  163. case PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP:
  164. prop = PALMAS_EXT_CONTROL_NSLEEP;
  165. break;
  166. default:
  167. dev_warn(&pdev->dev, "%pOFn: Invalid ext control option: %u\n",
  168. node, prop);
  169. prop = 0;
  170. break;
  171. }
  172. cinfo->ext_control_pin = prop;
  173. }
  174. static int palmas_clks_init_configure(struct palmas_clock_info *cinfo)
  175. {
  176. int ret;
  177. ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
  178. cinfo->clk_desc->control_reg,
  179. cinfo->clk_desc->sleep_mask, 0);
  180. if (ret < 0) {
  181. dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
  182. cinfo->clk_desc->control_reg, ret);
  183. return ret;
  184. }
  185. if (cinfo->ext_control_pin) {
  186. ret = clk_prepare(cinfo->hw.clk);
  187. if (ret < 0) {
  188. dev_err(cinfo->dev, "Clock prep failed, %d\n", ret);
  189. return ret;
  190. }
  191. ret = palmas_ext_control_req_config(cinfo->palmas,
  192. cinfo->clk_desc->sleep_reqstr_id,
  193. cinfo->ext_control_pin, true);
  194. if (ret < 0) {
  195. dev_err(cinfo->dev, "Ext config for %s failed, %d\n",
  196. cinfo->clk_desc->clk_name, ret);
  197. clk_unprepare(cinfo->hw.clk);
  198. return ret;
  199. }
  200. }
  201. return ret;
  202. }
  203. static int palmas_clks_probe(struct platform_device *pdev)
  204. {
  205. struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
  206. struct device_node *node = pdev->dev.of_node;
  207. const struct palmas_clks_of_match_data *match_data;
  208. struct palmas_clock_info *cinfo;
  209. int ret;
  210. match_data = of_device_get_match_data(&pdev->dev);
  211. if (!match_data)
  212. return 1;
  213. cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
  214. if (!cinfo)
  215. return -ENOMEM;
  216. palmas_clks_get_clk_data(pdev, cinfo);
  217. platform_set_drvdata(pdev, cinfo);
  218. cinfo->dev = &pdev->dev;
  219. cinfo->palmas = palmas;
  220. cinfo->clk_desc = &match_data->desc;
  221. cinfo->hw.init = &match_data->init;
  222. ret = devm_clk_hw_register(&pdev->dev, &cinfo->hw);
  223. if (ret) {
  224. dev_err(&pdev->dev, "Fail to register clock %s, %d\n",
  225. match_data->desc.clk_name, ret);
  226. return ret;
  227. }
  228. ret = palmas_clks_init_configure(cinfo);
  229. if (ret < 0) {
  230. dev_err(&pdev->dev, "Clock config failed, %d\n", ret);
  231. return ret;
  232. }
  233. ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &cinfo->hw);
  234. if (ret < 0)
  235. dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret);
  236. return ret;
  237. }
  238. static int palmas_clks_remove(struct platform_device *pdev)
  239. {
  240. of_clk_del_provider(pdev->dev.of_node);
  241. return 0;
  242. }
  243. static struct platform_driver palmas_clks_driver = {
  244. .driver = {
  245. .name = "palmas-clk",
  246. .of_match_table = palmas_clks_of_match,
  247. },
  248. .probe = palmas_clks_probe,
  249. .remove = palmas_clks_remove,
  250. };
  251. module_platform_driver(palmas_clks_driver);
  252. MODULE_DESCRIPTION("Clock driver for Palmas Series Devices");
  253. MODULE_ALIAS("platform:palmas-clk");
  254. MODULE_AUTHOR("Peter Ujfalusi <[email protected]>");
  255. MODULE_LICENSE("GPL v2");