clk-max9485.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/module.h>
  3. #include <linux/kernel.h>
  4. #include <linux/clk.h>
  5. #include <linux/clk-provider.h>
  6. #include <linux/err.h>
  7. #include <linux/errno.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/i2c.h>
  10. #include <linux/regulator/consumer.h>
  11. #include <dt-bindings/clock/maxim,max9485.h>
  12. #define MAX9485_NUM_CLKS 4
  13. /* This chip has only one register of 8 bit width. */
  14. #define MAX9485_FS_12KHZ (0 << 0)
  15. #define MAX9485_FS_32KHZ (1 << 0)
  16. #define MAX9485_FS_44_1KHZ (2 << 0)
  17. #define MAX9485_FS_48KHZ (3 << 0)
  18. #define MAX9485_SCALE_256 (0 << 2)
  19. #define MAX9485_SCALE_384 (1 << 2)
  20. #define MAX9485_SCALE_768 (2 << 2)
  21. #define MAX9485_DOUBLE BIT(4)
  22. #define MAX9485_CLKOUT1_ENABLE BIT(5)
  23. #define MAX9485_CLKOUT2_ENABLE BIT(6)
  24. #define MAX9485_MCLK_ENABLE BIT(7)
  25. #define MAX9485_FREQ_MASK 0x1f
  26. struct max9485_rate {
  27. unsigned long out;
  28. u8 reg_value;
  29. };
  30. /*
  31. * Ordered by frequency. For frequency the hardware can generate with
  32. * multiple settings, the one with lowest jitter is listed first.
  33. */
  34. static const struct max9485_rate max9485_rates[] = {
  35. { 3072000, MAX9485_FS_12KHZ | MAX9485_SCALE_256 },
  36. { 4608000, MAX9485_FS_12KHZ | MAX9485_SCALE_384 },
  37. { 8192000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 },
  38. { 9126000, MAX9485_FS_12KHZ | MAX9485_SCALE_768 },
  39. { 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
  40. { 12288000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 },
  41. { 12288000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 },
  42. { 16384000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
  43. { 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
  44. { 18384000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 },
  45. { 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
  46. { 24576000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
  47. { 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
  48. { 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 },
  49. { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
  50. { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
  51. { 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
  52. { 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 },
  53. { 49152000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
  54. { 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
  55. { 73728000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
  56. { } /* sentinel */
  57. };
  58. struct max9485_driver_data;
  59. struct max9485_clk_hw {
  60. struct clk_hw hw;
  61. struct clk_init_data init;
  62. u8 enable_bit;
  63. struct max9485_driver_data *drvdata;
  64. };
  65. struct max9485_driver_data {
  66. struct clk *xclk;
  67. struct i2c_client *client;
  68. u8 reg_value;
  69. struct regulator *supply;
  70. struct gpio_desc *reset_gpio;
  71. struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
  72. };
  73. static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
  74. {
  75. return container_of(hw, struct max9485_clk_hw, hw);
  76. }
  77. static int max9485_update_bits(struct max9485_driver_data *drvdata,
  78. u8 mask, u8 value)
  79. {
  80. int ret;
  81. drvdata->reg_value &= ~mask;
  82. drvdata->reg_value |= value;
  83. dev_dbg(&drvdata->client->dev,
  84. "updating mask 0x%02x value 0x%02x -> 0x%02x\n",
  85. mask, value, drvdata->reg_value);
  86. ret = i2c_master_send(drvdata->client,
  87. &drvdata->reg_value,
  88. sizeof(drvdata->reg_value));
  89. return ret < 0 ? ret : 0;
  90. }
  91. static int max9485_clk_prepare(struct clk_hw *hw)
  92. {
  93. struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
  94. return max9485_update_bits(clk_hw->drvdata,
  95. clk_hw->enable_bit,
  96. clk_hw->enable_bit);
  97. }
  98. static void max9485_clk_unprepare(struct clk_hw *hw)
  99. {
  100. struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
  101. max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
  102. }
  103. /*
  104. * CLKOUT - configurable clock output
  105. */
  106. static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
  107. unsigned long parent_rate)
  108. {
  109. struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
  110. const struct max9485_rate *entry;
  111. for (entry = max9485_rates; entry->out != 0; entry++)
  112. if (entry->out == rate)
  113. break;
  114. if (entry->out == 0)
  115. return -EINVAL;
  116. return max9485_update_bits(clk_hw->drvdata,
  117. MAX9485_FREQ_MASK,
  118. entry->reg_value);
  119. }
  120. static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
  121. unsigned long parent_rate)
  122. {
  123. struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
  124. struct max9485_driver_data *drvdata = clk_hw->drvdata;
  125. u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
  126. const struct max9485_rate *entry;
  127. for (entry = max9485_rates; entry->out != 0; entry++)
  128. if (val == entry->reg_value)
  129. return entry->out;
  130. return 0;
  131. }
  132. static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
  133. unsigned long *parent_rate)
  134. {
  135. const struct max9485_rate *curr, *prev = NULL;
  136. for (curr = max9485_rates; curr->out != 0; curr++) {
  137. /* Exact matches */
  138. if (curr->out == rate)
  139. return rate;
  140. /*
  141. * Find the first entry that has a frequency higher than the
  142. * requested one.
  143. */
  144. if (curr->out > rate) {
  145. unsigned int mid;
  146. /*
  147. * If this is the first entry, clamp the value to the
  148. * lowest possible frequency.
  149. */
  150. if (!prev)
  151. return curr->out;
  152. /*
  153. * Otherwise, determine whether the previous entry or
  154. * current one is closer.
  155. */
  156. mid = prev->out + ((curr->out - prev->out) / 2);
  157. return (mid > rate) ? prev->out : curr->out;
  158. }
  159. prev = curr;
  160. }
  161. /* If the last entry was still too high, clamp the value */
  162. return prev->out;
  163. }
  164. struct max9485_clk {
  165. const char *name;
  166. int parent_index;
  167. const struct clk_ops ops;
  168. u8 enable_bit;
  169. };
  170. static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
  171. [MAX9485_MCLKOUT] = {
  172. .name = "mclkout",
  173. .parent_index = -1,
  174. .enable_bit = MAX9485_MCLK_ENABLE,
  175. .ops = {
  176. .prepare = max9485_clk_prepare,
  177. .unprepare = max9485_clk_unprepare,
  178. },
  179. },
  180. [MAX9485_CLKOUT] = {
  181. .name = "clkout",
  182. .parent_index = -1,
  183. .ops = {
  184. .set_rate = max9485_clkout_set_rate,
  185. .round_rate = max9485_clkout_round_rate,
  186. .recalc_rate = max9485_clkout_recalc_rate,
  187. },
  188. },
  189. [MAX9485_CLKOUT1] = {
  190. .name = "clkout1",
  191. .parent_index = MAX9485_CLKOUT,
  192. .enable_bit = MAX9485_CLKOUT1_ENABLE,
  193. .ops = {
  194. .prepare = max9485_clk_prepare,
  195. .unprepare = max9485_clk_unprepare,
  196. },
  197. },
  198. [MAX9485_CLKOUT2] = {
  199. .name = "clkout2",
  200. .parent_index = MAX9485_CLKOUT,
  201. .enable_bit = MAX9485_CLKOUT2_ENABLE,
  202. .ops = {
  203. .prepare = max9485_clk_prepare,
  204. .unprepare = max9485_clk_unprepare,
  205. },
  206. },
  207. };
  208. static struct clk_hw *
  209. max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)
  210. {
  211. struct max9485_driver_data *drvdata = data;
  212. unsigned int idx = clkspec->args[0];
  213. return &drvdata->hw[idx].hw;
  214. }
  215. static int max9485_i2c_probe(struct i2c_client *client)
  216. {
  217. struct max9485_driver_data *drvdata;
  218. struct device *dev = &client->dev;
  219. const char *xclk_name;
  220. int i, ret;
  221. drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
  222. if (!drvdata)
  223. return -ENOMEM;
  224. drvdata->xclk = devm_clk_get(dev, "xclk");
  225. if (IS_ERR(drvdata->xclk))
  226. return PTR_ERR(drvdata->xclk);
  227. xclk_name = __clk_get_name(drvdata->xclk);
  228. drvdata->supply = devm_regulator_get(dev, "vdd");
  229. if (IS_ERR(drvdata->supply))
  230. return PTR_ERR(drvdata->supply);
  231. ret = regulator_enable(drvdata->supply);
  232. if (ret < 0)
  233. return ret;
  234. drvdata->reset_gpio =
  235. devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  236. if (IS_ERR(drvdata->reset_gpio))
  237. return PTR_ERR(drvdata->reset_gpio);
  238. i2c_set_clientdata(client, drvdata);
  239. drvdata->client = client;
  240. ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
  241. sizeof(drvdata->reg_value));
  242. if (ret < 0) {
  243. dev_warn(dev, "Unable to read device register: %d\n", ret);
  244. return ret;
  245. }
  246. for (i = 0; i < MAX9485_NUM_CLKS; i++) {
  247. int parent_index = max9485_clks[i].parent_index;
  248. const char *name;
  249. if (of_property_read_string_index(dev->of_node,
  250. "clock-output-names",
  251. i, &name) == 0) {
  252. drvdata->hw[i].init.name = name;
  253. } else {
  254. drvdata->hw[i].init.name = max9485_clks[i].name;
  255. }
  256. drvdata->hw[i].init.ops = &max9485_clks[i].ops;
  257. drvdata->hw[i].init.num_parents = 1;
  258. drvdata->hw[i].init.flags = 0;
  259. if (parent_index > 0) {
  260. drvdata->hw[i].init.parent_names =
  261. &drvdata->hw[parent_index].init.name;
  262. drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;
  263. } else {
  264. drvdata->hw[i].init.parent_names = &xclk_name;
  265. }
  266. drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
  267. drvdata->hw[i].hw.init = &drvdata->hw[i].init;
  268. drvdata->hw[i].drvdata = drvdata;
  269. ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);
  270. if (ret < 0)
  271. return ret;
  272. }
  273. return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);
  274. }
  275. static int __maybe_unused max9485_suspend(struct device *dev)
  276. {
  277. struct i2c_client *client = to_i2c_client(dev);
  278. struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
  279. gpiod_set_value_cansleep(drvdata->reset_gpio, 0);
  280. return 0;
  281. }
  282. static int __maybe_unused max9485_resume(struct device *dev)
  283. {
  284. struct i2c_client *client = to_i2c_client(dev);
  285. struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
  286. int ret;
  287. gpiod_set_value_cansleep(drvdata->reset_gpio, 1);
  288. ret = i2c_master_send(client, &drvdata->reg_value,
  289. sizeof(drvdata->reg_value));
  290. return ret < 0 ? ret : 0;
  291. }
  292. static const struct dev_pm_ops max9485_pm_ops = {
  293. SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
  294. };
  295. static const struct of_device_id max9485_dt_ids[] = {
  296. { .compatible = "maxim,max9485", },
  297. { }
  298. };
  299. MODULE_DEVICE_TABLE(of, max9485_dt_ids);
  300. static const struct i2c_device_id max9485_i2c_ids[] = {
  301. { .name = "max9485", },
  302. { }
  303. };
  304. MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);
  305. static struct i2c_driver max9485_driver = {
  306. .driver = {
  307. .name = "max9485",
  308. .pm = &max9485_pm_ops,
  309. .of_match_table = max9485_dt_ids,
  310. },
  311. .probe_new = max9485_i2c_probe,
  312. .id_table = max9485_i2c_ids,
  313. };
  314. module_i2c_driver(max9485_driver);
  315. MODULE_AUTHOR("Daniel Mack <[email protected]>");
  316. MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
  317. MODULE_LICENSE("GPL v2");