clk-kona.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Broadcom Corporation
  4. * Copyright 2013 Linaro Limited
  5. */
  6. #include "clk-kona.h"
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/clk-provider.h>
  11. /*
  12. * "Policies" affect the frequencies of bus clocks provided by a
  13. * CCU. (I believe these polices are named "Deep Sleep", "Economy",
  14. * "Normal", and "Turbo".) A lower policy number has lower power
  15. * consumption, and policy 2 is the default.
  16. */
  17. #define CCU_POLICY_COUNT 4
  18. #define CCU_ACCESS_PASSWORD 0xA5A500
  19. #define CLK_GATE_DELAY_LOOP 2000
  20. /* Bitfield operations */
  21. /* Produces a mask of set bits covering a range of a 32-bit value */
  22. static inline u32 bitfield_mask(u32 shift, u32 width)
  23. {
  24. return ((1 << width) - 1) << shift;
  25. }
  26. /* Extract the value of a bitfield found within a given register value */
  27. static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width)
  28. {
  29. return (reg_val & bitfield_mask(shift, width)) >> shift;
  30. }
  31. /* Replace the value of a bitfield found within a given register value */
  32. static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val)
  33. {
  34. u32 mask = bitfield_mask(shift, width);
  35. return (reg_val & ~mask) | (val << shift);
  36. }
  37. /* Divider and scaling helpers */
  38. /* Convert a divider into the scaled divisor value it represents. */
  39. static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div)
  40. {
  41. return (u64)reg_div + ((u64)1 << div->u.s.frac_width);
  42. }
  43. /*
  44. * Build a scaled divider value as close as possible to the
  45. * given whole part (div_value) and fractional part (expressed
  46. * in billionths).
  47. */
  48. u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths)
  49. {
  50. u64 combined;
  51. BUG_ON(!div_value);
  52. BUG_ON(billionths >= BILLION);
  53. combined = (u64)div_value * BILLION + billionths;
  54. combined <<= div->u.s.frac_width;
  55. return DIV_ROUND_CLOSEST_ULL(combined, BILLION);
  56. }
  57. /* The scaled minimum divisor representable by a divider */
  58. static inline u64
  59. scaled_div_min(struct bcm_clk_div *div)
  60. {
  61. if (divider_is_fixed(div))
  62. return (u64)div->u.fixed;
  63. return scaled_div_value(div, 0);
  64. }
  65. /* The scaled maximum divisor representable by a divider */
  66. u64 scaled_div_max(struct bcm_clk_div *div)
  67. {
  68. u32 reg_div;
  69. if (divider_is_fixed(div))
  70. return (u64)div->u.fixed;
  71. reg_div = ((u32)1 << div->u.s.width) - 1;
  72. return scaled_div_value(div, reg_div);
  73. }
  74. /*
  75. * Convert a scaled divisor into its divider representation as
  76. * stored in a divider register field.
  77. */
  78. static inline u32
  79. divider(struct bcm_clk_div *div, u64 scaled_div)
  80. {
  81. BUG_ON(scaled_div < scaled_div_min(div));
  82. BUG_ON(scaled_div > scaled_div_max(div));
  83. return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width));
  84. }
  85. /* Return a rate scaled for use when dividing by a scaled divisor. */
  86. static inline u64
  87. scale_rate(struct bcm_clk_div *div, u32 rate)
  88. {
  89. if (divider_is_fixed(div))
  90. return (u64)rate;
  91. return (u64)rate << div->u.s.frac_width;
  92. }
  93. /* CCU access */
  94. /* Read a 32-bit register value from a CCU's address space. */
  95. static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset)
  96. {
  97. return readl(ccu->base + reg_offset);
  98. }
  99. /* Write a 32-bit register value into a CCU's address space. */
  100. static inline void
  101. __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val)
  102. {
  103. writel(reg_val, ccu->base + reg_offset);
  104. }
  105. static inline unsigned long ccu_lock(struct ccu_data *ccu)
  106. {
  107. unsigned long flags;
  108. spin_lock_irqsave(&ccu->lock, flags);
  109. return flags;
  110. }
  111. static inline void ccu_unlock(struct ccu_data *ccu, unsigned long flags)
  112. {
  113. spin_unlock_irqrestore(&ccu->lock, flags);
  114. }
  115. /*
  116. * Enable/disable write access to CCU protected registers. The
  117. * WR_ACCESS register for all CCUs is at offset 0.
  118. */
  119. static inline void __ccu_write_enable(struct ccu_data *ccu)
  120. {
  121. if (ccu->write_enabled) {
  122. pr_err("%s: access already enabled for %s\n", __func__,
  123. ccu->name);
  124. return;
  125. }
  126. ccu->write_enabled = true;
  127. __ccu_write(ccu, 0, CCU_ACCESS_PASSWORD | 1);
  128. }
  129. static inline void __ccu_write_disable(struct ccu_data *ccu)
  130. {
  131. if (!ccu->write_enabled) {
  132. pr_err("%s: access wasn't enabled for %s\n", __func__,
  133. ccu->name);
  134. return;
  135. }
  136. __ccu_write(ccu, 0, CCU_ACCESS_PASSWORD);
  137. ccu->write_enabled = false;
  138. }
  139. /*
  140. * Poll a register in a CCU's address space, returning when the
  141. * specified bit in that register's value is set (or clear). Delay
  142. * a microsecond after each read of the register. Returns true if
  143. * successful, or false if we gave up trying.
  144. *
  145. * Caller must ensure the CCU lock is held.
  146. */
  147. static inline bool
  148. __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want)
  149. {
  150. unsigned int tries;
  151. u32 bit_mask = 1 << bit;
  152. for (tries = 0; tries < CLK_GATE_DELAY_LOOP; tries++) {
  153. u32 val;
  154. bool bit_val;
  155. val = __ccu_read(ccu, reg_offset);
  156. bit_val = (val & bit_mask) != 0;
  157. if (bit_val == want)
  158. return true;
  159. udelay(1);
  160. }
  161. pr_warn("%s: %s/0x%04x bit %u was never %s\n", __func__,
  162. ccu->name, reg_offset, bit, want ? "set" : "clear");
  163. return false;
  164. }
  165. /* Policy operations */
  166. static bool __ccu_policy_engine_start(struct ccu_data *ccu, bool sync)
  167. {
  168. struct bcm_policy_ctl *control = &ccu->policy.control;
  169. u32 offset;
  170. u32 go_bit;
  171. u32 mask;
  172. bool ret;
  173. /* If we don't need to control policy for this CCU, we're done. */
  174. if (!policy_ctl_exists(control))
  175. return true;
  176. offset = control->offset;
  177. go_bit = control->go_bit;
  178. /* Ensure we're not busy before we start */
  179. ret = __ccu_wait_bit(ccu, offset, go_bit, false);
  180. if (!ret) {
  181. pr_err("%s: ccu %s policy engine wouldn't go idle\n",
  182. __func__, ccu->name);
  183. return false;
  184. }
  185. /*
  186. * If it's a synchronous request, we'll wait for the voltage
  187. * and frequency of the active load to stabilize before
  188. * returning. To do this we select the active load by
  189. * setting the ATL bit.
  190. *
  191. * An asynchronous request instead ramps the voltage in the
  192. * background, and when that process stabilizes, the target
  193. * load is copied to the active load and the CCU frequency
  194. * is switched. We do this by selecting the target load
  195. * (ATL bit clear) and setting the request auto-copy (AC bit
  196. * set).
  197. *
  198. * Note, we do NOT read-modify-write this register.
  199. */
  200. mask = (u32)1 << go_bit;
  201. if (sync)
  202. mask |= 1 << control->atl_bit;
  203. else
  204. mask |= 1 << control->ac_bit;
  205. __ccu_write(ccu, offset, mask);
  206. /* Wait for indication that operation is complete. */
  207. ret = __ccu_wait_bit(ccu, offset, go_bit, false);
  208. if (!ret)
  209. pr_err("%s: ccu %s policy engine never started\n",
  210. __func__, ccu->name);
  211. return ret;
  212. }
  213. static bool __ccu_policy_engine_stop(struct ccu_data *ccu)
  214. {
  215. struct bcm_lvm_en *enable = &ccu->policy.enable;
  216. u32 offset;
  217. u32 enable_bit;
  218. bool ret;
  219. /* If we don't need to control policy for this CCU, we're done. */
  220. if (!policy_lvm_en_exists(enable))
  221. return true;
  222. /* Ensure we're not busy before we start */
  223. offset = enable->offset;
  224. enable_bit = enable->bit;
  225. ret = __ccu_wait_bit(ccu, offset, enable_bit, false);
  226. if (!ret) {
  227. pr_err("%s: ccu %s policy engine already stopped\n",
  228. __func__, ccu->name);
  229. return false;
  230. }
  231. /* Now set the bit to stop the engine (NO read-modify-write) */
  232. __ccu_write(ccu, offset, (u32)1 << enable_bit);
  233. /* Wait for indication that it has stopped. */
  234. ret = __ccu_wait_bit(ccu, offset, enable_bit, false);
  235. if (!ret)
  236. pr_err("%s: ccu %s policy engine never stopped\n",
  237. __func__, ccu->name);
  238. return ret;
  239. }
  240. /*
  241. * A CCU has four operating conditions ("policies"), and some clocks
  242. * can be disabled or enabled based on which policy is currently in
  243. * effect. Such clocks have a bit in a "policy mask" register for
  244. * each policy indicating whether the clock is enabled for that
  245. * policy or not. The bit position for a clock is the same for all
  246. * four registers, and the 32-bit registers are at consecutive
  247. * addresses.
  248. */
  249. static bool policy_init(struct ccu_data *ccu, struct bcm_clk_policy *policy)
  250. {
  251. u32 offset;
  252. u32 mask;
  253. int i;
  254. bool ret;
  255. if (!policy_exists(policy))
  256. return true;
  257. /*
  258. * We need to stop the CCU policy engine to allow update
  259. * of our policy bits.
  260. */
  261. if (!__ccu_policy_engine_stop(ccu)) {
  262. pr_err("%s: unable to stop CCU %s policy engine\n",
  263. __func__, ccu->name);
  264. return false;
  265. }
  266. /*
  267. * For now, if a clock defines its policy bit we just mark
  268. * it "enabled" for all four policies.
  269. */
  270. offset = policy->offset;
  271. mask = (u32)1 << policy->bit;
  272. for (i = 0; i < CCU_POLICY_COUNT; i++) {
  273. u32 reg_val;
  274. reg_val = __ccu_read(ccu, offset);
  275. reg_val |= mask;
  276. __ccu_write(ccu, offset, reg_val);
  277. offset += sizeof(u32);
  278. }
  279. /* We're done updating; fire up the policy engine again. */
  280. ret = __ccu_policy_engine_start(ccu, true);
  281. if (!ret)
  282. pr_err("%s: unable to restart CCU %s policy engine\n",
  283. __func__, ccu->name);
  284. return ret;
  285. }
  286. /* Gate operations */
  287. /* Determine whether a clock is gated. CCU lock must be held. */
  288. static bool
  289. __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate)
  290. {
  291. u32 bit_mask;
  292. u32 reg_val;
  293. /* If there is no gate we can assume it's enabled. */
  294. if (!gate_exists(gate))
  295. return true;
  296. bit_mask = 1 << gate->status_bit;
  297. reg_val = __ccu_read(ccu, gate->offset);
  298. return (reg_val & bit_mask) != 0;
  299. }
  300. /* Determine whether a clock is gated. */
  301. static bool
  302. is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate)
  303. {
  304. long flags;
  305. bool ret;
  306. /* Avoid taking the lock if we can */
  307. if (!gate_exists(gate))
  308. return true;
  309. flags = ccu_lock(ccu);
  310. ret = __is_clk_gate_enabled(ccu, gate);
  311. ccu_unlock(ccu, flags);
  312. return ret;
  313. }
  314. /*
  315. * Commit our desired gate state to the hardware.
  316. * Returns true if successful, false otherwise.
  317. */
  318. static bool
  319. __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate)
  320. {
  321. u32 reg_val;
  322. u32 mask;
  323. bool enabled = false;
  324. BUG_ON(!gate_exists(gate));
  325. if (!gate_is_sw_controllable(gate))
  326. return true; /* Nothing we can change */
  327. reg_val = __ccu_read(ccu, gate->offset);
  328. /* For a hardware/software gate, set which is in control */
  329. if (gate_is_hw_controllable(gate)) {
  330. mask = (u32)1 << gate->hw_sw_sel_bit;
  331. if (gate_is_sw_managed(gate))
  332. reg_val |= mask;
  333. else
  334. reg_val &= ~mask;
  335. }
  336. /*
  337. * If software is in control, enable or disable the gate.
  338. * If hardware is, clear the enabled bit for good measure.
  339. * If a software controlled gate can't be disabled, we're
  340. * required to write a 0 into the enable bit (but the gate
  341. * will be enabled).
  342. */
  343. mask = (u32)1 << gate->en_bit;
  344. if (gate_is_sw_managed(gate) && (enabled = gate_is_enabled(gate)) &&
  345. !gate_is_no_disable(gate))
  346. reg_val |= mask;
  347. else
  348. reg_val &= ~mask;
  349. __ccu_write(ccu, gate->offset, reg_val);
  350. /* For a hardware controlled gate, we're done */
  351. if (!gate_is_sw_managed(gate))
  352. return true;
  353. /* Otherwise wait for the gate to be in desired state */
  354. return __ccu_wait_bit(ccu, gate->offset, gate->status_bit, enabled);
  355. }
  356. /*
  357. * Initialize a gate. Our desired state (hardware/software select,
  358. * and if software, its enable state) is committed to hardware
  359. * without the usual checks to see if it's already set up that way.
  360. * Returns true if successful, false otherwise.
  361. */
  362. static bool gate_init(struct ccu_data *ccu, struct bcm_clk_gate *gate)
  363. {
  364. if (!gate_exists(gate))
  365. return true;
  366. return __gate_commit(ccu, gate);
  367. }
  368. /*
  369. * Set a gate to enabled or disabled state. Does nothing if the
  370. * gate is not currently under software control, or if it is already
  371. * in the requested state. Returns true if successful, false
  372. * otherwise. CCU lock must be held.
  373. */
  374. static bool
  375. __clk_gate(struct ccu_data *ccu, struct bcm_clk_gate *gate, bool enable)
  376. {
  377. bool ret;
  378. if (!gate_exists(gate) || !gate_is_sw_managed(gate))
  379. return true; /* Nothing to do */
  380. if (!enable && gate_is_no_disable(gate)) {
  381. pr_warn("%s: invalid gate disable request (ignoring)\n",
  382. __func__);
  383. return true;
  384. }
  385. if (enable == gate_is_enabled(gate))
  386. return true; /* No change */
  387. gate_flip_enabled(gate);
  388. ret = __gate_commit(ccu, gate);
  389. if (!ret)
  390. gate_flip_enabled(gate); /* Revert the change */
  391. return ret;
  392. }
  393. /* Enable or disable a gate. Returns 0 if successful, -EIO otherwise */
  394. static int clk_gate(struct ccu_data *ccu, const char *name,
  395. struct bcm_clk_gate *gate, bool enable)
  396. {
  397. unsigned long flags;
  398. bool success;
  399. /*
  400. * Avoid taking the lock if we can. We quietly ignore
  401. * requests to change state that don't make sense.
  402. */
  403. if (!gate_exists(gate) || !gate_is_sw_managed(gate))
  404. return 0;
  405. if (!enable && gate_is_no_disable(gate))
  406. return 0;
  407. flags = ccu_lock(ccu);
  408. __ccu_write_enable(ccu);
  409. success = __clk_gate(ccu, gate, enable);
  410. __ccu_write_disable(ccu);
  411. ccu_unlock(ccu, flags);
  412. if (success)
  413. return 0;
  414. pr_err("%s: failed to %s gate for %s\n", __func__,
  415. enable ? "enable" : "disable", name);
  416. return -EIO;
  417. }
  418. /* Hysteresis operations */
  419. /*
  420. * If a clock gate requires a turn-off delay it will have
  421. * "hysteresis" register bits defined. The first, if set, enables
  422. * the delay; and if enabled, the second bit determines whether the
  423. * delay is "low" or "high" (1 means high). For now, if it's
  424. * defined for a clock, we set it.
  425. */
  426. static bool hyst_init(struct ccu_data *ccu, struct bcm_clk_hyst *hyst)
  427. {
  428. u32 offset;
  429. u32 reg_val;
  430. u32 mask;
  431. if (!hyst_exists(hyst))
  432. return true;
  433. offset = hyst->offset;
  434. mask = (u32)1 << hyst->en_bit;
  435. mask |= (u32)1 << hyst->val_bit;
  436. reg_val = __ccu_read(ccu, offset);
  437. reg_val |= mask;
  438. __ccu_write(ccu, offset, reg_val);
  439. return true;
  440. }
  441. /* Trigger operations */
  442. /*
  443. * Caller must ensure CCU lock is held and access is enabled.
  444. * Returns true if successful, false otherwise.
  445. */
  446. static bool __clk_trigger(struct ccu_data *ccu, struct bcm_clk_trig *trig)
  447. {
  448. /* Trigger the clock and wait for it to finish */
  449. __ccu_write(ccu, trig->offset, 1 << trig->bit);
  450. return __ccu_wait_bit(ccu, trig->offset, trig->bit, false);
  451. }
  452. /* Divider operations */
  453. /* Read a divider value and return the scaled divisor it represents. */
  454. static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div)
  455. {
  456. unsigned long flags;
  457. u32 reg_val;
  458. u32 reg_div;
  459. if (divider_is_fixed(div))
  460. return (u64)div->u.fixed;
  461. flags = ccu_lock(ccu);
  462. reg_val = __ccu_read(ccu, div->u.s.offset);
  463. ccu_unlock(ccu, flags);
  464. /* Extract the full divider field from the register value */
  465. reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width);
  466. /* Return the scaled divisor value it represents */
  467. return scaled_div_value(div, reg_div);
  468. }
  469. /*
  470. * Convert a divider's scaled divisor value into its recorded form
  471. * and commit it into the hardware divider register.
  472. *
  473. * Returns 0 on success. Returns -EINVAL for invalid arguments.
  474. * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
  475. */
  476. static int __div_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate,
  477. struct bcm_clk_div *div, struct bcm_clk_trig *trig)
  478. {
  479. bool enabled;
  480. u32 reg_div;
  481. u32 reg_val;
  482. int ret = 0;
  483. BUG_ON(divider_is_fixed(div));
  484. /*
  485. * If we're just initializing the divider, and no initial
  486. * state was defined in the device tree, we just find out
  487. * what its current value is rather than updating it.
  488. */
  489. if (div->u.s.scaled_div == BAD_SCALED_DIV_VALUE) {
  490. reg_val = __ccu_read(ccu, div->u.s.offset);
  491. reg_div = bitfield_extract(reg_val, div->u.s.shift,
  492. div->u.s.width);
  493. div->u.s.scaled_div = scaled_div_value(div, reg_div);
  494. return 0;
  495. }
  496. /* Convert the scaled divisor to the value we need to record */
  497. reg_div = divider(div, div->u.s.scaled_div);
  498. /* Clock needs to be enabled before changing the rate */
  499. enabled = __is_clk_gate_enabled(ccu, gate);
  500. if (!enabled && !__clk_gate(ccu, gate, true)) {
  501. ret = -ENXIO;
  502. goto out;
  503. }
  504. /* Replace the divider value and record the result */
  505. reg_val = __ccu_read(ccu, div->u.s.offset);
  506. reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width,
  507. reg_div);
  508. __ccu_write(ccu, div->u.s.offset, reg_val);
  509. /* If the trigger fails we still want to disable the gate */
  510. if (!__clk_trigger(ccu, trig))
  511. ret = -EIO;
  512. /* Disable the clock again if it was disabled to begin with */
  513. if (!enabled && !__clk_gate(ccu, gate, false))
  514. ret = ret ? ret : -ENXIO; /* return first error */
  515. out:
  516. return ret;
  517. }
  518. /*
  519. * Initialize a divider by committing our desired state to hardware
  520. * without the usual checks to see if it's already set up that way.
  521. * Returns true if successful, false otherwise.
  522. */
  523. static bool div_init(struct ccu_data *ccu, struct bcm_clk_gate *gate,
  524. struct bcm_clk_div *div, struct bcm_clk_trig *trig)
  525. {
  526. if (!divider_exists(div) || divider_is_fixed(div))
  527. return true;
  528. return !__div_commit(ccu, gate, div, trig);
  529. }
  530. static int divider_write(struct ccu_data *ccu, struct bcm_clk_gate *gate,
  531. struct bcm_clk_div *div, struct bcm_clk_trig *trig,
  532. u64 scaled_div)
  533. {
  534. unsigned long flags;
  535. u64 previous;
  536. int ret;
  537. BUG_ON(divider_is_fixed(div));
  538. previous = div->u.s.scaled_div;
  539. if (previous == scaled_div)
  540. return 0; /* No change */
  541. div->u.s.scaled_div = scaled_div;
  542. flags = ccu_lock(ccu);
  543. __ccu_write_enable(ccu);
  544. ret = __div_commit(ccu, gate, div, trig);
  545. __ccu_write_disable(ccu);
  546. ccu_unlock(ccu, flags);
  547. if (ret)
  548. div->u.s.scaled_div = previous; /* Revert the change */
  549. return ret;
  550. }
  551. /* Common clock rate helpers */
  552. /*
  553. * Implement the common clock framework recalc_rate method, taking
  554. * into account a divider and an optional pre-divider. The
  555. * pre-divider register pointer may be NULL.
  556. */
  557. static unsigned long clk_recalc_rate(struct ccu_data *ccu,
  558. struct bcm_clk_div *div, struct bcm_clk_div *pre_div,
  559. unsigned long parent_rate)
  560. {
  561. u64 scaled_parent_rate;
  562. u64 scaled_div;
  563. u64 result;
  564. if (!divider_exists(div))
  565. return parent_rate;
  566. if (parent_rate > (unsigned long)LONG_MAX)
  567. return 0; /* actually this would be a caller bug */
  568. /*
  569. * If there is a pre-divider, divide the scaled parent rate
  570. * by the pre-divider value first. In this case--to improve
  571. * accuracy--scale the parent rate by *both* the pre-divider
  572. * value and the divider before actually computing the
  573. * result of the pre-divider.
  574. *
  575. * If there's only one divider, just scale the parent rate.
  576. */
  577. if (pre_div && divider_exists(pre_div)) {
  578. u64 scaled_rate;
  579. scaled_rate = scale_rate(pre_div, parent_rate);
  580. scaled_rate = scale_rate(div, scaled_rate);
  581. scaled_div = divider_read_scaled(ccu, pre_div);
  582. scaled_parent_rate = DIV_ROUND_CLOSEST_ULL(scaled_rate,
  583. scaled_div);
  584. } else {
  585. scaled_parent_rate = scale_rate(div, parent_rate);
  586. }
  587. /*
  588. * Get the scaled divisor value, and divide the scaled
  589. * parent rate by that to determine this clock's resulting
  590. * rate.
  591. */
  592. scaled_div = divider_read_scaled(ccu, div);
  593. result = DIV_ROUND_CLOSEST_ULL(scaled_parent_rate, scaled_div);
  594. return (unsigned long)result;
  595. }
  596. /*
  597. * Compute the output rate produced when a given parent rate is fed
  598. * into two dividers. The pre-divider can be NULL, and even if it's
  599. * non-null it may be nonexistent. It's also OK for the divider to
  600. * be nonexistent, and in that case the pre-divider is also ignored.
  601. *
  602. * If scaled_div is non-null, it is used to return the scaled divisor
  603. * value used by the (downstream) divider to produce that rate.
  604. */
  605. static long round_rate(struct ccu_data *ccu, struct bcm_clk_div *div,
  606. struct bcm_clk_div *pre_div,
  607. unsigned long rate, unsigned long parent_rate,
  608. u64 *scaled_div)
  609. {
  610. u64 scaled_parent_rate;
  611. u64 min_scaled_div;
  612. u64 max_scaled_div;
  613. u64 best_scaled_div;
  614. u64 result;
  615. BUG_ON(!divider_exists(div));
  616. BUG_ON(!rate);
  617. BUG_ON(parent_rate > (u64)LONG_MAX);
  618. /*
  619. * If there is a pre-divider, divide the scaled parent rate
  620. * by the pre-divider value first. In this case--to improve
  621. * accuracy--scale the parent rate by *both* the pre-divider
  622. * value and the divider before actually computing the
  623. * result of the pre-divider.
  624. *
  625. * If there's only one divider, just scale the parent rate.
  626. *
  627. * For simplicity we treat the pre-divider as fixed (for now).
  628. */
  629. if (divider_exists(pre_div)) {
  630. u64 scaled_rate;
  631. u64 scaled_pre_div;
  632. scaled_rate = scale_rate(pre_div, parent_rate);
  633. scaled_rate = scale_rate(div, scaled_rate);
  634. scaled_pre_div = divider_read_scaled(ccu, pre_div);
  635. scaled_parent_rate = DIV_ROUND_CLOSEST_ULL(scaled_rate,
  636. scaled_pre_div);
  637. } else {
  638. scaled_parent_rate = scale_rate(div, parent_rate);
  639. }
  640. /*
  641. * Compute the best possible divider and ensure it is in
  642. * range. A fixed divider can't be changed, so just report
  643. * the best we can do.
  644. */
  645. if (!divider_is_fixed(div)) {
  646. best_scaled_div = DIV_ROUND_CLOSEST_ULL(scaled_parent_rate,
  647. rate);
  648. min_scaled_div = scaled_div_min(div);
  649. max_scaled_div = scaled_div_max(div);
  650. if (best_scaled_div > max_scaled_div)
  651. best_scaled_div = max_scaled_div;
  652. else if (best_scaled_div < min_scaled_div)
  653. best_scaled_div = min_scaled_div;
  654. } else {
  655. best_scaled_div = divider_read_scaled(ccu, div);
  656. }
  657. /* OK, figure out the resulting rate */
  658. result = DIV_ROUND_CLOSEST_ULL(scaled_parent_rate, best_scaled_div);
  659. if (scaled_div)
  660. *scaled_div = best_scaled_div;
  661. return (long)result;
  662. }
  663. /* Common clock parent helpers */
  664. /*
  665. * For a given parent selector (register field) value, find the
  666. * index into a selector's parent_sel array that contains it.
  667. * Returns the index, or BAD_CLK_INDEX if it's not found.
  668. */
  669. static u8 parent_index(struct bcm_clk_sel *sel, u8 parent_sel)
  670. {
  671. u8 i;
  672. BUG_ON(sel->parent_count > (u32)U8_MAX);
  673. for (i = 0; i < sel->parent_count; i++)
  674. if (sel->parent_sel[i] == parent_sel)
  675. return i;
  676. return BAD_CLK_INDEX;
  677. }
  678. /*
  679. * Fetch the current value of the selector, and translate that into
  680. * its corresponding index in the parent array we registered with
  681. * the clock framework.
  682. *
  683. * Returns parent array index that corresponds with the value found,
  684. * or BAD_CLK_INDEX if the found value is out of range.
  685. */
  686. static u8 selector_read_index(struct ccu_data *ccu, struct bcm_clk_sel *sel)
  687. {
  688. unsigned long flags;
  689. u32 reg_val;
  690. u32 parent_sel;
  691. u8 index;
  692. /* If there's no selector, there's only one parent */
  693. if (!selector_exists(sel))
  694. return 0;
  695. /* Get the value in the selector register */
  696. flags = ccu_lock(ccu);
  697. reg_val = __ccu_read(ccu, sel->offset);
  698. ccu_unlock(ccu, flags);
  699. parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);
  700. /* Look up that selector's parent array index and return it */
  701. index = parent_index(sel, parent_sel);
  702. if (index == BAD_CLK_INDEX)
  703. pr_err("%s: out-of-range parent selector %u (%s 0x%04x)\n",
  704. __func__, parent_sel, ccu->name, sel->offset);
  705. return index;
  706. }
  707. /*
  708. * Commit our desired selector value to the hardware.
  709. *
  710. * Returns 0 on success. Returns -EINVAL for invalid arguments.
  711. * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
  712. */
  713. static int
  714. __sel_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate,
  715. struct bcm_clk_sel *sel, struct bcm_clk_trig *trig)
  716. {
  717. u32 parent_sel;
  718. u32 reg_val;
  719. bool enabled;
  720. int ret = 0;
  721. BUG_ON(!selector_exists(sel));
  722. /*
  723. * If we're just initializing the selector, and no initial
  724. * state was defined in the device tree, we just find out
  725. * what its current value is rather than updating it.
  726. */
  727. if (sel->clk_index == BAD_CLK_INDEX) {
  728. u8 index;
  729. reg_val = __ccu_read(ccu, sel->offset);
  730. parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);
  731. index = parent_index(sel, parent_sel);
  732. if (index == BAD_CLK_INDEX)
  733. return -EINVAL;
  734. sel->clk_index = index;
  735. return 0;
  736. }
  737. BUG_ON((u32)sel->clk_index >= sel->parent_count);
  738. parent_sel = sel->parent_sel[sel->clk_index];
  739. /* Clock needs to be enabled before changing the parent */
  740. enabled = __is_clk_gate_enabled(ccu, gate);
  741. if (!enabled && !__clk_gate(ccu, gate, true))
  742. return -ENXIO;
  743. /* Replace the selector value and record the result */
  744. reg_val = __ccu_read(ccu, sel->offset);
  745. reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel);
  746. __ccu_write(ccu, sel->offset, reg_val);
  747. /* If the trigger fails we still want to disable the gate */
  748. if (!__clk_trigger(ccu, trig))
  749. ret = -EIO;
  750. /* Disable the clock again if it was disabled to begin with */
  751. if (!enabled && !__clk_gate(ccu, gate, false))
  752. ret = ret ? ret : -ENXIO; /* return first error */
  753. return ret;
  754. }
  755. /*
  756. * Initialize a selector by committing our desired state to hardware
  757. * without the usual checks to see if it's already set up that way.
  758. * Returns true if successful, false otherwise.
  759. */
  760. static bool sel_init(struct ccu_data *ccu, struct bcm_clk_gate *gate,
  761. struct bcm_clk_sel *sel, struct bcm_clk_trig *trig)
  762. {
  763. if (!selector_exists(sel))
  764. return true;
  765. return !__sel_commit(ccu, gate, sel, trig);
  766. }
  767. /*
  768. * Write a new value into a selector register to switch to a
  769. * different parent clock. Returns 0 on success, or an error code
  770. * (from __sel_commit()) otherwise.
  771. */
  772. static int selector_write(struct ccu_data *ccu, struct bcm_clk_gate *gate,
  773. struct bcm_clk_sel *sel, struct bcm_clk_trig *trig,
  774. u8 index)
  775. {
  776. unsigned long flags;
  777. u8 previous;
  778. int ret;
  779. previous = sel->clk_index;
  780. if (previous == index)
  781. return 0; /* No change */
  782. sel->clk_index = index;
  783. flags = ccu_lock(ccu);
  784. __ccu_write_enable(ccu);
  785. ret = __sel_commit(ccu, gate, sel, trig);
  786. __ccu_write_disable(ccu);
  787. ccu_unlock(ccu, flags);
  788. if (ret)
  789. sel->clk_index = previous; /* Revert the change */
  790. return ret;
  791. }
  792. /* Clock operations */
  793. static int kona_peri_clk_enable(struct clk_hw *hw)
  794. {
  795. struct kona_clk *bcm_clk = to_kona_clk(hw);
  796. struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
  797. return clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, true);
  798. }
  799. static void kona_peri_clk_disable(struct clk_hw *hw)
  800. {
  801. struct kona_clk *bcm_clk = to_kona_clk(hw);
  802. struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
  803. (void)clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, false);
  804. }
  805. static int kona_peri_clk_is_enabled(struct clk_hw *hw)
  806. {
  807. struct kona_clk *bcm_clk = to_kona_clk(hw);
  808. struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
  809. return is_clk_gate_enabled(bcm_clk->ccu, gate) ? 1 : 0;
  810. }
  811. static unsigned long kona_peri_clk_recalc_rate(struct clk_hw *hw,
  812. unsigned long parent_rate)
  813. {
  814. struct kona_clk *bcm_clk = to_kona_clk(hw);
  815. struct peri_clk_data *data = bcm_clk->u.peri;
  816. return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div,
  817. parent_rate);
  818. }
  819. static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  820. unsigned long *parent_rate)
  821. {
  822. struct kona_clk *bcm_clk = to_kona_clk(hw);
  823. struct bcm_clk_div *div = &bcm_clk->u.peri->div;
  824. if (!divider_exists(div))
  825. return clk_hw_get_rate(hw);
  826. /* Quietly avoid a zero rate */
  827. return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div,
  828. rate ? rate : 1, *parent_rate, NULL);
  829. }
  830. static int kona_peri_clk_determine_rate(struct clk_hw *hw,
  831. struct clk_rate_request *req)
  832. {
  833. struct kona_clk *bcm_clk = to_kona_clk(hw);
  834. struct clk_hw *current_parent;
  835. unsigned long parent_rate;
  836. unsigned long best_delta;
  837. unsigned long best_rate;
  838. u32 parent_count;
  839. long rate;
  840. u32 which;
  841. /*
  842. * If there is no other parent to choose, use the current one.
  843. * Note: We don't honor (or use) CLK_SET_RATE_NO_REPARENT.
  844. */
  845. WARN_ON_ONCE(bcm_clk->init_data.flags & CLK_SET_RATE_NO_REPARENT);
  846. parent_count = (u32)bcm_clk->init_data.num_parents;
  847. if (parent_count < 2) {
  848. rate = kona_peri_clk_round_rate(hw, req->rate,
  849. &req->best_parent_rate);
  850. if (rate < 0)
  851. return rate;
  852. req->rate = rate;
  853. return 0;
  854. }
  855. /* Unless we can do better, stick with current parent */
  856. current_parent = clk_hw_get_parent(hw);
  857. parent_rate = clk_hw_get_rate(current_parent);
  858. best_rate = kona_peri_clk_round_rate(hw, req->rate, &parent_rate);
  859. best_delta = abs(best_rate - req->rate);
  860. /* Check whether any other parent clock can produce a better result */
  861. for (which = 0; which < parent_count; which++) {
  862. struct clk_hw *parent = clk_hw_get_parent_by_index(hw, which);
  863. unsigned long delta;
  864. unsigned long other_rate;
  865. BUG_ON(!parent);
  866. if (parent == current_parent)
  867. continue;
  868. /* We don't support CLK_SET_RATE_PARENT */
  869. parent_rate = clk_hw_get_rate(parent);
  870. other_rate = kona_peri_clk_round_rate(hw, req->rate,
  871. &parent_rate);
  872. delta = abs(other_rate - req->rate);
  873. if (delta < best_delta) {
  874. best_delta = delta;
  875. best_rate = other_rate;
  876. req->best_parent_hw = parent;
  877. req->best_parent_rate = parent_rate;
  878. }
  879. }
  880. req->rate = best_rate;
  881. return 0;
  882. }
  883. static int kona_peri_clk_set_parent(struct clk_hw *hw, u8 index)
  884. {
  885. struct kona_clk *bcm_clk = to_kona_clk(hw);
  886. struct peri_clk_data *data = bcm_clk->u.peri;
  887. struct bcm_clk_sel *sel = &data->sel;
  888. struct bcm_clk_trig *trig;
  889. int ret;
  890. BUG_ON(index >= sel->parent_count);
  891. /* If there's only one parent we don't require a selector */
  892. if (!selector_exists(sel))
  893. return 0;
  894. /*
  895. * The regular trigger is used by default, but if there's a
  896. * pre-trigger we want to use that instead.
  897. */
  898. trig = trigger_exists(&data->pre_trig) ? &data->pre_trig
  899. : &data->trig;
  900. ret = selector_write(bcm_clk->ccu, &data->gate, sel, trig, index);
  901. if (ret == -ENXIO) {
  902. pr_err("%s: gating failure for %s\n", __func__,
  903. bcm_clk->init_data.name);
  904. ret = -EIO; /* Don't proliferate weird errors */
  905. } else if (ret == -EIO) {
  906. pr_err("%s: %strigger failed for %s\n", __func__,
  907. trig == &data->pre_trig ? "pre-" : "",
  908. bcm_clk->init_data.name);
  909. }
  910. return ret;
  911. }
  912. static u8 kona_peri_clk_get_parent(struct clk_hw *hw)
  913. {
  914. struct kona_clk *bcm_clk = to_kona_clk(hw);
  915. struct peri_clk_data *data = bcm_clk->u.peri;
  916. u8 index;
  917. index = selector_read_index(bcm_clk->ccu, &data->sel);
  918. /* Not all callers would handle an out-of-range value gracefully */
  919. return index == BAD_CLK_INDEX ? 0 : index;
  920. }
  921. static int kona_peri_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  922. unsigned long parent_rate)
  923. {
  924. struct kona_clk *bcm_clk = to_kona_clk(hw);
  925. struct peri_clk_data *data = bcm_clk->u.peri;
  926. struct bcm_clk_div *div = &data->div;
  927. u64 scaled_div = 0;
  928. int ret;
  929. if (parent_rate > (unsigned long)LONG_MAX)
  930. return -EINVAL;
  931. if (rate == clk_hw_get_rate(hw))
  932. return 0;
  933. if (!divider_exists(div))
  934. return rate == parent_rate ? 0 : -EINVAL;
  935. /*
  936. * A fixed divider can't be changed. (Nor can a fixed
  937. * pre-divider be, but for now we never actually try to
  938. * change that.) Tolerate a request for a no-op change.
  939. */
  940. if (divider_is_fixed(&data->div))
  941. return rate == parent_rate ? 0 : -EINVAL;
  942. /*
  943. * Get the scaled divisor value needed to achieve a clock
  944. * rate as close as possible to what was requested, given
  945. * the parent clock rate supplied.
  946. */
  947. (void)round_rate(bcm_clk->ccu, div, &data->pre_div,
  948. rate ? rate : 1, parent_rate, &scaled_div);
  949. /*
  950. * We aren't updating any pre-divider at this point, so
  951. * we'll use the regular trigger.
  952. */
  953. ret = divider_write(bcm_clk->ccu, &data->gate, &data->div,
  954. &data->trig, scaled_div);
  955. if (ret == -ENXIO) {
  956. pr_err("%s: gating failure for %s\n", __func__,
  957. bcm_clk->init_data.name);
  958. ret = -EIO; /* Don't proliferate weird errors */
  959. } else if (ret == -EIO) {
  960. pr_err("%s: trigger failed for %s\n", __func__,
  961. bcm_clk->init_data.name);
  962. }
  963. return ret;
  964. }
  965. struct clk_ops kona_peri_clk_ops = {
  966. .enable = kona_peri_clk_enable,
  967. .disable = kona_peri_clk_disable,
  968. .is_enabled = kona_peri_clk_is_enabled,
  969. .recalc_rate = kona_peri_clk_recalc_rate,
  970. .determine_rate = kona_peri_clk_determine_rate,
  971. .set_parent = kona_peri_clk_set_parent,
  972. .get_parent = kona_peri_clk_get_parent,
  973. .set_rate = kona_peri_clk_set_rate,
  974. };
  975. /* Put a peripheral clock into its initial state */
  976. static bool __peri_clk_init(struct kona_clk *bcm_clk)
  977. {
  978. struct ccu_data *ccu = bcm_clk->ccu;
  979. struct peri_clk_data *peri = bcm_clk->u.peri;
  980. const char *name = bcm_clk->init_data.name;
  981. struct bcm_clk_trig *trig;
  982. BUG_ON(bcm_clk->type != bcm_clk_peri);
  983. if (!policy_init(ccu, &peri->policy)) {
  984. pr_err("%s: error initializing policy for %s\n",
  985. __func__, name);
  986. return false;
  987. }
  988. if (!gate_init(ccu, &peri->gate)) {
  989. pr_err("%s: error initializing gate for %s\n", __func__, name);
  990. return false;
  991. }
  992. if (!hyst_init(ccu, &peri->hyst)) {
  993. pr_err("%s: error initializing hyst for %s\n", __func__, name);
  994. return false;
  995. }
  996. if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) {
  997. pr_err("%s: error initializing divider for %s\n", __func__,
  998. name);
  999. return false;
  1000. }
  1001. /*
  1002. * For the pre-divider and selector, the pre-trigger is used
  1003. * if it's present, otherwise we just use the regular trigger.
  1004. */
  1005. trig = trigger_exists(&peri->pre_trig) ? &peri->pre_trig
  1006. : &peri->trig;
  1007. if (!div_init(ccu, &peri->gate, &peri->pre_div, trig)) {
  1008. pr_err("%s: error initializing pre-divider for %s\n", __func__,
  1009. name);
  1010. return false;
  1011. }
  1012. if (!sel_init(ccu, &peri->gate, &peri->sel, trig)) {
  1013. pr_err("%s: error initializing selector for %s\n", __func__,
  1014. name);
  1015. return false;
  1016. }
  1017. return true;
  1018. }
  1019. static bool __kona_clk_init(struct kona_clk *bcm_clk)
  1020. {
  1021. switch (bcm_clk->type) {
  1022. case bcm_clk_peri:
  1023. return __peri_clk_init(bcm_clk);
  1024. default:
  1025. BUG();
  1026. }
  1027. return false;
  1028. }
  1029. /* Set a CCU and all its clocks into their desired initial state */
  1030. bool __init kona_ccu_init(struct ccu_data *ccu)
  1031. {
  1032. unsigned long flags;
  1033. unsigned int which;
  1034. struct kona_clk *kona_clks = ccu->kona_clks;
  1035. bool success = true;
  1036. flags = ccu_lock(ccu);
  1037. __ccu_write_enable(ccu);
  1038. for (which = 0; which < ccu->clk_num; which++) {
  1039. struct kona_clk *bcm_clk = &kona_clks[which];
  1040. if (!bcm_clk->ccu)
  1041. continue;
  1042. success &= __kona_clk_init(bcm_clk);
  1043. }
  1044. __ccu_write_disable(ccu);
  1045. ccu_unlock(ccu, flags);
  1046. return success;
  1047. }