at91sam9g45.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/clk-provider.h>
  3. #include <linux/mfd/syscon.h>
  4. #include <linux/slab.h>
  5. #include <dt-bindings/clock/at91.h>
  6. #include "pmc.h"
  7. static DEFINE_SPINLOCK(at91sam9g45_mck_lock);
  8. static const struct clk_master_characteristics mck_characteristics = {
  9. .output = { .min = 0, .max = 133333333 },
  10. .divisors = { 1, 2, 4, 3 },
  11. };
  12. static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
  13. static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
  14. static const struct clk_range plla_outputs[] = {
  15. { .min = 745000000, .max = 800000000 },
  16. { .min = 695000000, .max = 750000000 },
  17. { .min = 645000000, .max = 700000000 },
  18. { .min = 595000000, .max = 650000000 },
  19. { .min = 545000000, .max = 600000000 },
  20. { .min = 495000000, .max = 555000000 },
  21. { .min = 445000000, .max = 500000000 },
  22. { .min = 400000000, .max = 450000000 },
  23. };
  24. static const struct clk_pll_characteristics plla_characteristics = {
  25. .input = { .min = 2000000, .max = 32000000 },
  26. .num_output = ARRAY_SIZE(plla_outputs),
  27. .output = plla_outputs,
  28. .icpll = plla_icpll,
  29. .out = plla_out,
  30. };
  31. static const struct {
  32. char *n;
  33. char *p;
  34. u8 id;
  35. } at91sam9g45_systemck[] = {
  36. { .n = "ddrck", .p = "masterck_div", .id = 2 },
  37. { .n = "uhpck", .p = "usbck", .id = 6 },
  38. { .n = "pck0", .p = "prog0", .id = 8 },
  39. { .n = "pck1", .p = "prog1", .id = 9 },
  40. };
  41. struct pck {
  42. char *n;
  43. u8 id;
  44. };
  45. static const struct pck at91sam9g45_periphck[] = {
  46. { .n = "pioA_clk", .id = 2, },
  47. { .n = "pioB_clk", .id = 3, },
  48. { .n = "pioC_clk", .id = 4, },
  49. { .n = "pioDE_clk", .id = 5, },
  50. { .n = "trng_clk", .id = 6, },
  51. { .n = "usart0_clk", .id = 7, },
  52. { .n = "usart1_clk", .id = 8, },
  53. { .n = "usart2_clk", .id = 9, },
  54. { .n = "usart3_clk", .id = 10, },
  55. { .n = "mci0_clk", .id = 11, },
  56. { .n = "twi0_clk", .id = 12, },
  57. { .n = "twi1_clk", .id = 13, },
  58. { .n = "spi0_clk", .id = 14, },
  59. { .n = "spi1_clk", .id = 15, },
  60. { .n = "ssc0_clk", .id = 16, },
  61. { .n = "ssc1_clk", .id = 17, },
  62. { .n = "tcb0_clk", .id = 18, },
  63. { .n = "pwm_clk", .id = 19, },
  64. { .n = "adc_clk", .id = 20, },
  65. { .n = "dma0_clk", .id = 21, },
  66. { .n = "uhphs_clk", .id = 22, },
  67. { .n = "lcd_clk", .id = 23, },
  68. { .n = "ac97_clk", .id = 24, },
  69. { .n = "macb0_clk", .id = 25, },
  70. { .n = "isi_clk", .id = 26, },
  71. { .n = "udphs_clk", .id = 27, },
  72. { .n = "aestdessha_clk", .id = 28, },
  73. { .n = "mci1_clk", .id = 29, },
  74. { .n = "vdec_clk", .id = 30, },
  75. };
  76. static void __init at91sam9g45_pmc_setup(struct device_node *np)
  77. {
  78. const char *slck_name, *mainxtal_name;
  79. struct pmc_data *at91sam9g45_pmc;
  80. const char *parent_names[6];
  81. struct regmap *regmap;
  82. struct clk_hw *hw;
  83. int i;
  84. bool bypass;
  85. i = of_property_match_string(np, "clock-names", "slow_clk");
  86. if (i < 0)
  87. return;
  88. slck_name = of_clk_get_parent_name(np, i);
  89. i = of_property_match_string(np, "clock-names", "main_xtal");
  90. if (i < 0)
  91. return;
  92. mainxtal_name = of_clk_get_parent_name(np, i);
  93. regmap = device_node_to_regmap(np);
  94. if (IS_ERR(regmap))
  95. return;
  96. at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1,
  97. nck(at91sam9g45_systemck),
  98. nck(at91sam9g45_periphck), 0, 2);
  99. if (!at91sam9g45_pmc)
  100. return;
  101. bypass = of_property_read_bool(np, "atmel,osc-bypass");
  102. hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
  103. bypass);
  104. if (IS_ERR(hw))
  105. goto err_free;
  106. hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
  107. if (IS_ERR(hw))
  108. goto err_free;
  109. at91sam9g45_pmc->chws[PMC_MAIN] = hw;
  110. hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
  111. &at91rm9200_pll_layout, &plla_characteristics);
  112. if (IS_ERR(hw))
  113. goto err_free;
  114. hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
  115. if (IS_ERR(hw))
  116. goto err_free;
  117. at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
  118. hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
  119. if (IS_ERR(hw))
  120. goto err_free;
  121. at91sam9g45_pmc->chws[PMC_UTMI] = hw;
  122. parent_names[0] = slck_name;
  123. parent_names[1] = "mainck";
  124. parent_names[2] = "plladivck";
  125. parent_names[3] = "utmick";
  126. hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
  127. parent_names,
  128. &at91rm9200_master_layout,
  129. &mck_characteristics,
  130. &at91sam9g45_mck_lock);
  131. if (IS_ERR(hw))
  132. goto err_free;
  133. hw = at91_clk_register_master_div(regmap, "masterck_div",
  134. "masterck_pres",
  135. &at91rm9200_master_layout,
  136. &mck_characteristics,
  137. &at91sam9g45_mck_lock,
  138. CLK_SET_RATE_GATE, 0);
  139. if (IS_ERR(hw))
  140. goto err_free;
  141. at91sam9g45_pmc->chws[PMC_MCK] = hw;
  142. parent_names[0] = "plladivck";
  143. parent_names[1] = "utmick";
  144. hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
  145. if (IS_ERR(hw))
  146. goto err_free;
  147. parent_names[0] = slck_name;
  148. parent_names[1] = "mainck";
  149. parent_names[2] = "plladivck";
  150. parent_names[3] = "utmick";
  151. parent_names[4] = "masterck_div";
  152. for (i = 0; i < 2; i++) {
  153. char name[6];
  154. snprintf(name, sizeof(name), "prog%d", i);
  155. hw = at91_clk_register_programmable(regmap, name,
  156. parent_names, 5, i,
  157. &at91sam9g45_programmable_layout,
  158. NULL);
  159. if (IS_ERR(hw))
  160. goto err_free;
  161. at91sam9g45_pmc->pchws[i] = hw;
  162. }
  163. for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
  164. hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
  165. at91sam9g45_systemck[i].p,
  166. at91sam9g45_systemck[i].id);
  167. if (IS_ERR(hw))
  168. goto err_free;
  169. at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw;
  170. }
  171. for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
  172. hw = at91_clk_register_peripheral(regmap,
  173. at91sam9g45_periphck[i].n,
  174. "masterck_div",
  175. at91sam9g45_periphck[i].id);
  176. if (IS_ERR(hw))
  177. goto err_free;
  178. at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw;
  179. }
  180. of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc);
  181. return;
  182. err_free:
  183. kfree(at91sam9g45_pmc);
  184. }
  185. /*
  186. * The TCB is used as the clocksource so its clock is needed early. This means
  187. * this can't be a platform driver.
  188. */
  189. CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);