cctrng.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
  3. #include <linux/kernel.h>
  4. #include <linux/module.h>
  5. #include <linux/clk.h>
  6. #include <linux/hw_random.h>
  7. #include <linux/io.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm_runtime.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/irqreturn.h>
  12. #include <linux/workqueue.h>
  13. #include <linux/circ_buf.h>
  14. #include <linux/completion.h>
  15. #include <linux/of.h>
  16. #include <linux/bitfield.h>
  17. #include <linux/fips.h>
  18. #include "cctrng.h"
  19. #define CC_REG_LOW(name) (name ## _BIT_SHIFT)
  20. #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
  21. #define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
  22. #define CC_REG_FLD_GET(reg_name, fld_name, reg_val) \
  23. (FIELD_GET(CC_GENMASK(CC_ ## reg_name ## _ ## fld_name), reg_val))
  24. #define CC_HW_RESET_LOOP_COUNT 10
  25. #define CC_TRNG_SUSPEND_TIMEOUT 3000
  26. /* data circular buffer in words must be:
  27. * - of a power-of-2 size (limitation of circ_buf.h macros)
  28. * - at least 6, the size generated in the EHR according to HW implementation
  29. */
  30. #define CCTRNG_DATA_BUF_WORDS 32
  31. /* The timeout for the TRNG operation should be calculated with the formula:
  32. * Timeout = EHR_NUM * VN_COEFF * EHR_LENGTH * SAMPLE_CNT * SCALE_VALUE
  33. * while:
  34. * - SAMPLE_CNT is input value from the characterisation process
  35. * - all the rest are constants
  36. */
  37. #define EHR_NUM 1
  38. #define VN_COEFF 4
  39. #define EHR_LENGTH CC_TRNG_EHR_IN_BITS
  40. #define SCALE_VALUE 2
  41. #define CCTRNG_TIMEOUT(smpl_cnt) \
  42. (EHR_NUM * VN_COEFF * EHR_LENGTH * smpl_cnt * SCALE_VALUE)
  43. struct cctrng_drvdata {
  44. struct platform_device *pdev;
  45. void __iomem *cc_base;
  46. struct clk *clk;
  47. struct hwrng rng;
  48. u32 active_rosc;
  49. /* Sampling interval for each ring oscillator:
  50. * count of ring oscillator cycles between consecutive bits sampling.
  51. * Value of 0 indicates non-valid rosc
  52. */
  53. u32 smpl_ratio[CC_TRNG_NUM_OF_ROSCS];
  54. u32 data_buf[CCTRNG_DATA_BUF_WORDS];
  55. struct circ_buf circ;
  56. struct work_struct compwork;
  57. struct work_struct startwork;
  58. /* pending_hw - 1 when HW is pending, 0 when it is idle */
  59. atomic_t pending_hw;
  60. /* protects against multiple concurrent consumers of data_buf */
  61. spinlock_t read_lock;
  62. };
  63. /* functions for write/read CC registers */
  64. static inline void cc_iowrite(struct cctrng_drvdata *drvdata, u32 reg, u32 val)
  65. {
  66. iowrite32(val, (drvdata->cc_base + reg));
  67. }
  68. static inline u32 cc_ioread(struct cctrng_drvdata *drvdata, u32 reg)
  69. {
  70. return ioread32(drvdata->cc_base + reg);
  71. }
  72. static int cc_trng_pm_get(struct device *dev)
  73. {
  74. int rc = 0;
  75. rc = pm_runtime_get_sync(dev);
  76. /* pm_runtime_get_sync() can return 1 as a valid return code */
  77. return (rc == 1 ? 0 : rc);
  78. }
  79. static void cc_trng_pm_put_suspend(struct device *dev)
  80. {
  81. int rc = 0;
  82. pm_runtime_mark_last_busy(dev);
  83. rc = pm_runtime_put_autosuspend(dev);
  84. if (rc)
  85. dev_err(dev, "pm_runtime_put_autosuspend returned %x\n", rc);
  86. }
  87. static int cc_trng_pm_init(struct cctrng_drvdata *drvdata)
  88. {
  89. struct device *dev = &(drvdata->pdev->dev);
  90. /* must be before the enabling to avoid redundant suspending */
  91. pm_runtime_set_autosuspend_delay(dev, CC_TRNG_SUSPEND_TIMEOUT);
  92. pm_runtime_use_autosuspend(dev);
  93. /* set us as active - note we won't do PM ops until cc_trng_pm_go()! */
  94. return pm_runtime_set_active(dev);
  95. }
  96. static void cc_trng_pm_go(struct cctrng_drvdata *drvdata)
  97. {
  98. struct device *dev = &(drvdata->pdev->dev);
  99. /* enable the PM module*/
  100. pm_runtime_enable(dev);
  101. }
  102. static void cc_trng_pm_fini(struct cctrng_drvdata *drvdata)
  103. {
  104. struct device *dev = &(drvdata->pdev->dev);
  105. pm_runtime_disable(dev);
  106. }
  107. static inline int cc_trng_parse_sampling_ratio(struct cctrng_drvdata *drvdata)
  108. {
  109. struct device *dev = &(drvdata->pdev->dev);
  110. struct device_node *np = drvdata->pdev->dev.of_node;
  111. int rc;
  112. int i;
  113. /* ret will be set to 0 if at least one rosc has (sampling ratio > 0) */
  114. int ret = -EINVAL;
  115. rc = of_property_read_u32_array(np, "arm,rosc-ratio",
  116. drvdata->smpl_ratio,
  117. CC_TRNG_NUM_OF_ROSCS);
  118. if (rc) {
  119. /* arm,rosc-ratio was not found in device tree */
  120. return rc;
  121. }
  122. /* verify that at least one rosc has (sampling ratio > 0) */
  123. for (i = 0; i < CC_TRNG_NUM_OF_ROSCS; ++i) {
  124. dev_dbg(dev, "rosc %d sampling ratio %u",
  125. i, drvdata->smpl_ratio[i]);
  126. if (drvdata->smpl_ratio[i] > 0)
  127. ret = 0;
  128. }
  129. return ret;
  130. }
  131. static int cc_trng_change_rosc(struct cctrng_drvdata *drvdata)
  132. {
  133. struct device *dev = &(drvdata->pdev->dev);
  134. dev_dbg(dev, "cctrng change rosc (was %d)\n", drvdata->active_rosc);
  135. drvdata->active_rosc += 1;
  136. while (drvdata->active_rosc < CC_TRNG_NUM_OF_ROSCS) {
  137. if (drvdata->smpl_ratio[drvdata->active_rosc] > 0)
  138. return 0;
  139. drvdata->active_rosc += 1;
  140. }
  141. return -EINVAL;
  142. }
  143. static void cc_trng_enable_rnd_source(struct cctrng_drvdata *drvdata)
  144. {
  145. u32 max_cycles;
  146. /* Set watchdog threshold to maximal allowed time (in CPU cycles) */
  147. max_cycles = CCTRNG_TIMEOUT(drvdata->smpl_ratio[drvdata->active_rosc]);
  148. cc_iowrite(drvdata, CC_RNG_WATCHDOG_VAL_REG_OFFSET, max_cycles);
  149. /* enable the RND source */
  150. cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0x1);
  151. /* unmask RNG interrupts */
  152. cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, (u32)~CC_RNG_INT_MASK);
  153. }
  154. /* increase circular data buffer index (head/tail) */
  155. static inline void circ_idx_inc(int *idx, int bytes)
  156. {
  157. *idx += (bytes + 3) >> 2;
  158. *idx &= (CCTRNG_DATA_BUF_WORDS - 1);
  159. }
  160. static inline size_t circ_buf_space(struct cctrng_drvdata *drvdata)
  161. {
  162. return CIRC_SPACE(drvdata->circ.head,
  163. drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
  164. }
  165. static int cctrng_read(struct hwrng *rng, void *data, size_t max, bool wait)
  166. {
  167. /* current implementation ignores "wait" */
  168. struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)rng->priv;
  169. struct device *dev = &(drvdata->pdev->dev);
  170. u32 *buf = (u32 *)drvdata->circ.buf;
  171. size_t copied = 0;
  172. size_t cnt_w;
  173. size_t size;
  174. size_t left;
  175. if (!spin_trylock(&drvdata->read_lock)) {
  176. /* concurrent consumers from data_buf cannot be served */
  177. dev_dbg_ratelimited(dev, "unable to hold lock\n");
  178. return 0;
  179. }
  180. /* copy till end of data buffer (without wrap back) */
  181. cnt_w = CIRC_CNT_TO_END(drvdata->circ.head,
  182. drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
  183. size = min((cnt_w<<2), max);
  184. memcpy(data, &(buf[drvdata->circ.tail]), size);
  185. copied = size;
  186. circ_idx_inc(&drvdata->circ.tail, size);
  187. /* copy rest of data in data buffer */
  188. left = max - copied;
  189. if (left > 0) {
  190. cnt_w = CIRC_CNT(drvdata->circ.head,
  191. drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
  192. size = min((cnt_w<<2), left);
  193. memcpy(data, &(buf[drvdata->circ.tail]), size);
  194. copied += size;
  195. circ_idx_inc(&drvdata->circ.tail, size);
  196. }
  197. spin_unlock(&drvdata->read_lock);
  198. if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
  199. if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
  200. /* re-check space in buffer to avoid potential race */
  201. if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
  202. /* increment device's usage counter */
  203. int rc = cc_trng_pm_get(dev);
  204. if (rc) {
  205. dev_err(dev,
  206. "cc_trng_pm_get returned %x\n",
  207. rc);
  208. return rc;
  209. }
  210. /* schedule execution of deferred work handler
  211. * for filling of data buffer
  212. */
  213. schedule_work(&drvdata->startwork);
  214. } else {
  215. atomic_set(&drvdata->pending_hw, 0);
  216. }
  217. }
  218. }
  219. return copied;
  220. }
  221. static void cc_trng_hw_trigger(struct cctrng_drvdata *drvdata)
  222. {
  223. u32 tmp_smpl_cnt = 0;
  224. struct device *dev = &(drvdata->pdev->dev);
  225. dev_dbg(dev, "cctrng hw trigger.\n");
  226. /* enable the HW RND clock */
  227. cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
  228. /* do software reset */
  229. cc_iowrite(drvdata, CC_RNG_SW_RESET_REG_OFFSET, 0x1);
  230. /* in order to verify that the reset has completed,
  231. * the sample count need to be verified
  232. */
  233. do {
  234. /* enable the HW RND clock */
  235. cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
  236. /* set sampling ratio (rng_clocks) between consecutive bits */
  237. cc_iowrite(drvdata, CC_SAMPLE_CNT1_REG_OFFSET,
  238. drvdata->smpl_ratio[drvdata->active_rosc]);
  239. /* read the sampling ratio */
  240. tmp_smpl_cnt = cc_ioread(drvdata, CC_SAMPLE_CNT1_REG_OFFSET);
  241. } while (tmp_smpl_cnt != drvdata->smpl_ratio[drvdata->active_rosc]);
  242. /* disable the RND source for setting new parameters in HW */
  243. cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
  244. cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, 0xFFFFFFFF);
  245. cc_iowrite(drvdata, CC_TRNG_CONFIG_REG_OFFSET, drvdata->active_rosc);
  246. /* Debug Control register: set to 0 - no bypasses */
  247. cc_iowrite(drvdata, CC_TRNG_DEBUG_CONTROL_REG_OFFSET, 0);
  248. cc_trng_enable_rnd_source(drvdata);
  249. }
  250. static void cc_trng_compwork_handler(struct work_struct *w)
  251. {
  252. u32 isr = 0;
  253. u32 ehr_valid = 0;
  254. struct cctrng_drvdata *drvdata =
  255. container_of(w, struct cctrng_drvdata, compwork);
  256. struct device *dev = &(drvdata->pdev->dev);
  257. int i;
  258. /* stop DMA and the RNG source */
  259. cc_iowrite(drvdata, CC_RNG_DMA_ENABLE_REG_OFFSET, 0);
  260. cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
  261. /* read RNG_ISR and check for errors */
  262. isr = cc_ioread(drvdata, CC_RNG_ISR_REG_OFFSET);
  263. ehr_valid = CC_REG_FLD_GET(RNG_ISR, EHR_VALID, isr);
  264. dev_dbg(dev, "Got RNG_ISR=0x%08X (EHR_VALID=%u)\n", isr, ehr_valid);
  265. if (fips_enabled && CC_REG_FLD_GET(RNG_ISR, CRNGT_ERR, isr)) {
  266. fips_fail_notify();
  267. /* FIPS error is fatal */
  268. panic("Got HW CRNGT error while fips is enabled!\n");
  269. }
  270. /* Clear all pending RNG interrupts */
  271. cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, isr);
  272. if (!ehr_valid) {
  273. /* in case of AUTOCORR/TIMEOUT error, try the next ROSC */
  274. if (CC_REG_FLD_GET(RNG_ISR, AUTOCORR_ERR, isr) ||
  275. CC_REG_FLD_GET(RNG_ISR, WATCHDOG, isr)) {
  276. dev_dbg(dev, "cctrng autocorr/timeout error.\n");
  277. goto next_rosc;
  278. }
  279. /* in case of VN error, ignore it */
  280. }
  281. /* read EHR data from registers */
  282. for (i = 0; i < CC_TRNG_EHR_IN_WORDS; i++) {
  283. /* calc word ptr in data_buf */
  284. u32 *buf = (u32 *)drvdata->circ.buf;
  285. buf[drvdata->circ.head] = cc_ioread(drvdata,
  286. CC_EHR_DATA_0_REG_OFFSET + (i*sizeof(u32)));
  287. /* EHR_DATA registers are cleared on read. In case 0 value was
  288. * returned, restart the entropy collection.
  289. */
  290. if (buf[drvdata->circ.head] == 0) {
  291. dev_dbg(dev, "Got 0 value in EHR. active_rosc %u\n",
  292. drvdata->active_rosc);
  293. goto next_rosc;
  294. }
  295. circ_idx_inc(&drvdata->circ.head, 1<<2);
  296. }
  297. atomic_set(&drvdata->pending_hw, 0);
  298. /* continue to fill data buffer if needed */
  299. if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
  300. if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
  301. /* Re-enable rnd source */
  302. cc_trng_enable_rnd_source(drvdata);
  303. return;
  304. }
  305. }
  306. cc_trng_pm_put_suspend(dev);
  307. dev_dbg(dev, "compwork handler done\n");
  308. return;
  309. next_rosc:
  310. if ((circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) &&
  311. (cc_trng_change_rosc(drvdata) == 0)) {
  312. /* trigger trng hw with next rosc */
  313. cc_trng_hw_trigger(drvdata);
  314. } else {
  315. atomic_set(&drvdata->pending_hw, 0);
  316. cc_trng_pm_put_suspend(dev);
  317. }
  318. }
  319. static irqreturn_t cc_isr(int irq, void *dev_id)
  320. {
  321. struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)dev_id;
  322. struct device *dev = &(drvdata->pdev->dev);
  323. u32 irr;
  324. /* if driver suspended return, probably shared interrupt */
  325. if (pm_runtime_suspended(dev))
  326. return IRQ_NONE;
  327. /* read the interrupt status */
  328. irr = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
  329. dev_dbg(dev, "Got IRR=0x%08X\n", irr);
  330. if (irr == 0) /* Probably shared interrupt line */
  331. return IRQ_NONE;
  332. /* clear interrupt - must be before processing events */
  333. cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, irr);
  334. /* RNG interrupt - most probable */
  335. if (irr & CC_HOST_RNG_IRQ_MASK) {
  336. /* Mask RNG interrupts - will be unmasked in deferred work */
  337. cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, 0xFFFFFFFF);
  338. /* We clear RNG interrupt here,
  339. * to avoid it from firing as we'll unmask RNG interrupts.
  340. */
  341. cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET,
  342. CC_HOST_RNG_IRQ_MASK);
  343. irr &= ~CC_HOST_RNG_IRQ_MASK;
  344. /* schedule execution of deferred work handler */
  345. schedule_work(&drvdata->compwork);
  346. }
  347. if (irr) {
  348. dev_dbg_ratelimited(dev,
  349. "IRR includes unknown cause bits (0x%08X)\n",
  350. irr);
  351. /* Just warning */
  352. }
  353. return IRQ_HANDLED;
  354. }
  355. static void cc_trng_startwork_handler(struct work_struct *w)
  356. {
  357. struct cctrng_drvdata *drvdata =
  358. container_of(w, struct cctrng_drvdata, startwork);
  359. drvdata->active_rosc = 0;
  360. cc_trng_hw_trigger(drvdata);
  361. }
  362. static int cc_trng_clk_init(struct cctrng_drvdata *drvdata)
  363. {
  364. struct clk *clk;
  365. struct device *dev = &(drvdata->pdev->dev);
  366. int rc = 0;
  367. clk = devm_clk_get_optional(dev, NULL);
  368. if (IS_ERR(clk))
  369. return dev_err_probe(dev, PTR_ERR(clk),
  370. "Error getting clock\n");
  371. drvdata->clk = clk;
  372. rc = clk_prepare_enable(drvdata->clk);
  373. if (rc) {
  374. dev_err(dev, "Failed to enable clock\n");
  375. return rc;
  376. }
  377. return 0;
  378. }
  379. static void cc_trng_clk_fini(struct cctrng_drvdata *drvdata)
  380. {
  381. clk_disable_unprepare(drvdata->clk);
  382. }
  383. static int cctrng_probe(struct platform_device *pdev)
  384. {
  385. struct cctrng_drvdata *drvdata;
  386. struct device *dev = &pdev->dev;
  387. int rc = 0;
  388. u32 val;
  389. int irq;
  390. drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
  391. if (!drvdata)
  392. return -ENOMEM;
  393. drvdata->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
  394. if (!drvdata->rng.name)
  395. return -ENOMEM;
  396. drvdata->rng.read = cctrng_read;
  397. drvdata->rng.priv = (unsigned long)drvdata;
  398. drvdata->rng.quality = CC_TRNG_QUALITY;
  399. platform_set_drvdata(pdev, drvdata);
  400. drvdata->pdev = pdev;
  401. drvdata->circ.buf = (char *)drvdata->data_buf;
  402. drvdata->cc_base = devm_platform_ioremap_resource(pdev, 0);
  403. if (IS_ERR(drvdata->cc_base)) {
  404. dev_err(dev, "Failed to ioremap registers");
  405. return PTR_ERR(drvdata->cc_base);
  406. }
  407. /* Then IRQ */
  408. irq = platform_get_irq(pdev, 0);
  409. if (irq < 0)
  410. return irq;
  411. /* parse sampling rate from device tree */
  412. rc = cc_trng_parse_sampling_ratio(drvdata);
  413. if (rc) {
  414. dev_err(dev, "Failed to get legal sampling ratio for rosc\n");
  415. return rc;
  416. }
  417. rc = cc_trng_clk_init(drvdata);
  418. if (rc) {
  419. dev_err(dev, "cc_trng_clk_init failed\n");
  420. return rc;
  421. }
  422. INIT_WORK(&drvdata->compwork, cc_trng_compwork_handler);
  423. INIT_WORK(&drvdata->startwork, cc_trng_startwork_handler);
  424. spin_lock_init(&drvdata->read_lock);
  425. /* register the driver isr function */
  426. rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "cctrng", drvdata);
  427. if (rc) {
  428. dev_err(dev, "Could not register to interrupt %d\n", irq);
  429. goto post_clk_err;
  430. }
  431. dev_dbg(dev, "Registered to IRQ: %d\n", irq);
  432. /* Clear all pending interrupts */
  433. val = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
  434. dev_dbg(dev, "IRR=0x%08X\n", val);
  435. cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, val);
  436. /* unmask HOST RNG interrupt */
  437. cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
  438. cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
  439. ~CC_HOST_RNG_IRQ_MASK);
  440. /* init PM */
  441. rc = cc_trng_pm_init(drvdata);
  442. if (rc) {
  443. dev_err(dev, "cc_trng_pm_init failed\n");
  444. goto post_clk_err;
  445. }
  446. /* increment device's usage counter */
  447. rc = cc_trng_pm_get(dev);
  448. if (rc) {
  449. dev_err(dev, "cc_trng_pm_get returned %x\n", rc);
  450. goto post_pm_err;
  451. }
  452. /* set pending_hw to verify that HW won't be triggered from read */
  453. atomic_set(&drvdata->pending_hw, 1);
  454. /* registration of the hwrng device */
  455. rc = devm_hwrng_register(dev, &drvdata->rng);
  456. if (rc) {
  457. dev_err(dev, "Could not register hwrng device.\n");
  458. goto post_pm_err;
  459. }
  460. /* trigger HW to start generate data */
  461. drvdata->active_rosc = 0;
  462. cc_trng_hw_trigger(drvdata);
  463. /* All set, we can allow auto-suspend */
  464. cc_trng_pm_go(drvdata);
  465. dev_info(dev, "ARM cctrng device initialized\n");
  466. return 0;
  467. post_pm_err:
  468. cc_trng_pm_fini(drvdata);
  469. post_clk_err:
  470. cc_trng_clk_fini(drvdata);
  471. return rc;
  472. }
  473. static int cctrng_remove(struct platform_device *pdev)
  474. {
  475. struct cctrng_drvdata *drvdata = platform_get_drvdata(pdev);
  476. struct device *dev = &pdev->dev;
  477. dev_dbg(dev, "Releasing cctrng resources...\n");
  478. cc_trng_pm_fini(drvdata);
  479. cc_trng_clk_fini(drvdata);
  480. dev_info(dev, "ARM cctrng device terminated\n");
  481. return 0;
  482. }
  483. static int __maybe_unused cctrng_suspend(struct device *dev)
  484. {
  485. struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
  486. dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
  487. cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
  488. POWER_DOWN_ENABLE);
  489. clk_disable_unprepare(drvdata->clk);
  490. return 0;
  491. }
  492. static bool cctrng_wait_for_reset_completion(struct cctrng_drvdata *drvdata)
  493. {
  494. unsigned int val;
  495. unsigned int i;
  496. for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) {
  497. /* in cc7x3 NVM_IS_IDLE indicates that CC reset is
  498. * completed and device is fully functional
  499. */
  500. val = cc_ioread(drvdata, CC_NVM_IS_IDLE_REG_OFFSET);
  501. if (val & BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)) {
  502. /* hw indicate reset completed */
  503. return true;
  504. }
  505. /* allow scheduling other process on the processor */
  506. schedule();
  507. }
  508. /* reset not completed */
  509. return false;
  510. }
  511. static int __maybe_unused cctrng_resume(struct device *dev)
  512. {
  513. struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
  514. int rc;
  515. dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
  516. /* Enables the device source clk */
  517. rc = clk_prepare_enable(drvdata->clk);
  518. if (rc) {
  519. dev_err(dev, "failed getting clock back on. We're toast.\n");
  520. return rc;
  521. }
  522. /* wait for Cryptocell reset completion */
  523. if (!cctrng_wait_for_reset_completion(drvdata)) {
  524. dev_err(dev, "Cryptocell reset not completed");
  525. return -EBUSY;
  526. }
  527. /* unmask HOST RNG interrupt */
  528. cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
  529. cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
  530. ~CC_HOST_RNG_IRQ_MASK);
  531. cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
  532. POWER_DOWN_DISABLE);
  533. return 0;
  534. }
  535. static UNIVERSAL_DEV_PM_OPS(cctrng_pm, cctrng_suspend, cctrng_resume, NULL);
  536. static const struct of_device_id arm_cctrng_dt_match[] = {
  537. { .compatible = "arm,cryptocell-713-trng", },
  538. { .compatible = "arm,cryptocell-703-trng", },
  539. {},
  540. };
  541. MODULE_DEVICE_TABLE(of, arm_cctrng_dt_match);
  542. static struct platform_driver cctrng_driver = {
  543. .driver = {
  544. .name = "cctrng",
  545. .of_match_table = arm_cctrng_dt_match,
  546. .pm = &cctrng_pm,
  547. },
  548. .probe = cctrng_probe,
  549. .remove = cctrng_remove,
  550. };
  551. static int __init cctrng_mod_init(void)
  552. {
  553. /* Compile time assertion checks */
  554. BUILD_BUG_ON(CCTRNG_DATA_BUF_WORDS < 6);
  555. BUILD_BUG_ON((CCTRNG_DATA_BUF_WORDS & (CCTRNG_DATA_BUF_WORDS-1)) != 0);
  556. return platform_driver_register(&cctrng_driver);
  557. }
  558. module_init(cctrng_mod_init);
  559. static void __exit cctrng_mod_exit(void)
  560. {
  561. platform_driver_unregister(&cctrng_driver);
  562. }
  563. module_exit(cctrng_mod_exit);
  564. /* Module description */
  565. MODULE_DESCRIPTION("ARM CryptoCell TRNG Driver");
  566. MODULE_AUTHOR("ARM");
  567. MODULE_LICENSE("GPL v2");