tegra-gmi.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for NVIDIA Generic Memory Interface
  4. *
  5. * Copyright (C) 2016 Host Mobility AB. All rights reserved.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/reset.h>
  14. #include <soc/tegra/common.h>
  15. #define TEGRA_GMI_CONFIG 0x00
  16. #define TEGRA_GMI_CONFIG_GO BIT(31)
  17. #define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
  18. #define TEGRA_GMI_MUX_MODE BIT(28)
  19. #define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
  20. #define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
  21. #define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
  22. #define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
  23. #define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
  24. #define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
  25. #define TEGRA_GMI_TIMING0 0x10
  26. #define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
  27. #define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
  28. #define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
  29. #define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
  30. #define TEGRA_GMI_TIMING1 0x14
  31. #define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
  32. #define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
  33. #define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
  34. #define TEGRA_GMI_MAX_CHIP_SELECT 8
  35. struct tegra_gmi {
  36. struct device *dev;
  37. void __iomem *base;
  38. struct clk *clk;
  39. struct reset_control *rst;
  40. u32 snor_config;
  41. u32 snor_timing0;
  42. u32 snor_timing1;
  43. };
  44. static int tegra_gmi_enable(struct tegra_gmi *gmi)
  45. {
  46. int err;
  47. pm_runtime_enable(gmi->dev);
  48. err = pm_runtime_resume_and_get(gmi->dev);
  49. if (err) {
  50. pm_runtime_disable(gmi->dev);
  51. return err;
  52. }
  53. reset_control_assert(gmi->rst);
  54. usleep_range(2000, 4000);
  55. reset_control_deassert(gmi->rst);
  56. writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
  57. writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
  58. gmi->snor_config |= TEGRA_GMI_CONFIG_GO;
  59. writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
  60. return 0;
  61. }
  62. static void tegra_gmi_disable(struct tegra_gmi *gmi)
  63. {
  64. u32 config;
  65. /* stop GMI operation */
  66. config = readl(gmi->base + TEGRA_GMI_CONFIG);
  67. config &= ~TEGRA_GMI_CONFIG_GO;
  68. writel(config, gmi->base + TEGRA_GMI_CONFIG);
  69. reset_control_assert(gmi->rst);
  70. pm_runtime_put_sync_suspend(gmi->dev);
  71. pm_runtime_force_suspend(gmi->dev);
  72. }
  73. static int tegra_gmi_parse_dt(struct tegra_gmi *gmi)
  74. {
  75. struct device_node *child;
  76. u32 property, ranges[4];
  77. int err;
  78. child = of_get_next_available_child(gmi->dev->of_node, NULL);
  79. if (!child) {
  80. dev_err(gmi->dev, "no child nodes found\n");
  81. return -ENODEV;
  82. }
  83. /*
  84. * We currently only support one child device due to lack of
  85. * chip-select address decoding. Which means that we only have one
  86. * chip-select line from the GMI controller.
  87. */
  88. if (of_get_child_count(gmi->dev->of_node) > 1)
  89. dev_warn(gmi->dev, "only one child device is supported.");
  90. if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
  91. gmi->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
  92. if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
  93. gmi->snor_config |= TEGRA_GMI_MUX_MODE;
  94. if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
  95. gmi->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
  96. if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
  97. gmi->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
  98. if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
  99. gmi->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
  100. if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
  101. gmi->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
  102. if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
  103. gmi->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
  104. /* Decode the CS# */
  105. err = of_property_read_u32_array(child, "ranges", ranges, 4);
  106. if (err < 0) {
  107. /* Invalid binding */
  108. if (err == -EOVERFLOW) {
  109. dev_err(gmi->dev,
  110. "failed to decode CS: invalid ranges length\n");
  111. goto error_cs;
  112. }
  113. /*
  114. * If we reach here it means that the child node has an empty
  115. * ranges or it does not exist at all. Attempt to decode the
  116. * CS# from the reg property instead.
  117. */
  118. err = of_property_read_u32(child, "reg", &property);
  119. if (err < 0) {
  120. dev_err(gmi->dev,
  121. "failed to decode CS: no reg property found\n");
  122. goto error_cs;
  123. }
  124. } else {
  125. property = ranges[1];
  126. }
  127. /* Valid chip selects are CS0-CS7 */
  128. if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
  129. dev_err(gmi->dev, "invalid chip select: %d", property);
  130. err = -EINVAL;
  131. goto error_cs;
  132. }
  133. gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
  134. /* The default values that are provided below are reset values */
  135. if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
  136. gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
  137. else
  138. gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
  139. if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
  140. gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
  141. else
  142. gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
  143. if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
  144. gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
  145. else
  146. gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
  147. if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
  148. gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
  149. else
  150. gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
  151. if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
  152. gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
  153. else
  154. gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
  155. if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
  156. gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
  157. else
  158. gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
  159. if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
  160. gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
  161. else
  162. gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
  163. error_cs:
  164. of_node_put(child);
  165. return err;
  166. }
  167. static int tegra_gmi_probe(struct platform_device *pdev)
  168. {
  169. struct device *dev = &pdev->dev;
  170. struct tegra_gmi *gmi;
  171. struct resource *res;
  172. int err;
  173. gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
  174. if (!gmi)
  175. return -ENOMEM;
  176. platform_set_drvdata(pdev, gmi);
  177. gmi->dev = dev;
  178. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  179. gmi->base = devm_ioremap_resource(dev, res);
  180. if (IS_ERR(gmi->base))
  181. return PTR_ERR(gmi->base);
  182. gmi->clk = devm_clk_get(dev, "gmi");
  183. if (IS_ERR(gmi->clk)) {
  184. dev_err(dev, "can not get clock\n");
  185. return PTR_ERR(gmi->clk);
  186. }
  187. gmi->rst = devm_reset_control_get(dev, "gmi");
  188. if (IS_ERR(gmi->rst)) {
  189. dev_err(dev, "can not get reset\n");
  190. return PTR_ERR(gmi->rst);
  191. }
  192. err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
  193. if (err)
  194. return err;
  195. err = tegra_gmi_parse_dt(gmi);
  196. if (err)
  197. return err;
  198. err = tegra_gmi_enable(gmi);
  199. if (err < 0)
  200. return err;
  201. err = of_platform_default_populate(dev->of_node, NULL, dev);
  202. if (err < 0) {
  203. dev_err(dev, "fail to create devices.\n");
  204. tegra_gmi_disable(gmi);
  205. return err;
  206. }
  207. return 0;
  208. }
  209. static int tegra_gmi_remove(struct platform_device *pdev)
  210. {
  211. struct tegra_gmi *gmi = platform_get_drvdata(pdev);
  212. of_platform_depopulate(gmi->dev);
  213. tegra_gmi_disable(gmi);
  214. return 0;
  215. }
  216. static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev)
  217. {
  218. struct tegra_gmi *gmi = dev_get_drvdata(dev);
  219. int err;
  220. err = clk_prepare_enable(gmi->clk);
  221. if (err < 0) {
  222. dev_err(gmi->dev, "failed to enable clock: %d\n", err);
  223. return err;
  224. }
  225. return 0;
  226. }
  227. static int __maybe_unused tegra_gmi_runtime_suspend(struct device *dev)
  228. {
  229. struct tegra_gmi *gmi = dev_get_drvdata(dev);
  230. clk_disable_unprepare(gmi->clk);
  231. return 0;
  232. }
  233. static const struct dev_pm_ops tegra_gmi_pm = {
  234. SET_RUNTIME_PM_OPS(tegra_gmi_runtime_suspend, tegra_gmi_runtime_resume,
  235. NULL)
  236. };
  237. static const struct of_device_id tegra_gmi_id_table[] = {
  238. { .compatible = "nvidia,tegra20-gmi", },
  239. { .compatible = "nvidia,tegra30-gmi", },
  240. { }
  241. };
  242. MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
  243. static struct platform_driver tegra_gmi_driver = {
  244. .probe = tegra_gmi_probe,
  245. .remove = tegra_gmi_remove,
  246. .driver = {
  247. .name = "tegra-gmi",
  248. .of_match_table = tegra_gmi_id_table,
  249. .pm = &tegra_gmi_pm,
  250. },
  251. };
  252. module_platform_driver(tegra_gmi_driver);
  253. MODULE_AUTHOR("Mirza Krak <[email protected]");
  254. MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
  255. MODULE_LICENSE("GPL v2");