sunxi-rsb.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * RSB (Reduced Serial Bus) driver.
  4. *
  5. * Author: Chen-Yu Tsai <[email protected]>
  6. *
  7. * The RSB controller looks like an SMBus controller which only supports
  8. * byte and word data transfers. But, it differs from standard SMBus
  9. * protocol on several aspects:
  10. * - it uses addresses set at runtime to address slaves. Runtime addresses
  11. * are sent to slaves using their 12bit hardware addresses. Up to 15
  12. * runtime addresses are available.
  13. * - it adds a parity bit every 8bits of data and address for read and
  14. * write accesses; this replaces the ack bit
  15. * - only one read access is required to read a byte (instead of a write
  16. * followed by a read access in standard SMBus protocol)
  17. * - there's no Ack bit after each read access
  18. *
  19. * This means this bus cannot be used to interface with standard SMBus
  20. * devices. Devices known to support this interface include the AXP223,
  21. * AXP809, and AXP806 PMICs, and the AC100 audio codec, all from X-Powers.
  22. *
  23. * A description of the operation and wire protocol can be found in the
  24. * RSB section of Allwinner's A80 user manual, which can be found at
  25. *
  26. * https://github.com/allwinner-zh/documents/tree/master/A80
  27. *
  28. * This document is officially released by Allwinner.
  29. *
  30. * This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver.
  31. */
  32. #include <linux/clk.h>
  33. #include <linux/clk/clk-conf.h>
  34. #include <linux/device.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/io.h>
  37. #include <linux/iopoll.h>
  38. #include <linux/module.h>
  39. #include <linux/of.h>
  40. #include <linux/of_irq.h>
  41. #include <linux/of_platform.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/pm.h>
  44. #include <linux/pm_runtime.h>
  45. #include <linux/regmap.h>
  46. #include <linux/reset.h>
  47. #include <linux/slab.h>
  48. #include <linux/sunxi-rsb.h>
  49. #include <linux/types.h>
  50. /* RSB registers */
  51. #define RSB_CTRL 0x0 /* Global control */
  52. #define RSB_CCR 0x4 /* Clock control */
  53. #define RSB_INTE 0x8 /* Interrupt controls */
  54. #define RSB_INTS 0xc /* Interrupt status */
  55. #define RSB_ADDR 0x10 /* Address to send with read/write command */
  56. #define RSB_DATA 0x1c /* Data to read/write */
  57. #define RSB_LCR 0x24 /* Line control */
  58. #define RSB_DMCR 0x28 /* Device mode (init) control */
  59. #define RSB_CMD 0x2c /* RSB Command */
  60. #define RSB_DAR 0x30 /* Device address / runtime address */
  61. /* CTRL fields */
  62. #define RSB_CTRL_START_TRANS BIT(7)
  63. #define RSB_CTRL_ABORT_TRANS BIT(6)
  64. #define RSB_CTRL_GLOBAL_INT_ENB BIT(1)
  65. #define RSB_CTRL_SOFT_RST BIT(0)
  66. /* CLK CTRL fields */
  67. #define RSB_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
  68. #define RSB_CCR_MAX_CLK_DIV 0xff
  69. #define RSB_CCR_CLK_DIV(v) ((v) & RSB_CCR_MAX_CLK_DIV)
  70. /* STATUS fields */
  71. #define RSB_INTS_TRANS_ERR_ACK BIT(16)
  72. #define RSB_INTS_TRANS_ERR_DATA_BIT(v) (((v) >> 8) & 0xf)
  73. #define RSB_INTS_TRANS_ERR_DATA GENMASK(11, 8)
  74. #define RSB_INTS_LOAD_BSY BIT(2)
  75. #define RSB_INTS_TRANS_ERR BIT(1)
  76. #define RSB_INTS_TRANS_OVER BIT(0)
  77. /* LINE CTRL fields*/
  78. #define RSB_LCR_SCL_STATE BIT(5)
  79. #define RSB_LCR_SDA_STATE BIT(4)
  80. #define RSB_LCR_SCL_CTL BIT(3)
  81. #define RSB_LCR_SCL_CTL_EN BIT(2)
  82. #define RSB_LCR_SDA_CTL BIT(1)
  83. #define RSB_LCR_SDA_CTL_EN BIT(0)
  84. /* DEVICE MODE CTRL field values */
  85. #define RSB_DMCR_DEVICE_START BIT(31)
  86. #define RSB_DMCR_MODE_DATA (0x7c << 16)
  87. #define RSB_DMCR_MODE_REG (0x3e << 8)
  88. #define RSB_DMCR_DEV_ADDR 0x00
  89. /* CMD values */
  90. #define RSB_CMD_RD8 0x8b
  91. #define RSB_CMD_RD16 0x9c
  92. #define RSB_CMD_RD32 0xa6
  93. #define RSB_CMD_WR8 0x4e
  94. #define RSB_CMD_WR16 0x59
  95. #define RSB_CMD_WR32 0x63
  96. #define RSB_CMD_STRA 0xe8
  97. /* DAR fields */
  98. #define RSB_DAR_RTA(v) (((v) & 0xff) << 16)
  99. #define RSB_DAR_DA(v) ((v) & 0xffff)
  100. #define RSB_MAX_FREQ 20000000
  101. #define RSB_CTRL_NAME "sunxi-rsb"
  102. struct sunxi_rsb_addr_map {
  103. u16 hwaddr;
  104. u8 rtaddr;
  105. };
  106. struct sunxi_rsb {
  107. struct device *dev;
  108. void __iomem *regs;
  109. struct clk *clk;
  110. struct reset_control *rstc;
  111. struct completion complete;
  112. struct mutex lock;
  113. unsigned int status;
  114. u32 clk_freq;
  115. };
  116. /* bus / slave device related functions */
  117. static struct bus_type sunxi_rsb_bus;
  118. static int sunxi_rsb_device_match(struct device *dev, struct device_driver *drv)
  119. {
  120. return of_driver_match_device(dev, drv);
  121. }
  122. static int sunxi_rsb_device_probe(struct device *dev)
  123. {
  124. const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
  125. struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
  126. int ret;
  127. if (!drv->probe)
  128. return -ENODEV;
  129. if (!rdev->irq) {
  130. int irq = -ENOENT;
  131. if (dev->of_node)
  132. irq = of_irq_get(dev->of_node, 0);
  133. if (irq == -EPROBE_DEFER)
  134. return irq;
  135. if (irq < 0)
  136. irq = 0;
  137. rdev->irq = irq;
  138. }
  139. ret = of_clk_set_defaults(dev->of_node, false);
  140. if (ret < 0)
  141. return ret;
  142. return drv->probe(rdev);
  143. }
  144. static void sunxi_rsb_device_remove(struct device *dev)
  145. {
  146. const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
  147. drv->remove(to_sunxi_rsb_device(dev));
  148. }
  149. static struct bus_type sunxi_rsb_bus = {
  150. .name = RSB_CTRL_NAME,
  151. .match = sunxi_rsb_device_match,
  152. .probe = sunxi_rsb_device_probe,
  153. .remove = sunxi_rsb_device_remove,
  154. .uevent = of_device_uevent_modalias,
  155. };
  156. static void sunxi_rsb_dev_release(struct device *dev)
  157. {
  158. struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
  159. kfree(rdev);
  160. }
  161. /**
  162. * sunxi_rsb_device_create() - allocate and add an RSB device
  163. * @rsb: RSB controller
  164. * @node: RSB slave device node
  165. * @hwaddr: RSB slave hardware address
  166. * @rtaddr: RSB slave runtime address
  167. */
  168. static struct sunxi_rsb_device *sunxi_rsb_device_create(struct sunxi_rsb *rsb,
  169. struct device_node *node, u16 hwaddr, u8 rtaddr)
  170. {
  171. int err;
  172. struct sunxi_rsb_device *rdev;
  173. rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
  174. if (!rdev)
  175. return ERR_PTR(-ENOMEM);
  176. rdev->rsb = rsb;
  177. rdev->hwaddr = hwaddr;
  178. rdev->rtaddr = rtaddr;
  179. rdev->dev.bus = &sunxi_rsb_bus;
  180. rdev->dev.parent = rsb->dev;
  181. rdev->dev.of_node = node;
  182. rdev->dev.release = sunxi_rsb_dev_release;
  183. dev_set_name(&rdev->dev, "%s-%x", RSB_CTRL_NAME, hwaddr);
  184. err = device_register(&rdev->dev);
  185. if (err < 0) {
  186. dev_err(&rdev->dev, "Can't add %s, status %d\n",
  187. dev_name(&rdev->dev), err);
  188. goto err_device_add;
  189. }
  190. dev_dbg(&rdev->dev, "device %s registered\n", dev_name(&rdev->dev));
  191. return rdev;
  192. err_device_add:
  193. put_device(&rdev->dev);
  194. return ERR_PTR(err);
  195. }
  196. /**
  197. * sunxi_rsb_device_unregister(): unregister an RSB device
  198. * @rdev: rsb_device to be removed
  199. */
  200. static void sunxi_rsb_device_unregister(struct sunxi_rsb_device *rdev)
  201. {
  202. device_unregister(&rdev->dev);
  203. }
  204. static int sunxi_rsb_remove_devices(struct device *dev, void *data)
  205. {
  206. struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
  207. if (dev->bus == &sunxi_rsb_bus)
  208. sunxi_rsb_device_unregister(rdev);
  209. return 0;
  210. }
  211. /**
  212. * sunxi_rsb_driver_register() - Register device driver with RSB core
  213. * @rdrv: device driver to be associated with slave-device.
  214. *
  215. * This API will register the client driver with the RSB framework.
  216. * It is typically called from the driver's module-init function.
  217. */
  218. int sunxi_rsb_driver_register(struct sunxi_rsb_driver *rdrv)
  219. {
  220. rdrv->driver.bus = &sunxi_rsb_bus;
  221. return driver_register(&rdrv->driver);
  222. }
  223. EXPORT_SYMBOL_GPL(sunxi_rsb_driver_register);
  224. /* common code that starts a transfer */
  225. static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb)
  226. {
  227. u32 int_mask, status;
  228. bool timeout;
  229. if (readl(rsb->regs + RSB_CTRL) & RSB_CTRL_START_TRANS) {
  230. dev_dbg(rsb->dev, "RSB transfer still in progress\n");
  231. return -EBUSY;
  232. }
  233. reinit_completion(&rsb->complete);
  234. int_mask = RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER;
  235. writel(int_mask, rsb->regs + RSB_INTE);
  236. writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB,
  237. rsb->regs + RSB_CTRL);
  238. if (irqs_disabled()) {
  239. timeout = readl_poll_timeout_atomic(rsb->regs + RSB_INTS,
  240. status, (status & int_mask),
  241. 10, 100000);
  242. writel(status, rsb->regs + RSB_INTS);
  243. } else {
  244. timeout = !wait_for_completion_io_timeout(&rsb->complete,
  245. msecs_to_jiffies(100));
  246. status = rsb->status;
  247. }
  248. if (timeout) {
  249. dev_dbg(rsb->dev, "RSB timeout\n");
  250. /* abort the transfer */
  251. writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL);
  252. /* clear any interrupt flags */
  253. writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
  254. return -ETIMEDOUT;
  255. }
  256. if (status & RSB_INTS_LOAD_BSY) {
  257. dev_dbg(rsb->dev, "RSB busy\n");
  258. return -EBUSY;
  259. }
  260. if (status & RSB_INTS_TRANS_ERR) {
  261. if (status & RSB_INTS_TRANS_ERR_ACK) {
  262. dev_dbg(rsb->dev, "RSB slave nack\n");
  263. return -EINVAL;
  264. }
  265. if (status & RSB_INTS_TRANS_ERR_DATA) {
  266. dev_dbg(rsb->dev, "RSB transfer data error\n");
  267. return -EIO;
  268. }
  269. }
  270. return 0;
  271. }
  272. static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
  273. u32 *buf, size_t len)
  274. {
  275. u32 cmd;
  276. int ret;
  277. if (!buf)
  278. return -EINVAL;
  279. switch (len) {
  280. case 1:
  281. cmd = RSB_CMD_RD8;
  282. break;
  283. case 2:
  284. cmd = RSB_CMD_RD16;
  285. break;
  286. case 4:
  287. cmd = RSB_CMD_RD32;
  288. break;
  289. default:
  290. dev_err(rsb->dev, "Invalid access width: %zd\n", len);
  291. return -EINVAL;
  292. }
  293. ret = pm_runtime_resume_and_get(rsb->dev);
  294. if (ret)
  295. return ret;
  296. mutex_lock(&rsb->lock);
  297. writel(addr, rsb->regs + RSB_ADDR);
  298. writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
  299. writel(cmd, rsb->regs + RSB_CMD);
  300. ret = _sunxi_rsb_run_xfer(rsb);
  301. if (ret)
  302. goto unlock;
  303. *buf = readl(rsb->regs + RSB_DATA) & GENMASK(len * 8 - 1, 0);
  304. unlock:
  305. mutex_unlock(&rsb->lock);
  306. pm_runtime_mark_last_busy(rsb->dev);
  307. pm_runtime_put_autosuspend(rsb->dev);
  308. return ret;
  309. }
  310. static int sunxi_rsb_write(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
  311. const u32 *buf, size_t len)
  312. {
  313. u32 cmd;
  314. int ret;
  315. if (!buf)
  316. return -EINVAL;
  317. switch (len) {
  318. case 1:
  319. cmd = RSB_CMD_WR8;
  320. break;
  321. case 2:
  322. cmd = RSB_CMD_WR16;
  323. break;
  324. case 4:
  325. cmd = RSB_CMD_WR32;
  326. break;
  327. default:
  328. dev_err(rsb->dev, "Invalid access width: %zd\n", len);
  329. return -EINVAL;
  330. }
  331. ret = pm_runtime_resume_and_get(rsb->dev);
  332. if (ret)
  333. return ret;
  334. mutex_lock(&rsb->lock);
  335. writel(addr, rsb->regs + RSB_ADDR);
  336. writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
  337. writel(*buf, rsb->regs + RSB_DATA);
  338. writel(cmd, rsb->regs + RSB_CMD);
  339. ret = _sunxi_rsb_run_xfer(rsb);
  340. mutex_unlock(&rsb->lock);
  341. pm_runtime_mark_last_busy(rsb->dev);
  342. pm_runtime_put_autosuspend(rsb->dev);
  343. return ret;
  344. }
  345. /* RSB regmap functions */
  346. struct sunxi_rsb_ctx {
  347. struct sunxi_rsb_device *rdev;
  348. int size;
  349. };
  350. static int regmap_sunxi_rsb_reg_read(void *context, unsigned int reg,
  351. unsigned int *val)
  352. {
  353. struct sunxi_rsb_ctx *ctx = context;
  354. struct sunxi_rsb_device *rdev = ctx->rdev;
  355. if (reg > 0xff)
  356. return -EINVAL;
  357. return sunxi_rsb_read(rdev->rsb, rdev->rtaddr, reg, val, ctx->size);
  358. }
  359. static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg,
  360. unsigned int val)
  361. {
  362. struct sunxi_rsb_ctx *ctx = context;
  363. struct sunxi_rsb_device *rdev = ctx->rdev;
  364. return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size);
  365. }
  366. static void regmap_sunxi_rsb_free_ctx(void *context)
  367. {
  368. struct sunxi_rsb_ctx *ctx = context;
  369. kfree(ctx);
  370. }
  371. static struct regmap_bus regmap_sunxi_rsb = {
  372. .reg_write = regmap_sunxi_rsb_reg_write,
  373. .reg_read = regmap_sunxi_rsb_reg_read,
  374. .free_context = regmap_sunxi_rsb_free_ctx,
  375. .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
  376. .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
  377. };
  378. static struct sunxi_rsb_ctx *regmap_sunxi_rsb_init_ctx(struct sunxi_rsb_device *rdev,
  379. const struct regmap_config *config)
  380. {
  381. struct sunxi_rsb_ctx *ctx;
  382. switch (config->val_bits) {
  383. case 8:
  384. case 16:
  385. case 32:
  386. break;
  387. default:
  388. return ERR_PTR(-EINVAL);
  389. }
  390. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  391. if (!ctx)
  392. return ERR_PTR(-ENOMEM);
  393. ctx->rdev = rdev;
  394. ctx->size = config->val_bits / 8;
  395. return ctx;
  396. }
  397. struct regmap *__devm_regmap_init_sunxi_rsb(struct sunxi_rsb_device *rdev,
  398. const struct regmap_config *config,
  399. struct lock_class_key *lock_key,
  400. const char *lock_name)
  401. {
  402. struct sunxi_rsb_ctx *ctx = regmap_sunxi_rsb_init_ctx(rdev, config);
  403. if (IS_ERR(ctx))
  404. return ERR_CAST(ctx);
  405. return __devm_regmap_init(&rdev->dev, &regmap_sunxi_rsb, ctx, config,
  406. lock_key, lock_name);
  407. }
  408. EXPORT_SYMBOL_GPL(__devm_regmap_init_sunxi_rsb);
  409. /* RSB controller driver functions */
  410. static irqreturn_t sunxi_rsb_irq(int irq, void *dev_id)
  411. {
  412. struct sunxi_rsb *rsb = dev_id;
  413. u32 status;
  414. status = readl(rsb->regs + RSB_INTS);
  415. rsb->status = status;
  416. /* Clear interrupts */
  417. status &= (RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR |
  418. RSB_INTS_TRANS_OVER);
  419. writel(status, rsb->regs + RSB_INTS);
  420. complete(&rsb->complete);
  421. return IRQ_HANDLED;
  422. }
  423. static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb)
  424. {
  425. int ret = 0;
  426. u32 reg;
  427. /* send init sequence */
  428. writel(RSB_DMCR_DEVICE_START | RSB_DMCR_MODE_DATA |
  429. RSB_DMCR_MODE_REG | RSB_DMCR_DEV_ADDR, rsb->regs + RSB_DMCR);
  430. readl_poll_timeout(rsb->regs + RSB_DMCR, reg,
  431. !(reg & RSB_DMCR_DEVICE_START), 100, 250000);
  432. if (reg & RSB_DMCR_DEVICE_START)
  433. ret = -ETIMEDOUT;
  434. /* clear interrupt status bits */
  435. writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
  436. return ret;
  437. }
  438. /*
  439. * There are 15 valid runtime addresses, though Allwinner typically
  440. * skips the first, for unknown reasons, and uses the following three.
  441. *
  442. * 0x17, 0x2d, 0x3a, 0x4e, 0x59, 0x63, 0x74, 0x8b,
  443. * 0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff
  444. *
  445. * No designs with 2 RSB slave devices sharing identical hardware
  446. * addresses on the same bus have been seen in the wild. All designs
  447. * use 0x2d for the primary PMIC, 0x3a for the secondary PMIC if
  448. * there is one, and 0x45 for peripheral ICs.
  449. *
  450. * The hardware does not seem to support re-setting runtime addresses.
  451. * Attempts to do so result in the slave devices returning a NACK.
  452. * Hence we just hardcode the mapping here, like Allwinner does.
  453. */
  454. static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = {
  455. { 0x3a3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */
  456. { 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */
  457. { 0xe89, 0x4e }, /* Peripheral IC: AC100, ... */
  458. };
  459. static u8 sunxi_rsb_get_rtaddr(u16 hwaddr)
  460. {
  461. int i;
  462. for (i = 0; i < ARRAY_SIZE(sunxi_rsb_addr_maps); i++)
  463. if (hwaddr == sunxi_rsb_addr_maps[i].hwaddr)
  464. return sunxi_rsb_addr_maps[i].rtaddr;
  465. return 0; /* 0 is an invalid runtime address */
  466. }
  467. static int of_rsb_register_devices(struct sunxi_rsb *rsb)
  468. {
  469. struct device *dev = rsb->dev;
  470. struct device_node *child, *np = dev->of_node;
  471. u32 hwaddr;
  472. u8 rtaddr;
  473. int ret;
  474. if (!np)
  475. return -EINVAL;
  476. /* Runtime addresses for all slaves should be set first */
  477. for_each_available_child_of_node(np, child) {
  478. dev_dbg(dev, "setting child %pOF runtime address\n",
  479. child);
  480. ret = of_property_read_u32(child, "reg", &hwaddr);
  481. if (ret) {
  482. dev_err(dev, "%pOF: invalid 'reg' property: %d\n",
  483. child, ret);
  484. continue;
  485. }
  486. rtaddr = sunxi_rsb_get_rtaddr(hwaddr);
  487. if (!rtaddr) {
  488. dev_err(dev, "%pOF: unknown hardware device address\n",
  489. child);
  490. continue;
  491. }
  492. /*
  493. * Since no devices have been registered yet, we are the
  494. * only ones using the bus, we can skip locking the bus.
  495. */
  496. /* setup command parameters */
  497. writel(RSB_CMD_STRA, rsb->regs + RSB_CMD);
  498. writel(RSB_DAR_RTA(rtaddr) | RSB_DAR_DA(hwaddr),
  499. rsb->regs + RSB_DAR);
  500. /* send command */
  501. ret = _sunxi_rsb_run_xfer(rsb);
  502. if (ret)
  503. dev_warn(dev, "%pOF: set runtime address failed: %d\n",
  504. child, ret);
  505. }
  506. /* Then we start adding devices and probing them */
  507. for_each_available_child_of_node(np, child) {
  508. struct sunxi_rsb_device *rdev;
  509. dev_dbg(dev, "adding child %pOF\n", child);
  510. ret = of_property_read_u32(child, "reg", &hwaddr);
  511. if (ret)
  512. continue;
  513. rtaddr = sunxi_rsb_get_rtaddr(hwaddr);
  514. if (!rtaddr)
  515. continue;
  516. rdev = sunxi_rsb_device_create(rsb, child, hwaddr, rtaddr);
  517. if (IS_ERR(rdev))
  518. dev_err(dev, "failed to add child device %pOF: %ld\n",
  519. child, PTR_ERR(rdev));
  520. }
  521. return 0;
  522. }
  523. static int sunxi_rsb_hw_init(struct sunxi_rsb *rsb)
  524. {
  525. struct device *dev = rsb->dev;
  526. unsigned long p_clk_freq;
  527. u32 clk_delay, reg;
  528. int clk_div, ret;
  529. ret = clk_prepare_enable(rsb->clk);
  530. if (ret) {
  531. dev_err(dev, "failed to enable clk: %d\n", ret);
  532. return ret;
  533. }
  534. ret = reset_control_deassert(rsb->rstc);
  535. if (ret) {
  536. dev_err(dev, "failed to deassert reset line: %d\n", ret);
  537. goto err_clk_disable;
  538. }
  539. /* reset the controller */
  540. writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL);
  541. readl_poll_timeout(rsb->regs + RSB_CTRL, reg,
  542. !(reg & RSB_CTRL_SOFT_RST), 1000, 100000);
  543. /*
  544. * Clock frequency and delay calculation code is from
  545. * Allwinner U-boot sources.
  546. *
  547. * From A83 user manual:
  548. * bus clock frequency = parent clock frequency / (2 * (divider + 1))
  549. */
  550. p_clk_freq = clk_get_rate(rsb->clk);
  551. clk_div = p_clk_freq / rsb->clk_freq / 2;
  552. if (!clk_div)
  553. clk_div = 1;
  554. else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1)
  555. clk_div = RSB_CCR_MAX_CLK_DIV + 1;
  556. clk_delay = clk_div >> 1;
  557. if (!clk_delay)
  558. clk_delay = 1;
  559. dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2);
  560. writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1),
  561. rsb->regs + RSB_CCR);
  562. return 0;
  563. err_clk_disable:
  564. clk_disable_unprepare(rsb->clk);
  565. return ret;
  566. }
  567. static void sunxi_rsb_hw_exit(struct sunxi_rsb *rsb)
  568. {
  569. reset_control_assert(rsb->rstc);
  570. /* Keep the clock and PM reference counts consistent. */
  571. if (!pm_runtime_status_suspended(rsb->dev))
  572. clk_disable_unprepare(rsb->clk);
  573. }
  574. static int __maybe_unused sunxi_rsb_runtime_suspend(struct device *dev)
  575. {
  576. struct sunxi_rsb *rsb = dev_get_drvdata(dev);
  577. clk_disable_unprepare(rsb->clk);
  578. return 0;
  579. }
  580. static int __maybe_unused sunxi_rsb_runtime_resume(struct device *dev)
  581. {
  582. struct sunxi_rsb *rsb = dev_get_drvdata(dev);
  583. return clk_prepare_enable(rsb->clk);
  584. }
  585. static int __maybe_unused sunxi_rsb_suspend(struct device *dev)
  586. {
  587. struct sunxi_rsb *rsb = dev_get_drvdata(dev);
  588. sunxi_rsb_hw_exit(rsb);
  589. return 0;
  590. }
  591. static int __maybe_unused sunxi_rsb_resume(struct device *dev)
  592. {
  593. struct sunxi_rsb *rsb = dev_get_drvdata(dev);
  594. return sunxi_rsb_hw_init(rsb);
  595. }
  596. static int sunxi_rsb_probe(struct platform_device *pdev)
  597. {
  598. struct device *dev = &pdev->dev;
  599. struct device_node *np = dev->of_node;
  600. struct resource *r;
  601. struct sunxi_rsb *rsb;
  602. u32 clk_freq = 3000000;
  603. int irq, ret;
  604. of_property_read_u32(np, "clock-frequency", &clk_freq);
  605. if (clk_freq > RSB_MAX_FREQ) {
  606. dev_err(dev,
  607. "clock-frequency (%u Hz) is too high (max = 20MHz)\n",
  608. clk_freq);
  609. return -EINVAL;
  610. }
  611. rsb = devm_kzalloc(dev, sizeof(*rsb), GFP_KERNEL);
  612. if (!rsb)
  613. return -ENOMEM;
  614. rsb->dev = dev;
  615. rsb->clk_freq = clk_freq;
  616. platform_set_drvdata(pdev, rsb);
  617. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  618. rsb->regs = devm_ioremap_resource(dev, r);
  619. if (IS_ERR(rsb->regs))
  620. return PTR_ERR(rsb->regs);
  621. irq = platform_get_irq(pdev, 0);
  622. if (irq < 0)
  623. return irq;
  624. rsb->clk = devm_clk_get(dev, NULL);
  625. if (IS_ERR(rsb->clk)) {
  626. ret = PTR_ERR(rsb->clk);
  627. dev_err(dev, "failed to retrieve clk: %d\n", ret);
  628. return ret;
  629. }
  630. rsb->rstc = devm_reset_control_get(dev, NULL);
  631. if (IS_ERR(rsb->rstc)) {
  632. ret = PTR_ERR(rsb->rstc);
  633. dev_err(dev, "failed to retrieve reset controller: %d\n", ret);
  634. return ret;
  635. }
  636. init_completion(&rsb->complete);
  637. mutex_init(&rsb->lock);
  638. ret = devm_request_irq(dev, irq, sunxi_rsb_irq, 0, RSB_CTRL_NAME, rsb);
  639. if (ret) {
  640. dev_err(dev, "can't register interrupt handler irq %d: %d\n",
  641. irq, ret);
  642. return ret;
  643. }
  644. ret = sunxi_rsb_hw_init(rsb);
  645. if (ret)
  646. return ret;
  647. /* initialize all devices on the bus into RSB mode */
  648. ret = sunxi_rsb_init_device_mode(rsb);
  649. if (ret)
  650. dev_warn(dev, "Initialize device mode failed: %d\n", ret);
  651. pm_suspend_ignore_children(dev, true);
  652. pm_runtime_set_active(dev);
  653. pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
  654. pm_runtime_use_autosuspend(dev);
  655. pm_runtime_enable(dev);
  656. of_rsb_register_devices(rsb);
  657. return 0;
  658. }
  659. static int sunxi_rsb_remove(struct platform_device *pdev)
  660. {
  661. struct sunxi_rsb *rsb = platform_get_drvdata(pdev);
  662. device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices);
  663. pm_runtime_disable(&pdev->dev);
  664. sunxi_rsb_hw_exit(rsb);
  665. return 0;
  666. }
  667. static const struct dev_pm_ops sunxi_rsb_dev_pm_ops = {
  668. SET_RUNTIME_PM_OPS(sunxi_rsb_runtime_suspend,
  669. sunxi_rsb_runtime_resume, NULL)
  670. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sunxi_rsb_suspend, sunxi_rsb_resume)
  671. };
  672. static const struct of_device_id sunxi_rsb_of_match_table[] = {
  673. { .compatible = "allwinner,sun8i-a23-rsb" },
  674. {}
  675. };
  676. MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table);
  677. static struct platform_driver sunxi_rsb_driver = {
  678. .probe = sunxi_rsb_probe,
  679. .remove = sunxi_rsb_remove,
  680. .driver = {
  681. .name = RSB_CTRL_NAME,
  682. .of_match_table = sunxi_rsb_of_match_table,
  683. .pm = &sunxi_rsb_dev_pm_ops,
  684. },
  685. };
  686. static int __init sunxi_rsb_init(void)
  687. {
  688. int ret;
  689. ret = bus_register(&sunxi_rsb_bus);
  690. if (ret) {
  691. pr_err("failed to register sunxi sunxi_rsb bus: %d\n", ret);
  692. return ret;
  693. }
  694. ret = platform_driver_register(&sunxi_rsb_driver);
  695. if (ret) {
  696. bus_unregister(&sunxi_rsb_bus);
  697. return ret;
  698. }
  699. return 0;
  700. }
  701. module_init(sunxi_rsb_init);
  702. static void __exit sunxi_rsb_exit(void)
  703. {
  704. platform_driver_unregister(&sunxi_rsb_driver);
  705. bus_unregister(&sunxi_rsb_bus);
  706. }
  707. module_exit(sunxi_rsb_exit);
  708. MODULE_AUTHOR("Chen-Yu Tsai <[email protected]>");
  709. MODULE_DESCRIPTION("Allwinner sunXi Reduced Serial Bus controller driver");
  710. MODULE_LICENSE("GPL v2");