omap_l3_noc.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP L3 Interconnect error handling driver
  4. *
  5. * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
  6. * Santosh Shilimkar <[email protected]>
  7. * Sricharan <[email protected]>
  8. */
  9. #include <linux/init.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include "omap_l3_noc.h"
  19. /**
  20. * l3_handle_target() - Handle Target specific parse and reporting
  21. * @l3: pointer to l3 struct
  22. * @base: base address of clkdm
  23. * @flag_mux: flagmux corresponding to the event
  24. * @err_src: error source index of the slave (target)
  25. *
  26. * This does the second part of the error interrupt handling:
  27. * 3) Parse in the slave information
  28. * 4) Print the logged information.
  29. * 5) Add dump stack to provide kernel trace.
  30. * 6) Clear the source if known.
  31. *
  32. * This handles two types of errors:
  33. * 1) Custom errors in L3 :
  34. * Target like DMM/FW/EMIF generates SRESP=ERR error
  35. * 2) Standard L3 error:
  36. * - Unsupported CMD.
  37. * L3 tries to access target while it is idle
  38. * - OCP disconnect.
  39. * - Address hole error:
  40. * If DSS/ISS/FDIF/USBHOSTFS access a target where they
  41. * do not have connectivity, the error is logged in
  42. * their default target which is DMM2.
  43. *
  44. * On High Secure devices, firewall errors are possible and those
  45. * can be trapped as well. But the trapping is implemented as part
  46. * secure software and hence need not be implemented here.
  47. */
  48. static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
  49. struct l3_flagmux_data *flag_mux, int err_src)
  50. {
  51. int k;
  52. u32 std_err_main, clear, masterid;
  53. u8 op_code, m_req_info;
  54. void __iomem *l3_targ_base;
  55. void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
  56. void __iomem *l3_targ_hdr, *l3_targ_info;
  57. struct l3_target_data *l3_targ_inst;
  58. struct l3_masters_data *master;
  59. char *target_name, *master_name = "UN IDENTIFIED";
  60. char *err_description;
  61. char err_string[30] = { 0 };
  62. char info_string[60] = { 0 };
  63. /* We DONOT expect err_src to go out of bounds */
  64. BUG_ON(err_src > MAX_CLKDM_TARGETS);
  65. if (err_src < flag_mux->num_targ_data) {
  66. l3_targ_inst = &flag_mux->l3_targ[err_src];
  67. target_name = l3_targ_inst->name;
  68. l3_targ_base = base + l3_targ_inst->offset;
  69. } else {
  70. target_name = L3_TARGET_NOT_SUPPORTED;
  71. }
  72. if (target_name == L3_TARGET_NOT_SUPPORTED)
  73. return -ENODEV;
  74. /* Read the stderrlog_main_source from clk domain */
  75. l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
  76. l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
  77. std_err_main = readl_relaxed(l3_targ_stderr);
  78. switch (std_err_main & CUSTOM_ERROR) {
  79. case STANDARD_ERROR:
  80. err_description = "Standard";
  81. snprintf(err_string, sizeof(err_string),
  82. ": At Address: 0x%08X ",
  83. readl_relaxed(l3_targ_slvofslsb));
  84. l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
  85. l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_HDR;
  86. l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_INFO;
  87. break;
  88. case CUSTOM_ERROR:
  89. err_description = "Custom";
  90. l3_targ_mstaddr = l3_targ_base +
  91. L3_TARG_STDERRLOG_CINFO_MSTADDR;
  92. l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_CINFO_OPCODE;
  93. l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_CINFO_INFO;
  94. break;
  95. default:
  96. /* Nothing to be handled here as of now */
  97. return 0;
  98. }
  99. /* STDERRLOG_MSTADDR Stores the NTTP master address. */
  100. masterid = (readl_relaxed(l3_targ_mstaddr) &
  101. l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
  102. for (k = 0, master = l3->l3_masters; k < l3->num_masters;
  103. k++, master++) {
  104. if (masterid == master->id) {
  105. master_name = master->name;
  106. break;
  107. }
  108. }
  109. op_code = readl_relaxed(l3_targ_hdr) & 0x7;
  110. m_req_info = readl_relaxed(l3_targ_info) & 0xF;
  111. snprintf(info_string, sizeof(info_string),
  112. ": %s in %s mode during %s access",
  113. (m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access",
  114. (m_req_info & BIT(1)) ? "Supervisor" : "User",
  115. (m_req_info & BIT(3)) ? "Debug" : "Functional");
  116. WARN(true,
  117. "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n",
  118. dev_name(l3->dev),
  119. err_description,
  120. master_name, target_name,
  121. l3_transaction_type[op_code],
  122. err_string, info_string);
  123. /* clear the std error log*/
  124. clear = std_err_main | CLEAR_STDERR_LOG;
  125. writel_relaxed(clear, l3_targ_stderr);
  126. return 0;
  127. }
  128. /**
  129. * l3_interrupt_handler() - interrupt handler for l3 events
  130. * @irq: irq number
  131. * @_l3: pointer to l3 structure
  132. *
  133. * Interrupt Handler for L3 error detection.
  134. * 1) Identify the L3 clockdomain partition to which the error belongs to.
  135. * 2) Identify the slave where the error information is logged
  136. * ... handle the slave event..
  137. * 7) if the slave is unknown, mask out the slave.
  138. */
  139. static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
  140. {
  141. struct omap_l3 *l3 = _l3;
  142. int inttype, i, ret;
  143. int err_src = 0;
  144. u32 err_reg, mask_val;
  145. void __iomem *base, *mask_reg;
  146. struct l3_flagmux_data *flag_mux;
  147. /* Get the Type of interrupt */
  148. inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
  149. for (i = 0; i < l3->num_modules; i++) {
  150. /*
  151. * Read the regerr register of the clock domain
  152. * to determine the source
  153. */
  154. base = l3->l3_base[i];
  155. flag_mux = l3->l3_flagmux[i];
  156. err_reg = readl_relaxed(base + flag_mux->offset +
  157. L3_FLAGMUX_REGERR0 + (inttype << 3));
  158. err_reg &= ~(inttype ? flag_mux->mask_app_bits :
  159. flag_mux->mask_dbg_bits);
  160. /* Get the corresponding error and analyse */
  161. if (err_reg) {
  162. /* Identify the source from control status register */
  163. err_src = __ffs(err_reg);
  164. ret = l3_handle_target(l3, base, flag_mux, err_src);
  165. /*
  166. * Certain plaforms may have "undocumented" status
  167. * pending on boot. So dont generate a severe warning
  168. * here. Just mask it off to prevent the error from
  169. * reoccuring and locking up the system.
  170. */
  171. if (ret) {
  172. dev_err(l3->dev,
  173. "L3 %s error: target %d mod:%d %s\n",
  174. inttype ? "debug" : "application",
  175. err_src, i, "(unclearable)");
  176. mask_reg = base + flag_mux->offset +
  177. L3_FLAGMUX_MASK0 + (inttype << 3);
  178. mask_val = readl_relaxed(mask_reg);
  179. mask_val &= ~(1 << err_src);
  180. writel_relaxed(mask_val, mask_reg);
  181. /* Mark these bits as to be ignored */
  182. if (inttype)
  183. flag_mux->mask_app_bits |= 1 << err_src;
  184. else
  185. flag_mux->mask_dbg_bits |= 1 << err_src;
  186. }
  187. /* Error found so break the for loop */
  188. return IRQ_HANDLED;
  189. }
  190. }
  191. dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
  192. inttype ? "debug" : "application");
  193. return IRQ_NONE;
  194. }
  195. static const struct of_device_id l3_noc_match[] = {
  196. {.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
  197. {.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
  198. {.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
  199. {.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
  200. {},
  201. };
  202. MODULE_DEVICE_TABLE(of, l3_noc_match);
  203. static int omap_l3_probe(struct platform_device *pdev)
  204. {
  205. const struct of_device_id *of_id;
  206. static struct omap_l3 *l3;
  207. int ret, i, res_idx;
  208. of_id = of_match_device(l3_noc_match, &pdev->dev);
  209. if (!of_id) {
  210. dev_err(&pdev->dev, "OF data missing\n");
  211. return -EINVAL;
  212. }
  213. l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
  214. if (!l3)
  215. return -ENOMEM;
  216. memcpy(l3, of_id->data, sizeof(*l3));
  217. l3->dev = &pdev->dev;
  218. platform_set_drvdata(pdev, l3);
  219. /* Get mem resources */
  220. for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
  221. struct resource *res;
  222. if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
  223. /* First entry cannot be submodule */
  224. BUG_ON(i == 0);
  225. l3->l3_base[i] = l3->l3_base[i - 1];
  226. continue;
  227. }
  228. res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
  229. l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
  230. if (IS_ERR(l3->l3_base[i])) {
  231. dev_err(l3->dev, "ioremap %d failed\n", i);
  232. return PTR_ERR(l3->l3_base[i]);
  233. }
  234. res_idx++;
  235. }
  236. /*
  237. * Setup interrupt Handlers
  238. */
  239. l3->debug_irq = platform_get_irq(pdev, 0);
  240. ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
  241. IRQF_NO_THREAD, "l3-dbg-irq", l3);
  242. if (ret) {
  243. dev_err(l3->dev, "request_irq failed for %d\n",
  244. l3->debug_irq);
  245. return ret;
  246. }
  247. l3->app_irq = platform_get_irq(pdev, 1);
  248. ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
  249. IRQF_NO_THREAD, "l3-app-irq", l3);
  250. if (ret)
  251. dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
  252. return ret;
  253. }
  254. #ifdef CONFIG_PM_SLEEP
  255. /**
  256. * l3_resume_noirq() - resume function for l3_noc
  257. * @dev: pointer to l3_noc device structure
  258. *
  259. * We only have the resume handler only since we
  260. * have already maintained the delta register
  261. * configuration as part of configuring the system
  262. */
  263. static int l3_resume_noirq(struct device *dev)
  264. {
  265. struct omap_l3 *l3 = dev_get_drvdata(dev);
  266. int i;
  267. struct l3_flagmux_data *flag_mux;
  268. void __iomem *base, *mask_regx = NULL;
  269. u32 mask_val;
  270. for (i = 0; i < l3->num_modules; i++) {
  271. base = l3->l3_base[i];
  272. flag_mux = l3->l3_flagmux[i];
  273. if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
  274. continue;
  275. mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
  276. (L3_APPLICATION_ERROR << 3);
  277. mask_val = readl_relaxed(mask_regx);
  278. mask_val &= ~(flag_mux->mask_app_bits);
  279. writel_relaxed(mask_val, mask_regx);
  280. mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
  281. (L3_DEBUG_ERROR << 3);
  282. mask_val = readl_relaxed(mask_regx);
  283. mask_val &= ~(flag_mux->mask_dbg_bits);
  284. writel_relaxed(mask_val, mask_regx);
  285. }
  286. /* Dummy read to force OCP barrier */
  287. if (mask_regx)
  288. (void)readl(mask_regx);
  289. return 0;
  290. }
  291. static const struct dev_pm_ops l3_dev_pm_ops = {
  292. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, l3_resume_noirq)
  293. };
  294. #define L3_DEV_PM_OPS (&l3_dev_pm_ops)
  295. #else
  296. #define L3_DEV_PM_OPS NULL
  297. #endif
  298. static struct platform_driver omap_l3_driver = {
  299. .probe = omap_l3_probe,
  300. .driver = {
  301. .name = "omap_l3_noc",
  302. .pm = L3_DEV_PM_OPS,
  303. .of_match_table = of_match_ptr(l3_noc_match),
  304. },
  305. };
  306. static int __init omap_l3_init(void)
  307. {
  308. return platform_driver_register(&omap_l3_driver);
  309. }
  310. postcore_initcall_sync(omap_l3_init);
  311. static void __exit omap_l3_exit(void)
  312. {
  313. platform_driver_unregister(&omap_l3_driver);
  314. }
  315. module_exit(omap_l3_exit);
  316. MODULE_AUTHOR("Santosh Shilimkar");
  317. MODULE_AUTHOR("Sricharan R");
  318. MODULE_DESCRIPTION("OMAP L3 Interconnect error handling driver");
  319. MODULE_LICENSE("GPL v2");