sata_rcar.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Renesas R-Car SATA driver
  4. *
  5. * Author: Vladimir Barinov <[email protected]>
  6. * Copyright (C) 2013-2015 Cogent Embedded, Inc.
  7. * Copyright (C) 2013-2015 Renesas Solutions Corp.
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/ata.h>
  12. #include <linux/libata.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/err.h>
  17. #define DRV_NAME "sata_rcar"
  18. /* SH-Navi2G/ATAPI module compatible control registers */
  19. #define ATAPI_CONTROL1_REG 0x180
  20. #define ATAPI_STATUS_REG 0x184
  21. #define ATAPI_INT_ENABLE_REG 0x188
  22. #define ATAPI_DTB_ADR_REG 0x198
  23. #define ATAPI_DMA_START_ADR_REG 0x19C
  24. #define ATAPI_DMA_TRANS_CNT_REG 0x1A0
  25. #define ATAPI_CONTROL2_REG 0x1A4
  26. #define ATAPI_SIG_ST_REG 0x1B0
  27. #define ATAPI_BYTE_SWAP_REG 0x1BC
  28. /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
  29. #define ATAPI_CONTROL1_ISM BIT(16)
  30. #define ATAPI_CONTROL1_DTA32M BIT(11)
  31. #define ATAPI_CONTROL1_RESET BIT(7)
  32. #define ATAPI_CONTROL1_DESE BIT(3)
  33. #define ATAPI_CONTROL1_RW BIT(2)
  34. #define ATAPI_CONTROL1_STOP BIT(1)
  35. #define ATAPI_CONTROL1_START BIT(0)
  36. /* ATAPI status register (ATAPI_STATUS) bits */
  37. #define ATAPI_STATUS_SATAINT BIT(11)
  38. #define ATAPI_STATUS_DNEND BIT(6)
  39. #define ATAPI_STATUS_DEVTRM BIT(5)
  40. #define ATAPI_STATUS_DEVINT BIT(4)
  41. #define ATAPI_STATUS_ERR BIT(2)
  42. #define ATAPI_STATUS_NEND BIT(1)
  43. #define ATAPI_STATUS_ACT BIT(0)
  44. /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
  45. #define ATAPI_INT_ENABLE_SATAINT BIT(11)
  46. #define ATAPI_INT_ENABLE_DNEND BIT(6)
  47. #define ATAPI_INT_ENABLE_DEVTRM BIT(5)
  48. #define ATAPI_INT_ENABLE_DEVINT BIT(4)
  49. #define ATAPI_INT_ENABLE_ERR BIT(2)
  50. #define ATAPI_INT_ENABLE_NEND BIT(1)
  51. #define ATAPI_INT_ENABLE_ACT BIT(0)
  52. /* Access control registers for physical layer control register */
  53. #define SATAPHYADDR_REG 0x200
  54. #define SATAPHYWDATA_REG 0x204
  55. #define SATAPHYACCEN_REG 0x208
  56. #define SATAPHYRESET_REG 0x20C
  57. #define SATAPHYRDATA_REG 0x210
  58. #define SATAPHYACK_REG 0x214
  59. /* Physical layer control address command register (SATAPHYADDR) bits */
  60. #define SATAPHYADDR_PHYRATEMODE BIT(10)
  61. #define SATAPHYADDR_PHYCMD_READ BIT(9)
  62. #define SATAPHYADDR_PHYCMD_WRITE BIT(8)
  63. /* Physical layer control enable register (SATAPHYACCEN) bits */
  64. #define SATAPHYACCEN_PHYLANE BIT(0)
  65. /* Physical layer control reset register (SATAPHYRESET) bits */
  66. #define SATAPHYRESET_PHYRST BIT(1)
  67. #define SATAPHYRESET_PHYSRES BIT(0)
  68. /* Physical layer control acknowledge register (SATAPHYACK) bits */
  69. #define SATAPHYACK_PHYACK BIT(0)
  70. /* Serial-ATA HOST control registers */
  71. #define BISTCONF_REG 0x102C
  72. #define SDATA_REG 0x1100
  73. #define SSDEVCON_REG 0x1204
  74. #define SCRSSTS_REG 0x1400
  75. #define SCRSERR_REG 0x1404
  76. #define SCRSCON_REG 0x1408
  77. #define SCRSACT_REG 0x140C
  78. #define SATAINTSTAT_REG 0x1508
  79. #define SATAINTMASK_REG 0x150C
  80. /* SATA INT status register (SATAINTSTAT) bits */
  81. #define SATAINTSTAT_SERR BIT(3)
  82. #define SATAINTSTAT_ATA BIT(0)
  83. /* SATA INT mask register (SATAINTSTAT) bits */
  84. #define SATAINTMASK_SERRMSK BIT(3)
  85. #define SATAINTMASK_ERRMSK BIT(2)
  86. #define SATAINTMASK_ERRCRTMSK BIT(1)
  87. #define SATAINTMASK_ATAMSK BIT(0)
  88. #define SATAINTMASK_ALL_GEN1 0x7ff
  89. #define SATAINTMASK_ALL_GEN2 0xfff
  90. #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
  91. SATAINTMASK_ATAMSK)
  92. /* Physical Layer Control Registers */
  93. #define SATAPCTLR1_REG 0x43
  94. #define SATAPCTLR2_REG 0x52
  95. #define SATAPCTLR3_REG 0x5A
  96. #define SATAPCTLR4_REG 0x60
  97. /* Descriptor table word 0 bit (when DTA32M = 1) */
  98. #define SATA_RCAR_DTEND BIT(0)
  99. #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL
  100. /* Gen2 Physical Layer Control Registers */
  101. #define RCAR_GEN2_PHY_CTL1_REG 0x1704
  102. #define RCAR_GEN2_PHY_CTL1 0x34180002
  103. #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */
  104. #define RCAR_GEN2_PHY_CTL2_REG 0x170C
  105. #define RCAR_GEN2_PHY_CTL2 0x00002303
  106. #define RCAR_GEN2_PHY_CTL3_REG 0x171C
  107. #define RCAR_GEN2_PHY_CTL3 0x000B0194
  108. #define RCAR_GEN2_PHY_CTL4_REG 0x1724
  109. #define RCAR_GEN2_PHY_CTL4 0x00030994
  110. #define RCAR_GEN2_PHY_CTL5_REG 0x1740
  111. #define RCAR_GEN2_PHY_CTL5 0x03004001
  112. #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */
  113. #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */
  114. enum sata_rcar_type {
  115. RCAR_GEN1_SATA,
  116. RCAR_GEN2_SATA,
  117. RCAR_GEN3_SATA,
  118. RCAR_R8A7790_ES1_SATA,
  119. };
  120. struct sata_rcar_priv {
  121. void __iomem *base;
  122. u32 sataint_mask;
  123. enum sata_rcar_type type;
  124. };
  125. static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
  126. {
  127. void __iomem *base = priv->base;
  128. /* idle state */
  129. iowrite32(0, base + SATAPHYADDR_REG);
  130. /* reset */
  131. iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
  132. udelay(10);
  133. /* deassert reset */
  134. iowrite32(0, base + SATAPHYRESET_REG);
  135. }
  136. static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
  137. u32 val, int group)
  138. {
  139. void __iomem *base = priv->base;
  140. int timeout;
  141. /* deassert reset */
  142. iowrite32(0, base + SATAPHYRESET_REG);
  143. /* lane 1 */
  144. iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
  145. /* write phy register value */
  146. iowrite32(val, base + SATAPHYWDATA_REG);
  147. /* set register group */
  148. if (group)
  149. reg |= SATAPHYADDR_PHYRATEMODE;
  150. /* write command */
  151. iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
  152. /* wait for ack */
  153. for (timeout = 0; timeout < 100; timeout++) {
  154. val = ioread32(base + SATAPHYACK_REG);
  155. if (val & SATAPHYACK_PHYACK)
  156. break;
  157. }
  158. if (timeout >= 100)
  159. pr_err("%s timeout\n", __func__);
  160. /* idle state */
  161. iowrite32(0, base + SATAPHYADDR_REG);
  162. }
  163. static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
  164. {
  165. sata_rcar_gen1_phy_preinit(priv);
  166. sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
  167. sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
  168. sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
  169. sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
  170. sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
  171. sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
  172. }
  173. static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
  174. {
  175. void __iomem *base = priv->base;
  176. iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
  177. iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
  178. iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
  179. iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
  180. iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
  181. RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
  182. }
  183. static void sata_rcar_freeze(struct ata_port *ap)
  184. {
  185. struct sata_rcar_priv *priv = ap->host->private_data;
  186. /* mask */
  187. iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG);
  188. ata_sff_freeze(ap);
  189. }
  190. static void sata_rcar_thaw(struct ata_port *ap)
  191. {
  192. struct sata_rcar_priv *priv = ap->host->private_data;
  193. void __iomem *base = priv->base;
  194. /* ack */
  195. iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
  196. ata_sff_thaw(ap);
  197. /* unmask */
  198. iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
  199. }
  200. static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
  201. {
  202. u16 *ptr = buffer;
  203. while (count--) {
  204. u16 data = ioread32(reg);
  205. *ptr++ = data;
  206. }
  207. }
  208. static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
  209. {
  210. const u16 *ptr = buffer;
  211. while (count--)
  212. iowrite32(*ptr++, reg);
  213. }
  214. static u8 sata_rcar_check_status(struct ata_port *ap)
  215. {
  216. return ioread32(ap->ioaddr.status_addr);
  217. }
  218. static u8 sata_rcar_check_altstatus(struct ata_port *ap)
  219. {
  220. return ioread32(ap->ioaddr.altstatus_addr);
  221. }
  222. static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
  223. {
  224. iowrite32(ctl, ap->ioaddr.ctl_addr);
  225. }
  226. static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
  227. {
  228. iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
  229. ata_sff_pause(ap); /* needed; also flushes, for mmio */
  230. }
  231. static bool sata_rcar_ata_devchk(struct ata_port *ap, unsigned int device)
  232. {
  233. struct ata_ioports *ioaddr = &ap->ioaddr;
  234. u8 nsect, lbal;
  235. sata_rcar_dev_select(ap, device);
  236. iowrite32(0x55, ioaddr->nsect_addr);
  237. iowrite32(0xaa, ioaddr->lbal_addr);
  238. iowrite32(0xaa, ioaddr->nsect_addr);
  239. iowrite32(0x55, ioaddr->lbal_addr);
  240. iowrite32(0x55, ioaddr->nsect_addr);
  241. iowrite32(0xaa, ioaddr->lbal_addr);
  242. nsect = ioread32(ioaddr->nsect_addr);
  243. lbal = ioread32(ioaddr->lbal_addr);
  244. if (nsect == 0x55 && lbal == 0xaa)
  245. return true; /* found a device */
  246. return false; /* nothing found */
  247. }
  248. static int sata_rcar_wait_after_reset(struct ata_link *link,
  249. unsigned long deadline)
  250. {
  251. struct ata_port *ap = link->ap;
  252. ata_msleep(ap, ATA_WAIT_AFTER_RESET);
  253. return ata_sff_wait_ready(link, deadline);
  254. }
  255. static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
  256. {
  257. struct ata_ioports *ioaddr = &ap->ioaddr;
  258. /* software reset. causes dev0 to be selected */
  259. iowrite32(ap->ctl, ioaddr->ctl_addr);
  260. udelay(20);
  261. iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
  262. udelay(20);
  263. iowrite32(ap->ctl, ioaddr->ctl_addr);
  264. ap->last_ctl = ap->ctl;
  265. /* wait the port to become ready */
  266. return sata_rcar_wait_after_reset(&ap->link, deadline);
  267. }
  268. static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
  269. unsigned long deadline)
  270. {
  271. struct ata_port *ap = link->ap;
  272. unsigned int devmask = 0;
  273. int rc;
  274. u8 err;
  275. /* determine if device 0 is present */
  276. if (sata_rcar_ata_devchk(ap, 0))
  277. devmask |= 1 << 0;
  278. /* issue bus reset */
  279. rc = sata_rcar_bus_softreset(ap, deadline);
  280. /* if link is occupied, -ENODEV too is an error */
  281. if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
  282. ata_link_err(link, "SRST failed (errno=%d)\n", rc);
  283. return rc;
  284. }
  285. /* determine by signature whether we have ATA or ATAPI devices */
  286. classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
  287. return 0;
  288. }
  289. static void sata_rcar_tf_load(struct ata_port *ap,
  290. const struct ata_taskfile *tf)
  291. {
  292. struct ata_ioports *ioaddr = &ap->ioaddr;
  293. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  294. if (tf->ctl != ap->last_ctl) {
  295. iowrite32(tf->ctl, ioaddr->ctl_addr);
  296. ap->last_ctl = tf->ctl;
  297. ata_wait_idle(ap);
  298. }
  299. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  300. iowrite32(tf->hob_feature, ioaddr->feature_addr);
  301. iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
  302. iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
  303. iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
  304. iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
  305. }
  306. if (is_addr) {
  307. iowrite32(tf->feature, ioaddr->feature_addr);
  308. iowrite32(tf->nsect, ioaddr->nsect_addr);
  309. iowrite32(tf->lbal, ioaddr->lbal_addr);
  310. iowrite32(tf->lbam, ioaddr->lbam_addr);
  311. iowrite32(tf->lbah, ioaddr->lbah_addr);
  312. }
  313. if (tf->flags & ATA_TFLAG_DEVICE)
  314. iowrite32(tf->device, ioaddr->device_addr);
  315. ata_wait_idle(ap);
  316. }
  317. static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  318. {
  319. struct ata_ioports *ioaddr = &ap->ioaddr;
  320. tf->status = sata_rcar_check_status(ap);
  321. tf->error = ioread32(ioaddr->error_addr);
  322. tf->nsect = ioread32(ioaddr->nsect_addr);
  323. tf->lbal = ioread32(ioaddr->lbal_addr);
  324. tf->lbam = ioread32(ioaddr->lbam_addr);
  325. tf->lbah = ioread32(ioaddr->lbah_addr);
  326. tf->device = ioread32(ioaddr->device_addr);
  327. if (tf->flags & ATA_TFLAG_LBA48) {
  328. iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  329. tf->hob_feature = ioread32(ioaddr->error_addr);
  330. tf->hob_nsect = ioread32(ioaddr->nsect_addr);
  331. tf->hob_lbal = ioread32(ioaddr->lbal_addr);
  332. tf->hob_lbam = ioread32(ioaddr->lbam_addr);
  333. tf->hob_lbah = ioread32(ioaddr->lbah_addr);
  334. iowrite32(tf->ctl, ioaddr->ctl_addr);
  335. ap->last_ctl = tf->ctl;
  336. }
  337. }
  338. static void sata_rcar_exec_command(struct ata_port *ap,
  339. const struct ata_taskfile *tf)
  340. {
  341. iowrite32(tf->command, ap->ioaddr.command_addr);
  342. ata_sff_pause(ap);
  343. }
  344. static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc,
  345. unsigned char *buf,
  346. unsigned int buflen, int rw)
  347. {
  348. struct ata_port *ap = qc->dev->link->ap;
  349. void __iomem *data_addr = ap->ioaddr.data_addr;
  350. unsigned int words = buflen >> 1;
  351. /* Transfer multiple of 2 bytes */
  352. if (rw == READ)
  353. sata_rcar_ioread16_rep(data_addr, buf, words);
  354. else
  355. sata_rcar_iowrite16_rep(data_addr, buf, words);
  356. /* Transfer trailing byte, if any. */
  357. if (unlikely(buflen & 0x01)) {
  358. unsigned char pad[2] = { };
  359. /* Point buf to the tail of buffer */
  360. buf += buflen - 1;
  361. /*
  362. * Use io*16_rep() accessors here as well to avoid pointlessly
  363. * swapping bytes to and from on the big endian machines...
  364. */
  365. if (rw == READ) {
  366. sata_rcar_ioread16_rep(data_addr, pad, 1);
  367. *buf = pad[0];
  368. } else {
  369. pad[0] = *buf;
  370. sata_rcar_iowrite16_rep(data_addr, pad, 1);
  371. }
  372. words++;
  373. }
  374. return words << 1;
  375. }
  376. static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
  377. {
  378. int count;
  379. struct ata_port *ap;
  380. /* We only need to flush incoming data when a command was running */
  381. if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
  382. return;
  383. ap = qc->ap;
  384. /* Drain up to 64K of data before we give up this recovery method */
  385. for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
  386. count < 65536; count += 2)
  387. ioread32(ap->ioaddr.data_addr);
  388. if (count)
  389. ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
  390. }
  391. static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
  392. u32 *val)
  393. {
  394. if (sc_reg > SCR_ACTIVE)
  395. return -EINVAL;
  396. *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
  397. return 0;
  398. }
  399. static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
  400. u32 val)
  401. {
  402. if (sc_reg > SCR_ACTIVE)
  403. return -EINVAL;
  404. iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
  405. return 0;
  406. }
  407. static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
  408. {
  409. struct ata_port *ap = qc->ap;
  410. struct ata_bmdma_prd *prd = ap->bmdma_prd;
  411. struct scatterlist *sg;
  412. unsigned int si;
  413. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  414. u32 addr, sg_len;
  415. /*
  416. * Note: h/w doesn't support 64-bit, so we unconditionally
  417. * truncate dma_addr_t to u32.
  418. */
  419. addr = (u32)sg_dma_address(sg);
  420. sg_len = sg_dma_len(sg);
  421. prd[si].addr = cpu_to_le32(addr);
  422. prd[si].flags_len = cpu_to_le32(sg_len);
  423. }
  424. /* end-of-table flag */
  425. prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
  426. }
  427. static enum ata_completion_errors sata_rcar_qc_prep(struct ata_queued_cmd *qc)
  428. {
  429. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  430. return AC_ERR_OK;
  431. sata_rcar_bmdma_fill_sg(qc);
  432. return AC_ERR_OK;
  433. }
  434. static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
  435. {
  436. struct ata_port *ap = qc->ap;
  437. unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
  438. struct sata_rcar_priv *priv = ap->host->private_data;
  439. void __iomem *base = priv->base;
  440. u32 dmactl;
  441. /* load PRD table addr. */
  442. mb(); /* make sure PRD table writes are visible to controller */
  443. iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
  444. /* specify data direction, triple-check start bit is clear */
  445. dmactl = ioread32(base + ATAPI_CONTROL1_REG);
  446. dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
  447. if (dmactl & ATAPI_CONTROL1_START) {
  448. dmactl &= ~ATAPI_CONTROL1_START;
  449. dmactl |= ATAPI_CONTROL1_STOP;
  450. }
  451. if (!rw)
  452. dmactl |= ATAPI_CONTROL1_RW;
  453. iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
  454. /* issue r/w command */
  455. ap->ops->sff_exec_command(ap, &qc->tf);
  456. }
  457. static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
  458. {
  459. struct ata_port *ap = qc->ap;
  460. struct sata_rcar_priv *priv = ap->host->private_data;
  461. void __iomem *base = priv->base;
  462. u32 dmactl;
  463. /* start host DMA transaction */
  464. dmactl = ioread32(base + ATAPI_CONTROL1_REG);
  465. dmactl &= ~ATAPI_CONTROL1_STOP;
  466. dmactl |= ATAPI_CONTROL1_START;
  467. iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
  468. }
  469. static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
  470. {
  471. struct ata_port *ap = qc->ap;
  472. struct sata_rcar_priv *priv = ap->host->private_data;
  473. void __iomem *base = priv->base;
  474. u32 dmactl;
  475. /* force termination of DMA transfer if active */
  476. dmactl = ioread32(base + ATAPI_CONTROL1_REG);
  477. if (dmactl & ATAPI_CONTROL1_START) {
  478. dmactl &= ~ATAPI_CONTROL1_START;
  479. dmactl |= ATAPI_CONTROL1_STOP;
  480. iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
  481. }
  482. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  483. ata_sff_dma_pause(ap);
  484. }
  485. static u8 sata_rcar_bmdma_status(struct ata_port *ap)
  486. {
  487. struct sata_rcar_priv *priv = ap->host->private_data;
  488. u8 host_stat = 0;
  489. u32 status;
  490. status = ioread32(priv->base + ATAPI_STATUS_REG);
  491. if (status & ATAPI_STATUS_DEVINT)
  492. host_stat |= ATA_DMA_INTR;
  493. if (status & ATAPI_STATUS_ACT)
  494. host_stat |= ATA_DMA_ACTIVE;
  495. return host_stat;
  496. }
  497. static struct scsi_host_template sata_rcar_sht = {
  498. ATA_BASE_SHT(DRV_NAME),
  499. /*
  500. * This controller allows transfer chunks up to 512MB which cross 64KB
  501. * boundaries, therefore the DMA limits are more relaxed than standard
  502. * ATA SFF.
  503. */
  504. .sg_tablesize = ATA_MAX_PRD,
  505. .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
  506. };
  507. static struct ata_port_operations sata_rcar_port_ops = {
  508. .inherits = &ata_bmdma_port_ops,
  509. .freeze = sata_rcar_freeze,
  510. .thaw = sata_rcar_thaw,
  511. .softreset = sata_rcar_softreset,
  512. .scr_read = sata_rcar_scr_read,
  513. .scr_write = sata_rcar_scr_write,
  514. .sff_dev_select = sata_rcar_dev_select,
  515. .sff_set_devctl = sata_rcar_set_devctl,
  516. .sff_check_status = sata_rcar_check_status,
  517. .sff_check_altstatus = sata_rcar_check_altstatus,
  518. .sff_tf_load = sata_rcar_tf_load,
  519. .sff_tf_read = sata_rcar_tf_read,
  520. .sff_exec_command = sata_rcar_exec_command,
  521. .sff_data_xfer = sata_rcar_data_xfer,
  522. .sff_drain_fifo = sata_rcar_drain_fifo,
  523. .qc_prep = sata_rcar_qc_prep,
  524. .bmdma_setup = sata_rcar_bmdma_setup,
  525. .bmdma_start = sata_rcar_bmdma_start,
  526. .bmdma_stop = sata_rcar_bmdma_stop,
  527. .bmdma_status = sata_rcar_bmdma_status,
  528. };
  529. static void sata_rcar_serr_interrupt(struct ata_port *ap)
  530. {
  531. struct sata_rcar_priv *priv = ap->host->private_data;
  532. struct ata_eh_info *ehi = &ap->link.eh_info;
  533. int freeze = 0;
  534. u32 serror;
  535. serror = ioread32(priv->base + SCRSERR_REG);
  536. if (!serror)
  537. return;
  538. ata_port_dbg(ap, "SError @host_intr: 0x%x\n", serror);
  539. /* first, analyze and record host port events */
  540. ata_ehi_clear_desc(ehi);
  541. if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
  542. /* Setup a soft-reset EH action */
  543. ata_ehi_hotplugged(ehi);
  544. ata_ehi_push_desc(ehi, "%s", "hotplug");
  545. freeze = serror & SERR_COMM_WAKE ? 0 : 1;
  546. }
  547. /* freeze or abort */
  548. if (freeze)
  549. ata_port_freeze(ap);
  550. else
  551. ata_port_abort(ap);
  552. }
  553. static void sata_rcar_ata_interrupt(struct ata_port *ap)
  554. {
  555. struct ata_queued_cmd *qc;
  556. int handled = 0;
  557. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  558. if (qc)
  559. handled |= ata_bmdma_port_intr(ap, qc);
  560. /* be sure to clear ATA interrupt */
  561. if (!handled)
  562. sata_rcar_check_status(ap);
  563. }
  564. static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
  565. {
  566. struct ata_host *host = dev_instance;
  567. struct sata_rcar_priv *priv = host->private_data;
  568. void __iomem *base = priv->base;
  569. unsigned int handled = 0;
  570. struct ata_port *ap;
  571. u32 sataintstat;
  572. unsigned long flags;
  573. spin_lock_irqsave(&host->lock, flags);
  574. sataintstat = ioread32(base + SATAINTSTAT_REG);
  575. sataintstat &= SATA_RCAR_INT_MASK;
  576. if (!sataintstat)
  577. goto done;
  578. /* ack */
  579. iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG);
  580. ap = host->ports[0];
  581. if (sataintstat & SATAINTSTAT_ATA)
  582. sata_rcar_ata_interrupt(ap);
  583. if (sataintstat & SATAINTSTAT_SERR)
  584. sata_rcar_serr_interrupt(ap);
  585. handled = 1;
  586. done:
  587. spin_unlock_irqrestore(&host->lock, flags);
  588. return IRQ_RETVAL(handled);
  589. }
  590. static void sata_rcar_setup_port(struct ata_host *host)
  591. {
  592. struct ata_port *ap = host->ports[0];
  593. struct ata_ioports *ioaddr = &ap->ioaddr;
  594. struct sata_rcar_priv *priv = host->private_data;
  595. void __iomem *base = priv->base;
  596. ap->ops = &sata_rcar_port_ops;
  597. ap->pio_mask = ATA_PIO4;
  598. ap->udma_mask = ATA_UDMA6;
  599. ap->flags |= ATA_FLAG_SATA;
  600. if (priv->type == RCAR_R8A7790_ES1_SATA)
  601. ap->flags |= ATA_FLAG_NO_DIPM;
  602. ioaddr->cmd_addr = base + SDATA_REG;
  603. ioaddr->ctl_addr = base + SSDEVCON_REG;
  604. ioaddr->scr_addr = base + SCRSSTS_REG;
  605. ioaddr->altstatus_addr = ioaddr->ctl_addr;
  606. ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
  607. ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
  608. ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
  609. ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
  610. ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
  611. ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
  612. ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
  613. ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
  614. ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
  615. ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
  616. }
  617. static void sata_rcar_init_module(struct sata_rcar_priv *priv)
  618. {
  619. void __iomem *base = priv->base;
  620. u32 val;
  621. /* SATA-IP reset state */
  622. val = ioread32(base + ATAPI_CONTROL1_REG);
  623. val |= ATAPI_CONTROL1_RESET;
  624. iowrite32(val, base + ATAPI_CONTROL1_REG);
  625. /* ISM mode, PRD mode, DTEND flag at bit 0 */
  626. val = ioread32(base + ATAPI_CONTROL1_REG);
  627. val |= ATAPI_CONTROL1_ISM;
  628. val |= ATAPI_CONTROL1_DESE;
  629. val |= ATAPI_CONTROL1_DTA32M;
  630. iowrite32(val, base + ATAPI_CONTROL1_REG);
  631. /* Release the SATA-IP from the reset state */
  632. val = ioread32(base + ATAPI_CONTROL1_REG);
  633. val &= ~ATAPI_CONTROL1_RESET;
  634. iowrite32(val, base + ATAPI_CONTROL1_REG);
  635. /* ack and mask */
  636. iowrite32(0, base + SATAINTSTAT_REG);
  637. iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
  638. /* enable interrupts */
  639. iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
  640. }
  641. static void sata_rcar_init_controller(struct ata_host *host)
  642. {
  643. struct sata_rcar_priv *priv = host->private_data;
  644. priv->sataint_mask = SATAINTMASK_ALL_GEN2;
  645. /* reset and setup phy */
  646. switch (priv->type) {
  647. case RCAR_GEN1_SATA:
  648. priv->sataint_mask = SATAINTMASK_ALL_GEN1;
  649. sata_rcar_gen1_phy_init(priv);
  650. break;
  651. case RCAR_GEN2_SATA:
  652. case RCAR_R8A7790_ES1_SATA:
  653. sata_rcar_gen2_phy_init(priv);
  654. break;
  655. case RCAR_GEN3_SATA:
  656. break;
  657. default:
  658. dev_warn(host->dev, "SATA phy is not initialized\n");
  659. break;
  660. }
  661. sata_rcar_init_module(priv);
  662. }
  663. static const struct of_device_id sata_rcar_match[] = {
  664. {
  665. /* Deprecated by "renesas,sata-r8a7779" */
  666. .compatible = "renesas,rcar-sata",
  667. .data = (void *)RCAR_GEN1_SATA,
  668. },
  669. {
  670. .compatible = "renesas,sata-r8a7779",
  671. .data = (void *)RCAR_GEN1_SATA,
  672. },
  673. {
  674. .compatible = "renesas,sata-r8a7790",
  675. .data = (void *)RCAR_GEN2_SATA
  676. },
  677. {
  678. .compatible = "renesas,sata-r8a7790-es1",
  679. .data = (void *)RCAR_R8A7790_ES1_SATA
  680. },
  681. {
  682. .compatible = "renesas,sata-r8a7791",
  683. .data = (void *)RCAR_GEN2_SATA
  684. },
  685. {
  686. .compatible = "renesas,sata-r8a7793",
  687. .data = (void *)RCAR_GEN2_SATA
  688. },
  689. {
  690. .compatible = "renesas,sata-r8a7795",
  691. .data = (void *)RCAR_GEN3_SATA
  692. },
  693. {
  694. .compatible = "renesas,rcar-gen2-sata",
  695. .data = (void *)RCAR_GEN2_SATA
  696. },
  697. {
  698. .compatible = "renesas,rcar-gen3-sata",
  699. .data = (void *)RCAR_GEN3_SATA
  700. },
  701. { /* sentinel */ }
  702. };
  703. MODULE_DEVICE_TABLE(of, sata_rcar_match);
  704. static int sata_rcar_probe(struct platform_device *pdev)
  705. {
  706. struct device *dev = &pdev->dev;
  707. struct ata_host *host;
  708. struct sata_rcar_priv *priv;
  709. struct resource *mem;
  710. int irq;
  711. int ret = 0;
  712. irq = platform_get_irq(pdev, 0);
  713. if (irq < 0)
  714. return irq;
  715. if (!irq)
  716. return -EINVAL;
  717. priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL);
  718. if (!priv)
  719. return -ENOMEM;
  720. priv->type = (unsigned long)of_device_get_match_data(dev);
  721. pm_runtime_enable(dev);
  722. ret = pm_runtime_get_sync(dev);
  723. if (ret < 0)
  724. goto err_pm_put;
  725. host = ata_host_alloc(dev, 1);
  726. if (!host) {
  727. ret = -ENOMEM;
  728. goto err_pm_put;
  729. }
  730. host->private_data = priv;
  731. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  732. priv->base = devm_ioremap_resource(dev, mem);
  733. if (IS_ERR(priv->base)) {
  734. ret = PTR_ERR(priv->base);
  735. goto err_pm_put;
  736. }
  737. /* setup port */
  738. sata_rcar_setup_port(host);
  739. /* initialize host controller */
  740. sata_rcar_init_controller(host);
  741. ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
  742. &sata_rcar_sht);
  743. if (!ret)
  744. return 0;
  745. err_pm_put:
  746. pm_runtime_put(dev);
  747. pm_runtime_disable(dev);
  748. return ret;
  749. }
  750. static int sata_rcar_remove(struct platform_device *pdev)
  751. {
  752. struct ata_host *host = platform_get_drvdata(pdev);
  753. struct sata_rcar_priv *priv = host->private_data;
  754. void __iomem *base = priv->base;
  755. ata_host_detach(host);
  756. /* disable interrupts */
  757. iowrite32(0, base + ATAPI_INT_ENABLE_REG);
  758. /* ack and mask */
  759. iowrite32(0, base + SATAINTSTAT_REG);
  760. iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
  761. pm_runtime_put(&pdev->dev);
  762. pm_runtime_disable(&pdev->dev);
  763. return 0;
  764. }
  765. #ifdef CONFIG_PM_SLEEP
  766. static int sata_rcar_suspend(struct device *dev)
  767. {
  768. struct ata_host *host = dev_get_drvdata(dev);
  769. struct sata_rcar_priv *priv = host->private_data;
  770. void __iomem *base = priv->base;
  771. ata_host_suspend(host, PMSG_SUSPEND);
  772. /* disable interrupts */
  773. iowrite32(0, base + ATAPI_INT_ENABLE_REG);
  774. /* mask */
  775. iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
  776. pm_runtime_put(dev);
  777. return 0;
  778. }
  779. static int sata_rcar_resume(struct device *dev)
  780. {
  781. struct ata_host *host = dev_get_drvdata(dev);
  782. struct sata_rcar_priv *priv = host->private_data;
  783. void __iomem *base = priv->base;
  784. int ret;
  785. ret = pm_runtime_get_sync(dev);
  786. if (ret < 0) {
  787. pm_runtime_put(dev);
  788. return ret;
  789. }
  790. if (priv->type == RCAR_GEN3_SATA) {
  791. sata_rcar_init_module(priv);
  792. } else {
  793. /* ack and mask */
  794. iowrite32(0, base + SATAINTSTAT_REG);
  795. iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
  796. /* enable interrupts */
  797. iowrite32(ATAPI_INT_ENABLE_SATAINT,
  798. base + ATAPI_INT_ENABLE_REG);
  799. }
  800. ata_host_resume(host);
  801. return 0;
  802. }
  803. static int sata_rcar_restore(struct device *dev)
  804. {
  805. struct ata_host *host = dev_get_drvdata(dev);
  806. int ret;
  807. ret = pm_runtime_get_sync(dev);
  808. if (ret < 0) {
  809. pm_runtime_put(dev);
  810. return ret;
  811. }
  812. sata_rcar_setup_port(host);
  813. /* initialize host controller */
  814. sata_rcar_init_controller(host);
  815. ata_host_resume(host);
  816. return 0;
  817. }
  818. static const struct dev_pm_ops sata_rcar_pm_ops = {
  819. .suspend = sata_rcar_suspend,
  820. .resume = sata_rcar_resume,
  821. .freeze = sata_rcar_suspend,
  822. .thaw = sata_rcar_resume,
  823. .poweroff = sata_rcar_suspend,
  824. .restore = sata_rcar_restore,
  825. };
  826. #endif
  827. static struct platform_driver sata_rcar_driver = {
  828. .probe = sata_rcar_probe,
  829. .remove = sata_rcar_remove,
  830. .driver = {
  831. .name = DRV_NAME,
  832. .of_match_table = sata_rcar_match,
  833. #ifdef CONFIG_PM_SLEEP
  834. .pm = &sata_rcar_pm_ops,
  835. #endif
  836. },
  837. };
  838. module_platform_driver(sata_rcar_driver);
  839. MODULE_LICENSE("GPL");
  840. MODULE_AUTHOR("Vladimir Barinov");
  841. MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");