sata_gemini.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010
  4. * Copyright (C) 2017 Linus Walleij <[email protected]>
  5. */
  6. #include <linux/init.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/bitops.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/regmap.h>
  12. #include <linux/delay.h>
  13. #include <linux/reset.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_device.h>
  16. #include <linux/clk.h>
  17. #include <linux/io.h>
  18. #include <linux/pinctrl/consumer.h>
  19. #include "sata_gemini.h"
  20. #define DRV_NAME "gemini_sata_bridge"
  21. /**
  22. * struct sata_gemini - a state container for a Gemini SATA bridge
  23. * @dev: the containing device
  24. * @base: remapped I/O memory base
  25. * @muxmode: the current muxing mode
  26. * @ide_pins: if the device is using the plain IDE interface pins
  27. * @sata_bridge: if the device enables the SATA bridge
  28. * @sata0_reset: SATA0 reset handler
  29. * @sata1_reset: SATA1 reset handler
  30. * @sata0_pclk: SATA0 PCLK handler
  31. * @sata1_pclk: SATA1 PCLK handler
  32. */
  33. struct sata_gemini {
  34. struct device *dev;
  35. void __iomem *base;
  36. enum gemini_muxmode muxmode;
  37. bool ide_pins;
  38. bool sata_bridge;
  39. struct reset_control *sata0_reset;
  40. struct reset_control *sata1_reset;
  41. struct clk *sata0_pclk;
  42. struct clk *sata1_pclk;
  43. };
  44. /* Miscellaneous Control Register */
  45. #define GEMINI_GLOBAL_MISC_CTRL 0x30
  46. /*
  47. * Values of IDE IOMUX bits in the misc control register
  48. *
  49. * Bits 26:24 are "IDE IO Select", which decides what SATA
  50. * adapters are connected to which of the two IDE/ATA
  51. * controllers in the Gemini. We can connect the two IDE blocks
  52. * to one SATA adapter each, both acting as master, or one IDE
  53. * blocks to two SATA adapters so the IDE block can act in a
  54. * master/slave configuration.
  55. *
  56. * We also bring out different blocks on the actual IDE
  57. * pins (not SATA pins) if (and only if) these are muxed in.
  58. *
  59. * 111-100 - Reserved
  60. * Mode 0: 000 - ata0 master <-> sata0
  61. * ata1 master <-> sata1
  62. * ata0 slave interface brought out on IDE pads
  63. * Mode 1: 001 - ata0 master <-> sata0
  64. * ata1 master <-> sata1
  65. * ata1 slave interface brought out on IDE pads
  66. * Mode 2: 010 - ata1 master <-> sata1
  67. * ata1 slave <-> sata0
  68. * ata0 master and slave interfaces brought out
  69. * on IDE pads
  70. * Mode 3: 011 - ata0 master <-> sata0
  71. * ata1 slave <-> sata1
  72. * ata1 master and slave interfaces brought out
  73. * on IDE pads
  74. */
  75. #define GEMINI_IDE_IOMUX_MASK (7 << 24)
  76. #define GEMINI_IDE_IOMUX_MODE0 (0 << 24)
  77. #define GEMINI_IDE_IOMUX_MODE1 (1 << 24)
  78. #define GEMINI_IDE_IOMUX_MODE2 (2 << 24)
  79. #define GEMINI_IDE_IOMUX_MODE3 (3 << 24)
  80. #define GEMINI_IDE_IOMUX_SHIFT (24)
  81. /*
  82. * Registers directly controlling the PATA<->SATA adapters
  83. */
  84. #define GEMINI_SATA_ID 0x00
  85. #define GEMINI_SATA_PHY_ID 0x04
  86. #define GEMINI_SATA0_STATUS 0x08
  87. #define GEMINI_SATA1_STATUS 0x0c
  88. #define GEMINI_SATA0_CTRL 0x18
  89. #define GEMINI_SATA1_CTRL 0x1c
  90. #define GEMINI_SATA_STATUS_BIST_DONE BIT(5)
  91. #define GEMINI_SATA_STATUS_BIST_OK BIT(4)
  92. #define GEMINI_SATA_STATUS_PHY_READY BIT(0)
  93. #define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14)
  94. #define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13)
  95. #define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12)
  96. #define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10)
  97. #define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9)
  98. #define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4)
  99. #define GEMINI_SATA_CTRL_ATAPI_EN BIT(3)
  100. #define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2)
  101. #define GEMINI_SATA_CTRL_SLAVE_EN BIT(1)
  102. #define GEMINI_SATA_CTRL_EN BIT(0)
  103. /*
  104. * There is only ever one instance of this bridge on a system,
  105. * so create a singleton so that the FTIDE010 instances can grab
  106. * a reference to it.
  107. */
  108. static struct sata_gemini *sg_singleton;
  109. struct sata_gemini *gemini_sata_bridge_get(void)
  110. {
  111. if (sg_singleton)
  112. return sg_singleton;
  113. return ERR_PTR(-EPROBE_DEFER);
  114. }
  115. EXPORT_SYMBOL(gemini_sata_bridge_get);
  116. bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1)
  117. {
  118. if (!sg->sata_bridge)
  119. return false;
  120. /*
  121. * In muxmode 2 and 3 one of the ATA controllers is
  122. * actually not connected to any SATA bridge.
  123. */
  124. if ((sg->muxmode == GEMINI_MUXMODE_2) &&
  125. !is_ata1)
  126. return false;
  127. if ((sg->muxmode == GEMINI_MUXMODE_3) &&
  128. is_ata1)
  129. return false;
  130. return true;
  131. }
  132. EXPORT_SYMBOL(gemini_sata_bridge_enabled);
  133. enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg)
  134. {
  135. return sg->muxmode;
  136. }
  137. EXPORT_SYMBOL(gemini_sata_get_muxmode);
  138. static int gemini_sata_setup_bridge(struct sata_gemini *sg,
  139. unsigned int bridge)
  140. {
  141. unsigned long timeout = jiffies + (HZ * 1);
  142. bool bridge_online;
  143. u32 val;
  144. if (bridge == 0) {
  145. val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN;
  146. /* SATA0 slave mode is only used in muxmode 2 */
  147. if (sg->muxmode == GEMINI_MUXMODE_2)
  148. val |= GEMINI_SATA_CTRL_SLAVE_EN;
  149. writel(val, sg->base + GEMINI_SATA0_CTRL);
  150. } else {
  151. val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN;
  152. /* SATA1 slave mode is only used in muxmode 3 */
  153. if (sg->muxmode == GEMINI_MUXMODE_3)
  154. val |= GEMINI_SATA_CTRL_SLAVE_EN;
  155. writel(val, sg->base + GEMINI_SATA1_CTRL);
  156. }
  157. /* Vendor code waits 10 ms here */
  158. msleep(10);
  159. /* Wait for PHY to become ready */
  160. do {
  161. msleep(100);
  162. if (bridge == 0)
  163. val = readl(sg->base + GEMINI_SATA0_STATUS);
  164. else
  165. val = readl(sg->base + GEMINI_SATA1_STATUS);
  166. if (val & GEMINI_SATA_STATUS_PHY_READY)
  167. break;
  168. } while (time_before(jiffies, timeout));
  169. bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY);
  170. dev_info(sg->dev, "SATA%d PHY %s\n", bridge,
  171. bridge_online ? "ready" : "not ready");
  172. return bridge_online ? 0: -ENODEV;
  173. }
  174. int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge)
  175. {
  176. struct clk *pclk;
  177. int ret;
  178. if (bridge == 0)
  179. pclk = sg->sata0_pclk;
  180. else
  181. pclk = sg->sata1_pclk;
  182. clk_enable(pclk);
  183. msleep(10);
  184. /* Do not keep clocking a bridge that is not online */
  185. ret = gemini_sata_setup_bridge(sg, bridge);
  186. if (ret)
  187. clk_disable(pclk);
  188. return ret;
  189. }
  190. EXPORT_SYMBOL(gemini_sata_start_bridge);
  191. void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge)
  192. {
  193. if (bridge == 0)
  194. clk_disable(sg->sata0_pclk);
  195. else if (bridge == 1)
  196. clk_disable(sg->sata1_pclk);
  197. }
  198. EXPORT_SYMBOL(gemini_sata_stop_bridge);
  199. int gemini_sata_reset_bridge(struct sata_gemini *sg,
  200. unsigned int bridge)
  201. {
  202. if (bridge == 0)
  203. reset_control_reset(sg->sata0_reset);
  204. else
  205. reset_control_reset(sg->sata1_reset);
  206. msleep(10);
  207. return gemini_sata_setup_bridge(sg, bridge);
  208. }
  209. EXPORT_SYMBOL(gemini_sata_reset_bridge);
  210. static int gemini_sata_bridge_init(struct sata_gemini *sg)
  211. {
  212. struct device *dev = sg->dev;
  213. u32 sata_id, sata_phy_id;
  214. int ret;
  215. sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK");
  216. if (IS_ERR(sg->sata0_pclk)) {
  217. dev_err(dev, "no SATA0 PCLK");
  218. return -ENODEV;
  219. }
  220. sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK");
  221. if (IS_ERR(sg->sata1_pclk)) {
  222. dev_err(dev, "no SATA1 PCLK");
  223. return -ENODEV;
  224. }
  225. ret = clk_prepare_enable(sg->sata0_pclk);
  226. if (ret) {
  227. dev_err(dev, "failed to enable SATA0 PCLK\n");
  228. return ret;
  229. }
  230. ret = clk_prepare_enable(sg->sata1_pclk);
  231. if (ret) {
  232. dev_err(dev, "failed to enable SATA1 PCLK\n");
  233. clk_disable_unprepare(sg->sata0_pclk);
  234. return ret;
  235. }
  236. sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
  237. if (IS_ERR(sg->sata0_reset)) {
  238. dev_err(dev, "no SATA0 reset controller\n");
  239. clk_disable_unprepare(sg->sata1_pclk);
  240. clk_disable_unprepare(sg->sata0_pclk);
  241. return PTR_ERR(sg->sata0_reset);
  242. }
  243. sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
  244. if (IS_ERR(sg->sata1_reset)) {
  245. dev_err(dev, "no SATA1 reset controller\n");
  246. clk_disable_unprepare(sg->sata1_pclk);
  247. clk_disable_unprepare(sg->sata0_pclk);
  248. return PTR_ERR(sg->sata1_reset);
  249. }
  250. sata_id = readl(sg->base + GEMINI_SATA_ID);
  251. sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
  252. sg->sata_bridge = true;
  253. clk_disable(sg->sata0_pclk);
  254. clk_disable(sg->sata1_pclk);
  255. dev_info(dev, "SATA ID %08x, PHY ID: %08x\n", sata_id, sata_phy_id);
  256. return 0;
  257. }
  258. static int gemini_setup_ide_pins(struct device *dev)
  259. {
  260. struct pinctrl *p;
  261. struct pinctrl_state *ide_state;
  262. int ret;
  263. p = devm_pinctrl_get(dev);
  264. if (IS_ERR(p))
  265. return PTR_ERR(p);
  266. ide_state = pinctrl_lookup_state(p, "ide");
  267. if (IS_ERR(ide_state))
  268. return PTR_ERR(ide_state);
  269. ret = pinctrl_select_state(p, ide_state);
  270. if (ret) {
  271. dev_err(dev, "could not select IDE state\n");
  272. return ret;
  273. }
  274. return 0;
  275. }
  276. static int gemini_sata_probe(struct platform_device *pdev)
  277. {
  278. struct device *dev = &pdev->dev;
  279. struct device_node *np = dev->of_node;
  280. struct sata_gemini *sg;
  281. struct regmap *map;
  282. enum gemini_muxmode muxmode;
  283. u32 gmode;
  284. u32 gmask;
  285. int ret;
  286. sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
  287. if (!sg)
  288. return -ENOMEM;
  289. sg->dev = dev;
  290. sg->base = devm_platform_ioremap_resource(pdev, 0);
  291. if (IS_ERR(sg->base))
  292. return PTR_ERR(sg->base);
  293. map = syscon_regmap_lookup_by_phandle(np, "syscon");
  294. if (IS_ERR(map)) {
  295. dev_err(dev, "no global syscon\n");
  296. return PTR_ERR(map);
  297. }
  298. /* Set up the SATA bridge if need be */
  299. if (of_property_read_bool(np, "cortina,gemini-enable-sata-bridge")) {
  300. ret = gemini_sata_bridge_init(sg);
  301. if (ret)
  302. return ret;
  303. }
  304. if (of_property_read_bool(np, "cortina,gemini-enable-ide-pins"))
  305. sg->ide_pins = true;
  306. if (!sg->sata_bridge && !sg->ide_pins) {
  307. dev_err(dev, "neither SATA bridge or IDE output enabled\n");
  308. ret = -EINVAL;
  309. goto out_unprep_clk;
  310. }
  311. ret = of_property_read_u32(np, "cortina,gemini-ata-muxmode", &muxmode);
  312. if (ret) {
  313. dev_err(dev, "could not parse ATA muxmode\n");
  314. goto out_unprep_clk;
  315. }
  316. if (muxmode > GEMINI_MUXMODE_3) {
  317. dev_err(dev, "illegal muxmode %d\n", muxmode);
  318. ret = -EINVAL;
  319. goto out_unprep_clk;
  320. }
  321. sg->muxmode = muxmode;
  322. gmask = GEMINI_IDE_IOMUX_MASK;
  323. gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT);
  324. ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, gmask, gmode);
  325. if (ret) {
  326. dev_err(dev, "unable to set up IDE muxing\n");
  327. ret = -ENODEV;
  328. goto out_unprep_clk;
  329. }
  330. /*
  331. * Route out the IDE pins if desired.
  332. * This is done by looking up a special pin control state called
  333. * "ide" that will route out the IDE pins.
  334. */
  335. if (sg->ide_pins) {
  336. ret = gemini_setup_ide_pins(dev);
  337. if (ret)
  338. return ret;
  339. }
  340. dev_info(dev, "set up the Gemini IDE/SATA nexus\n");
  341. platform_set_drvdata(pdev, sg);
  342. sg_singleton = sg;
  343. return 0;
  344. out_unprep_clk:
  345. if (sg->sata_bridge) {
  346. clk_unprepare(sg->sata1_pclk);
  347. clk_unprepare(sg->sata0_pclk);
  348. }
  349. return ret;
  350. }
  351. static int gemini_sata_remove(struct platform_device *pdev)
  352. {
  353. struct sata_gemini *sg = platform_get_drvdata(pdev);
  354. if (sg->sata_bridge) {
  355. clk_unprepare(sg->sata1_pclk);
  356. clk_unprepare(sg->sata0_pclk);
  357. }
  358. sg_singleton = NULL;
  359. return 0;
  360. }
  361. static const struct of_device_id gemini_sata_of_match[] = {
  362. { .compatible = "cortina,gemini-sata-bridge", },
  363. { /* sentinel */ }
  364. };
  365. static struct platform_driver gemini_sata_driver = {
  366. .driver = {
  367. .name = DRV_NAME,
  368. .of_match_table = of_match_ptr(gemini_sata_of_match),
  369. },
  370. .probe = gemini_sata_probe,
  371. .remove = gemini_sata_remove,
  372. };
  373. module_platform_driver(gemini_sata_driver);
  374. MODULE_DESCRIPTION("low level driver for Cortina Systems Gemini SATA bridge");
  375. MODULE_AUTHOR("Linus Walleij <[email protected]>");
  376. MODULE_LICENSE("GPL");
  377. MODULE_ALIAS("platform:" DRV_NAME);