pata_macio.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Libata based driver for Apple "macio" family of PATA controllers
  4. *
  5. * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
  6. * <[email protected]>
  7. *
  8. * Some bits and pieces from drivers/ide/ppc/pmac.c
  9. *
  10. */
  11. #undef DEBUG
  12. #undef DEBUG_DMA
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/blkdev.h>
  17. #include <linux/ata.h>
  18. #include <linux/libata.h>
  19. #include <linux/adb.h>
  20. #include <linux/pmu.h>
  21. #include <linux/scatterlist.h>
  22. #include <linux/of.h>
  23. #include <linux/gfp.h>
  24. #include <linux/pci.h>
  25. #include <scsi/scsi.h>
  26. #include <scsi/scsi_host.h>
  27. #include <scsi/scsi_device.h>
  28. #include <asm/macio.h>
  29. #include <asm/io.h>
  30. #include <asm/dbdma.h>
  31. #include <asm/machdep.h>
  32. #include <asm/pmac_feature.h>
  33. #include <asm/mediabay.h>
  34. #ifdef DEBUG_DMA
  35. #define dev_dbgdma(dev, format, arg...) \
  36. dev_printk(KERN_DEBUG , dev , format , ## arg)
  37. #else
  38. #define dev_dbgdma(dev, format, arg...) \
  39. ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
  40. #endif
  41. #define DRV_NAME "pata_macio"
  42. #define DRV_VERSION "0.9"
  43. /* Models of macio ATA controller */
  44. enum {
  45. controller_ohare, /* OHare based */
  46. controller_heathrow, /* Heathrow/Paddington */
  47. controller_kl_ata3, /* KeyLargo ATA-3 */
  48. controller_kl_ata4, /* KeyLargo ATA-4 */
  49. controller_un_ata6, /* UniNorth2 ATA-6 */
  50. controller_k2_ata6, /* K2 ATA-6 */
  51. controller_sh_ata6, /* Shasta ATA-6 */
  52. };
  53. static const char* macio_ata_names[] = {
  54. "OHare ATA", /* OHare based */
  55. "Heathrow ATA", /* Heathrow/Paddington */
  56. "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
  57. "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
  58. "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
  59. "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
  60. "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
  61. };
  62. /*
  63. * Extra registers, both 32-bit little-endian
  64. */
  65. #define IDE_TIMING_CONFIG 0x200
  66. #define IDE_INTERRUPT 0x300
  67. /* Kauai (U2) ATA has different register setup */
  68. #define IDE_KAUAI_PIO_CONFIG 0x200
  69. #define IDE_KAUAI_ULTRA_CONFIG 0x210
  70. #define IDE_KAUAI_POLL_CONFIG 0x220
  71. /*
  72. * Timing configuration register definitions
  73. */
  74. /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
  75. #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
  76. #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
  77. #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
  78. #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
  79. /* 133Mhz cell, found in shasta.
  80. * See comments about 100 Mhz Uninorth 2...
  81. * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
  82. * weird and I don't now why .. at this stage
  83. */
  84. #define TR_133_PIOREG_PIO_MASK 0xff000fff
  85. #define TR_133_PIOREG_MDMA_MASK 0x00fff800
  86. #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
  87. #define TR_133_UDMAREG_UDMA_EN 0x00000001
  88. /* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
  89. * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
  90. * controlled like gem or fw. It appears to be an evolution of keylargo
  91. * ATA4 with a timing register extended to 2x32bits registers (one
  92. * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
  93. * It has it's own local feature control register as well.
  94. *
  95. * After scratching my mind over the timing values, at least for PIO
  96. * and MDMA, I think I've figured the format of the timing register,
  97. * though I use pre-calculated tables for UDMA as usual...
  98. */
  99. #define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
  100. #define TR_100_PIO_ADDRSETUP_SHIFT 24
  101. #define TR_100_MDMA_MASK 0x00fff000
  102. #define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
  103. #define TR_100_MDMA_RECOVERY_SHIFT 18
  104. #define TR_100_MDMA_ACCESS_MASK 0x0003f000
  105. #define TR_100_MDMA_ACCESS_SHIFT 12
  106. #define TR_100_PIO_MASK 0xff000fff
  107. #define TR_100_PIO_RECOVERY_MASK 0x00000fc0
  108. #define TR_100_PIO_RECOVERY_SHIFT 6
  109. #define TR_100_PIO_ACCESS_MASK 0x0000003f
  110. #define TR_100_PIO_ACCESS_SHIFT 0
  111. #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
  112. #define TR_100_UDMAREG_UDMA_EN 0x00000001
  113. /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
  114. * 40 connector cable and to 4 on 80 connector one.
  115. * Clock unit is 15ns (66Mhz)
  116. *
  117. * 3 Values can be programmed:
  118. * - Write data setup, which appears to match the cycle time. They
  119. * also call it DIOW setup.
  120. * - Ready to pause time (from spec)
  121. * - Address setup. That one is weird. I don't see where exactly
  122. * it fits in UDMA cycles, I got it's name from an obscure piece
  123. * of commented out code in Darwin. They leave it to 0, we do as
  124. * well, despite a comment that would lead to think it has a
  125. * min value of 45ns.
  126. * Apple also add 60ns to the write data setup (or cycle time ?) on
  127. * reads.
  128. */
  129. #define TR_66_UDMA_MASK 0xfff00000
  130. #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
  131. #define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
  132. #define TR_66_PIO_ADDRSETUP_SHIFT 29
  133. #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
  134. #define TR_66_UDMA_RDY2PAUS_SHIFT 25
  135. #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
  136. #define TR_66_UDMA_WRDATASETUP_SHIFT 21
  137. #define TR_66_MDMA_MASK 0x000ffc00
  138. #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
  139. #define TR_66_MDMA_RECOVERY_SHIFT 15
  140. #define TR_66_MDMA_ACCESS_MASK 0x00007c00
  141. #define TR_66_MDMA_ACCESS_SHIFT 10
  142. #define TR_66_PIO_MASK 0xe00003ff
  143. #define TR_66_PIO_RECOVERY_MASK 0x000003e0
  144. #define TR_66_PIO_RECOVERY_SHIFT 5
  145. #define TR_66_PIO_ACCESS_MASK 0x0000001f
  146. #define TR_66_PIO_ACCESS_SHIFT 0
  147. /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
  148. * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
  149. *
  150. * The access time and recovery time can be programmed. Some older
  151. * Darwin code base limit OHare to 150ns cycle time. I decided to do
  152. * the same here fore safety against broken old hardware ;)
  153. * The HalfTick bit, when set, adds half a clock (15ns) to the access
  154. * time and removes one from recovery. It's not supported on KeyLargo
  155. * implementation afaik. The E bit appears to be set for PIO mode 0 and
  156. * is used to reach long timings used in this mode.
  157. */
  158. #define TR_33_MDMA_MASK 0x003ff800
  159. #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
  160. #define TR_33_MDMA_RECOVERY_SHIFT 16
  161. #define TR_33_MDMA_ACCESS_MASK 0x0000f800
  162. #define TR_33_MDMA_ACCESS_SHIFT 11
  163. #define TR_33_MDMA_HALFTICK 0x00200000
  164. #define TR_33_PIO_MASK 0x000007ff
  165. #define TR_33_PIO_E 0x00000400
  166. #define TR_33_PIO_RECOVERY_MASK 0x000003e0
  167. #define TR_33_PIO_RECOVERY_SHIFT 5
  168. #define TR_33_PIO_ACCESS_MASK 0x0000001f
  169. #define TR_33_PIO_ACCESS_SHIFT 0
  170. /*
  171. * Interrupt register definitions. Only present on newer cells
  172. * (Keylargo and later afaik) so we don't use it.
  173. */
  174. #define IDE_INTR_DMA 0x80000000
  175. #define IDE_INTR_DEVICE 0x40000000
  176. /*
  177. * FCR Register on Kauai. Not sure what bit 0x4 is ...
  178. */
  179. #define KAUAI_FCR_UATA_MAGIC 0x00000004
  180. #define KAUAI_FCR_UATA_RESET_N 0x00000002
  181. #define KAUAI_FCR_UATA_ENABLE 0x00000001
  182. /* Allow up to 256 DBDMA commands per xfer */
  183. #define MAX_DCMDS 256
  184. /* Don't let a DMA segment go all the way to 64K */
  185. #define MAX_DBDMA_SEG 0xff00
  186. /*
  187. * Wait 1s for disk to answer on IDE bus after a hard reset
  188. * of the device (via GPIO/FCR).
  189. *
  190. * Some devices seem to "pollute" the bus even after dropping
  191. * the BSY bit (typically some combo drives slave on the UDMA
  192. * bus) after a hard reset. Since we hard reset all drives on
  193. * KeyLargo ATA66, we have to keep that delay around. I may end
  194. * up not hard resetting anymore on these and keep the delay only
  195. * for older interfaces instead (we have to reset when coming
  196. * from MacOS...) --BenH.
  197. */
  198. #define IDE_WAKEUP_DELAY_MS 1000
  199. struct pata_macio_timing;
  200. struct pata_macio_priv {
  201. int kind;
  202. int aapl_bus_id;
  203. int mediabay : 1;
  204. struct device_node *node;
  205. struct macio_dev *mdev;
  206. struct pci_dev *pdev;
  207. struct device *dev;
  208. int irq;
  209. u32 treg[2][2];
  210. void __iomem *tfregs;
  211. void __iomem *kauai_fcr;
  212. struct dbdma_cmd * dma_table_cpu;
  213. dma_addr_t dma_table_dma;
  214. struct ata_host *host;
  215. const struct pata_macio_timing *timings;
  216. };
  217. /* Previous variants of this driver used to calculate timings
  218. * for various variants of the chip and use tables for others.
  219. *
  220. * Not only was this confusing, but in addition, it isn't clear
  221. * whether our calculation code was correct. It didn't entirely
  222. * match the darwin code and whatever documentation I could find
  223. * on these cells
  224. *
  225. * I decided to entirely rely on a table instead for this version
  226. * of the driver. Also, because I don't really care about derated
  227. * modes and really old HW other than making it work, I'm not going
  228. * to calculate / snoop timing values for something else than the
  229. * standard modes.
  230. */
  231. struct pata_macio_timing {
  232. int mode;
  233. u32 reg1; /* Bits to set in first timing reg */
  234. u32 reg2; /* Bits to set in second timing reg */
  235. };
  236. static const struct pata_macio_timing pata_macio_ohare_timings[] = {
  237. { XFER_PIO_0, 0x00000526, 0, },
  238. { XFER_PIO_1, 0x00000085, 0, },
  239. { XFER_PIO_2, 0x00000025, 0, },
  240. { XFER_PIO_3, 0x00000025, 0, },
  241. { XFER_PIO_4, 0x00000025, 0, },
  242. { XFER_MW_DMA_0, 0x00074000, 0, },
  243. { XFER_MW_DMA_1, 0x00221000, 0, },
  244. { XFER_MW_DMA_2, 0x00211000, 0, },
  245. { -1, 0, 0 }
  246. };
  247. static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
  248. { XFER_PIO_0, 0x00000526, 0, },
  249. { XFER_PIO_1, 0x00000085, 0, },
  250. { XFER_PIO_2, 0x00000025, 0, },
  251. { XFER_PIO_3, 0x00000025, 0, },
  252. { XFER_PIO_4, 0x00000025, 0, },
  253. { XFER_MW_DMA_0, 0x00074000, 0, },
  254. { XFER_MW_DMA_1, 0x00221000, 0, },
  255. { XFER_MW_DMA_2, 0x00211000, 0, },
  256. { -1, 0, 0 }
  257. };
  258. static const struct pata_macio_timing pata_macio_kl33_timings[] = {
  259. { XFER_PIO_0, 0x00000526, 0, },
  260. { XFER_PIO_1, 0x00000085, 0, },
  261. { XFER_PIO_2, 0x00000025, 0, },
  262. { XFER_PIO_3, 0x00000025, 0, },
  263. { XFER_PIO_4, 0x00000025, 0, },
  264. { XFER_MW_DMA_0, 0x00084000, 0, },
  265. { XFER_MW_DMA_1, 0x00021800, 0, },
  266. { XFER_MW_DMA_2, 0x00011800, 0, },
  267. { -1, 0, 0 }
  268. };
  269. static const struct pata_macio_timing pata_macio_kl66_timings[] = {
  270. { XFER_PIO_0, 0x0000038c, 0, },
  271. { XFER_PIO_1, 0x0000020a, 0, },
  272. { XFER_PIO_2, 0x00000127, 0, },
  273. { XFER_PIO_3, 0x000000c6, 0, },
  274. { XFER_PIO_4, 0x00000065, 0, },
  275. { XFER_MW_DMA_0, 0x00084000, 0, },
  276. { XFER_MW_DMA_1, 0x00029800, 0, },
  277. { XFER_MW_DMA_2, 0x00019400, 0, },
  278. { XFER_UDMA_0, 0x19100000, 0, },
  279. { XFER_UDMA_1, 0x14d00000, 0, },
  280. { XFER_UDMA_2, 0x10900000, 0, },
  281. { XFER_UDMA_3, 0x0c700000, 0, },
  282. { XFER_UDMA_4, 0x0c500000, 0, },
  283. { -1, 0, 0 }
  284. };
  285. static const struct pata_macio_timing pata_macio_kauai_timings[] = {
  286. { XFER_PIO_0, 0x08000a92, 0, },
  287. { XFER_PIO_1, 0x0800060f, 0, },
  288. { XFER_PIO_2, 0x0800038b, 0, },
  289. { XFER_PIO_3, 0x05000249, 0, },
  290. { XFER_PIO_4, 0x04000148, 0, },
  291. { XFER_MW_DMA_0, 0x00618000, 0, },
  292. { XFER_MW_DMA_1, 0x00209000, 0, },
  293. { XFER_MW_DMA_2, 0x00148000, 0, },
  294. { XFER_UDMA_0, 0, 0x000070c1, },
  295. { XFER_UDMA_1, 0, 0x00005d81, },
  296. { XFER_UDMA_2, 0, 0x00004a61, },
  297. { XFER_UDMA_3, 0, 0x00003a51, },
  298. { XFER_UDMA_4, 0, 0x00002a31, },
  299. { XFER_UDMA_5, 0, 0x00002921, },
  300. { -1, 0, 0 }
  301. };
  302. static const struct pata_macio_timing pata_macio_shasta_timings[] = {
  303. { XFER_PIO_0, 0x0a000c97, 0, },
  304. { XFER_PIO_1, 0x07000712, 0, },
  305. { XFER_PIO_2, 0x040003cd, 0, },
  306. { XFER_PIO_3, 0x0500028b, 0, },
  307. { XFER_PIO_4, 0x0400010a, 0, },
  308. { XFER_MW_DMA_0, 0x00820800, 0, },
  309. { XFER_MW_DMA_1, 0x0028b000, 0, },
  310. { XFER_MW_DMA_2, 0x001ca000, 0, },
  311. { XFER_UDMA_0, 0, 0x00035901, },
  312. { XFER_UDMA_1, 0, 0x000348b1, },
  313. { XFER_UDMA_2, 0, 0x00033881, },
  314. { XFER_UDMA_3, 0, 0x00033861, },
  315. { XFER_UDMA_4, 0, 0x00033841, },
  316. { XFER_UDMA_5, 0, 0x00033031, },
  317. { XFER_UDMA_6, 0, 0x00033021, },
  318. { -1, 0, 0 }
  319. };
  320. static const struct pata_macio_timing *pata_macio_find_timing(
  321. struct pata_macio_priv *priv,
  322. int mode)
  323. {
  324. int i;
  325. for (i = 0; priv->timings[i].mode > 0; i++) {
  326. if (priv->timings[i].mode == mode)
  327. return &priv->timings[i];
  328. }
  329. return NULL;
  330. }
  331. static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
  332. {
  333. struct pata_macio_priv *priv = ap->private_data;
  334. void __iomem *rbase = ap->ioaddr.cmd_addr;
  335. if (priv->kind == controller_sh_ata6 ||
  336. priv->kind == controller_un_ata6 ||
  337. priv->kind == controller_k2_ata6) {
  338. writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
  339. writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
  340. } else
  341. writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
  342. }
  343. static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
  344. {
  345. ata_sff_dev_select(ap, device);
  346. /* Apply timings */
  347. pata_macio_apply_timings(ap, device);
  348. }
  349. static void pata_macio_set_timings(struct ata_port *ap,
  350. struct ata_device *adev)
  351. {
  352. struct pata_macio_priv *priv = ap->private_data;
  353. const struct pata_macio_timing *t;
  354. dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
  355. adev->devno,
  356. adev->pio_mode,
  357. ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
  358. adev->dma_mode,
  359. ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
  360. /* First clear timings */
  361. priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
  362. /* Now get the PIO timings */
  363. t = pata_macio_find_timing(priv, adev->pio_mode);
  364. if (t == NULL) {
  365. dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
  366. adev->pio_mode);
  367. t = pata_macio_find_timing(priv, XFER_PIO_0);
  368. }
  369. BUG_ON(t == NULL);
  370. /* PIO timings only ever use the first treg */
  371. priv->treg[adev->devno][0] |= t->reg1;
  372. /* Now get DMA timings */
  373. t = pata_macio_find_timing(priv, adev->dma_mode);
  374. if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
  375. dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
  376. t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
  377. }
  378. BUG_ON(t == NULL);
  379. /* DMA timings can use both tregs */
  380. priv->treg[adev->devno][0] |= t->reg1;
  381. priv->treg[adev->devno][1] |= t->reg2;
  382. dev_dbg(priv->dev, " -> %08x %08x\n",
  383. priv->treg[adev->devno][0],
  384. priv->treg[adev->devno][1]);
  385. /* Apply to hardware */
  386. pata_macio_apply_timings(ap, adev->devno);
  387. }
  388. /*
  389. * Blast some well known "safe" values to the timing registers at init or
  390. * wakeup from sleep time, before we do real calculation
  391. */
  392. static void pata_macio_default_timings(struct pata_macio_priv *priv)
  393. {
  394. unsigned int value, value2 = 0;
  395. switch(priv->kind) {
  396. case controller_sh_ata6:
  397. value = 0x0a820c97;
  398. value2 = 0x00033031;
  399. break;
  400. case controller_un_ata6:
  401. case controller_k2_ata6:
  402. value = 0x08618a92;
  403. value2 = 0x00002921;
  404. break;
  405. case controller_kl_ata4:
  406. value = 0x0008438c;
  407. break;
  408. case controller_kl_ata3:
  409. value = 0x00084526;
  410. break;
  411. case controller_heathrow:
  412. case controller_ohare:
  413. default:
  414. value = 0x00074526;
  415. break;
  416. }
  417. priv->treg[0][0] = priv->treg[1][0] = value;
  418. priv->treg[0][1] = priv->treg[1][1] = value2;
  419. }
  420. static int pata_macio_cable_detect(struct ata_port *ap)
  421. {
  422. struct pata_macio_priv *priv = ap->private_data;
  423. /* Get cable type from device-tree */
  424. if (priv->kind == controller_kl_ata4 ||
  425. priv->kind == controller_un_ata6 ||
  426. priv->kind == controller_k2_ata6 ||
  427. priv->kind == controller_sh_ata6) {
  428. const char* cable = of_get_property(priv->node, "cable-type",
  429. NULL);
  430. struct device_node *root = of_find_node_by_path("/");
  431. const char *model = of_get_property(root, "model", NULL);
  432. of_node_put(root);
  433. if (cable && !strncmp(cable, "80-", 3)) {
  434. /* Some drives fail to detect 80c cable in PowerBook
  435. * These machine use proprietary short IDE cable
  436. * anyway
  437. */
  438. if (!strncmp(model, "PowerBook", 9))
  439. return ATA_CBL_PATA40_SHORT;
  440. else
  441. return ATA_CBL_PATA80;
  442. }
  443. }
  444. /* G5's seem to have incorrect cable type in device-tree.
  445. * Let's assume they always have a 80 conductor cable, this seem to
  446. * be always the case unless the user mucked around
  447. */
  448. if (of_device_is_compatible(priv->node, "K2-UATA") ||
  449. of_device_is_compatible(priv->node, "shasta-ata"))
  450. return ATA_CBL_PATA80;
  451. /* Anything else is 40 connectors */
  452. return ATA_CBL_PATA40;
  453. }
  454. static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)
  455. {
  456. unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
  457. struct ata_port *ap = qc->ap;
  458. struct pata_macio_priv *priv = ap->private_data;
  459. struct scatterlist *sg;
  460. struct dbdma_cmd *table;
  461. unsigned int si, pi;
  462. dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
  463. __func__, qc, qc->flags, write, qc->dev->devno);
  464. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  465. return AC_ERR_OK;
  466. table = (struct dbdma_cmd *) priv->dma_table_cpu;
  467. pi = 0;
  468. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  469. u32 addr, sg_len, len;
  470. /* determine if physical DMA addr spans 64K boundary.
  471. * Note h/w doesn't support 64-bit, so we unconditionally
  472. * truncate dma_addr_t to u32.
  473. */
  474. addr = (u32) sg_dma_address(sg);
  475. sg_len = sg_dma_len(sg);
  476. while (sg_len) {
  477. /* table overflow should never happen */
  478. BUG_ON (pi++ >= MAX_DCMDS);
  479. len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
  480. table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);
  481. table->req_count = cpu_to_le16(len);
  482. table->phy_addr = cpu_to_le32(addr);
  483. table->cmd_dep = 0;
  484. table->xfer_status = 0;
  485. table->res_count = 0;
  486. addr += len;
  487. sg_len -= len;
  488. ++table;
  489. }
  490. }
  491. /* Should never happen according to Tejun */
  492. BUG_ON(!pi);
  493. /* Convert the last command to an input/output */
  494. table--;
  495. table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST);
  496. table++;
  497. /* Add the stop command to the end of the list */
  498. memset(table, 0, sizeof(struct dbdma_cmd));
  499. table->command = cpu_to_le16(DBDMA_STOP);
  500. dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
  501. return AC_ERR_OK;
  502. }
  503. static void pata_macio_freeze(struct ata_port *ap)
  504. {
  505. struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
  506. if (dma_regs) {
  507. unsigned int timeout = 1000000;
  508. /* Make sure DMA controller is stopped */
  509. writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
  510. while (--timeout && (readl(&dma_regs->status) & RUN))
  511. udelay(1);
  512. }
  513. ata_sff_freeze(ap);
  514. }
  515. static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
  516. {
  517. struct ata_port *ap = qc->ap;
  518. struct pata_macio_priv *priv = ap->private_data;
  519. struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
  520. int dev = qc->dev->devno;
  521. dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
  522. /* Make sure DMA commands updates are visible */
  523. writel(priv->dma_table_dma, &dma_regs->cmdptr);
  524. /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
  525. * UDMA reads
  526. */
  527. if (priv->kind == controller_kl_ata4 &&
  528. (priv->treg[dev][0] & TR_66_UDMA_EN)) {
  529. void __iomem *rbase = ap->ioaddr.cmd_addr;
  530. u32 reg = priv->treg[dev][0];
  531. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  532. reg += 0x00800000;
  533. writel(reg, rbase + IDE_TIMING_CONFIG);
  534. }
  535. /* issue r/w command */
  536. ap->ops->sff_exec_command(ap, &qc->tf);
  537. }
  538. static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
  539. {
  540. struct ata_port *ap = qc->ap;
  541. struct pata_macio_priv *priv = ap->private_data;
  542. struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
  543. dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
  544. writel((RUN << 16) | RUN, &dma_regs->control);
  545. /* Make sure it gets to the controller right now */
  546. (void)readl(&dma_regs->control);
  547. }
  548. static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
  549. {
  550. struct ata_port *ap = qc->ap;
  551. struct pata_macio_priv *priv = ap->private_data;
  552. struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
  553. unsigned int timeout = 1000000;
  554. dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
  555. /* Stop the DMA engine and wait for it to full halt */
  556. writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
  557. while (--timeout && (readl(&dma_regs->status) & RUN))
  558. udelay(1);
  559. }
  560. static u8 pata_macio_bmdma_status(struct ata_port *ap)
  561. {
  562. struct pata_macio_priv *priv = ap->private_data;
  563. struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
  564. u32 dstat, rstat = ATA_DMA_INTR;
  565. unsigned long timeout = 0;
  566. dstat = readl(&dma_regs->status);
  567. dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
  568. /* We have two things to deal with here:
  569. *
  570. * - The dbdma won't stop if the command was started
  571. * but completed with an error without transferring all
  572. * datas. This happens when bad blocks are met during
  573. * a multi-block transfer.
  574. *
  575. * - The dbdma fifo hasn't yet finished flushing to
  576. * system memory when the disk interrupt occurs.
  577. */
  578. /* First check for errors */
  579. if ((dstat & (RUN|DEAD)) != RUN)
  580. rstat |= ATA_DMA_ERR;
  581. /* If ACTIVE is cleared, the STOP command has been hit and
  582. * the transfer is complete. If not, we have to flush the
  583. * channel.
  584. */
  585. if ((dstat & ACTIVE) == 0)
  586. return rstat;
  587. dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
  588. /* If dbdma didn't execute the STOP command yet, the
  589. * active bit is still set. We consider that we aren't
  590. * sharing interrupts (which is hopefully the case with
  591. * those controllers) and so we just try to flush the
  592. * channel for pending data in the fifo
  593. */
  594. udelay(1);
  595. writel((FLUSH << 16) | FLUSH, &dma_regs->control);
  596. for (;;) {
  597. udelay(1);
  598. dstat = readl(&dma_regs->status);
  599. if ((dstat & FLUSH) == 0)
  600. break;
  601. if (++timeout > 1000) {
  602. dev_warn(priv->dev, "timeout flushing DMA\n");
  603. rstat |= ATA_DMA_ERR;
  604. break;
  605. }
  606. }
  607. return rstat;
  608. }
  609. /* port_start is when we allocate the DMA command list */
  610. static int pata_macio_port_start(struct ata_port *ap)
  611. {
  612. struct pata_macio_priv *priv = ap->private_data;
  613. if (ap->ioaddr.bmdma_addr == NULL)
  614. return 0;
  615. /* Allocate space for the DBDMA commands.
  616. *
  617. * The +2 is +1 for the stop command and +1 to allow for
  618. * aligning the start address to a multiple of 16 bytes.
  619. */
  620. priv->dma_table_cpu =
  621. dmam_alloc_coherent(priv->dev,
  622. (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
  623. &priv->dma_table_dma, GFP_KERNEL);
  624. if (priv->dma_table_cpu == NULL) {
  625. dev_err(priv->dev, "Unable to allocate DMA command list\n");
  626. ap->ioaddr.bmdma_addr = NULL;
  627. ap->mwdma_mask = 0;
  628. ap->udma_mask = 0;
  629. }
  630. return 0;
  631. }
  632. static void pata_macio_irq_clear(struct ata_port *ap)
  633. {
  634. struct pata_macio_priv *priv = ap->private_data;
  635. /* Nothing to do here */
  636. dev_dbgdma(priv->dev, "%s\n", __func__);
  637. }
  638. static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
  639. {
  640. dev_dbg(priv->dev, "Enabling & resetting... \n");
  641. if (priv->mediabay)
  642. return;
  643. if (priv->kind == controller_ohare && !resume) {
  644. /* The code below is having trouble on some ohare machines
  645. * (timing related ?). Until I can put my hand on one of these
  646. * units, I keep the old way
  647. */
  648. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
  649. } else {
  650. int rc;
  651. /* Reset and enable controller */
  652. rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
  653. priv->node, priv->aapl_bus_id, 1);
  654. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
  655. priv->node, priv->aapl_bus_id, 1);
  656. msleep(10);
  657. /* Only bother waiting if there's a reset control */
  658. if (rc == 0) {
  659. ppc_md.feature_call(PMAC_FTR_IDE_RESET,
  660. priv->node, priv->aapl_bus_id, 0);
  661. msleep(IDE_WAKEUP_DELAY_MS);
  662. }
  663. }
  664. /* If resuming a PCI device, restore the config space here */
  665. if (priv->pdev && resume) {
  666. int rc;
  667. pci_restore_state(priv->pdev);
  668. rc = pcim_enable_device(priv->pdev);
  669. if (rc)
  670. dev_err(&priv->pdev->dev,
  671. "Failed to enable device after resume (%d)\n",
  672. rc);
  673. else
  674. pci_set_master(priv->pdev);
  675. }
  676. /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
  677. * seem necessary and speeds up the boot process
  678. */
  679. if (priv->kauai_fcr)
  680. writel(KAUAI_FCR_UATA_MAGIC |
  681. KAUAI_FCR_UATA_RESET_N |
  682. KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
  683. }
  684. /* Hook the standard slave config to fixup some HW related alignment
  685. * restrictions
  686. */
  687. static int pata_macio_slave_config(struct scsi_device *sdev)
  688. {
  689. struct ata_port *ap = ata_shost_to_port(sdev->host);
  690. struct pata_macio_priv *priv = ap->private_data;
  691. struct ata_device *dev;
  692. u16 cmd;
  693. int rc;
  694. /* First call original */
  695. rc = ata_scsi_slave_config(sdev);
  696. if (rc)
  697. return rc;
  698. /* This is lifted from sata_nv */
  699. dev = &ap->link.device[sdev->id];
  700. /* OHare has issues with non cache aligned DMA on some chipsets */
  701. if (priv->kind == controller_ohare) {
  702. blk_queue_update_dma_alignment(sdev->request_queue, 31);
  703. blk_queue_update_dma_pad(sdev->request_queue, 31);
  704. /* Tell the world about it */
  705. ata_dev_info(dev, "OHare alignment limits applied\n");
  706. return 0;
  707. }
  708. /* We only have issues with ATAPI */
  709. if (dev->class != ATA_DEV_ATAPI)
  710. return 0;
  711. /* Shasta and K2 seem to have "issues" with reads ... */
  712. if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
  713. /* Allright these are bad, apply restrictions */
  714. blk_queue_update_dma_alignment(sdev->request_queue, 15);
  715. blk_queue_update_dma_pad(sdev->request_queue, 15);
  716. /* We enable MWI and hack cache line size directly here, this
  717. * is specific to this chipset and not normal values, we happen
  718. * to somewhat know what we are doing here (which is basically
  719. * to do the same Apple does and pray they did not get it wrong :-)
  720. */
  721. BUG_ON(!priv->pdev);
  722. pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
  723. pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
  724. pci_write_config_word(priv->pdev, PCI_COMMAND,
  725. cmd | PCI_COMMAND_INVALIDATE);
  726. /* Tell the world about it */
  727. ata_dev_info(dev, "K2/Shasta alignment limits applied\n");
  728. }
  729. return 0;
  730. }
  731. #ifdef CONFIG_PM_SLEEP
  732. static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
  733. {
  734. /* First, core libata suspend to do most of the work */
  735. ata_host_suspend(priv->host, mesg);
  736. /* Restore to default timings */
  737. pata_macio_default_timings(priv);
  738. /* Mask interrupt. Not strictly necessary but old driver did
  739. * it and I'd rather not change that here */
  740. disable_irq(priv->irq);
  741. /* The media bay will handle itself just fine */
  742. if (priv->mediabay)
  743. return 0;
  744. /* Kauai has bus control FCRs directly here */
  745. if (priv->kauai_fcr) {
  746. u32 fcr = readl(priv->kauai_fcr);
  747. fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
  748. writel(fcr, priv->kauai_fcr);
  749. }
  750. /* For PCI, save state and disable DMA. No need to call
  751. * pci_set_power_state(), the HW doesn't do D states that
  752. * way, the platform code will take care of suspending the
  753. * ASIC properly
  754. */
  755. if (priv->pdev) {
  756. pci_save_state(priv->pdev);
  757. pci_disable_device(priv->pdev);
  758. }
  759. /* Disable the bus on older machines and the cell on kauai */
  760. ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
  761. priv->aapl_bus_id, 0);
  762. return 0;
  763. }
  764. static int pata_macio_do_resume(struct pata_macio_priv *priv)
  765. {
  766. /* Reset and re-enable the HW */
  767. pata_macio_reset_hw(priv, 1);
  768. /* Sanitize drive timings */
  769. pata_macio_apply_timings(priv->host->ports[0], 0);
  770. /* We want our IRQ back ! */
  771. enable_irq(priv->irq);
  772. /* Let the libata core take it from there */
  773. ata_host_resume(priv->host);
  774. return 0;
  775. }
  776. #endif /* CONFIG_PM_SLEEP */
  777. static struct scsi_host_template pata_macio_sht = {
  778. __ATA_BASE_SHT(DRV_NAME),
  779. .sg_tablesize = MAX_DCMDS,
  780. /* We may not need that strict one */
  781. .dma_boundary = ATA_DMA_BOUNDARY,
  782. /* Not sure what the real max is but we know it's less than 64K, let's
  783. * use 64K minus 256
  784. */
  785. .max_segment_size = MAX_DBDMA_SEG,
  786. .slave_configure = pata_macio_slave_config,
  787. .sdev_groups = ata_common_sdev_groups,
  788. .can_queue = ATA_DEF_QUEUE,
  789. .tag_alloc_policy = BLK_TAG_ALLOC_RR,
  790. };
  791. static struct ata_port_operations pata_macio_ops = {
  792. .inherits = &ata_bmdma_port_ops,
  793. .freeze = pata_macio_freeze,
  794. .set_piomode = pata_macio_set_timings,
  795. .set_dmamode = pata_macio_set_timings,
  796. .cable_detect = pata_macio_cable_detect,
  797. .sff_dev_select = pata_macio_dev_select,
  798. .qc_prep = pata_macio_qc_prep,
  799. .bmdma_setup = pata_macio_bmdma_setup,
  800. .bmdma_start = pata_macio_bmdma_start,
  801. .bmdma_stop = pata_macio_bmdma_stop,
  802. .bmdma_status = pata_macio_bmdma_status,
  803. .port_start = pata_macio_port_start,
  804. .sff_irq_clear = pata_macio_irq_clear,
  805. };
  806. static void pata_macio_invariants(struct pata_macio_priv *priv)
  807. {
  808. const int *bidp;
  809. /* Identify the type of controller */
  810. if (of_device_is_compatible(priv->node, "shasta-ata")) {
  811. priv->kind = controller_sh_ata6;
  812. priv->timings = pata_macio_shasta_timings;
  813. } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
  814. priv->kind = controller_un_ata6;
  815. priv->timings = pata_macio_kauai_timings;
  816. } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
  817. priv->kind = controller_k2_ata6;
  818. priv->timings = pata_macio_kauai_timings;
  819. } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
  820. if (of_node_name_eq(priv->node, "ata-4")) {
  821. priv->kind = controller_kl_ata4;
  822. priv->timings = pata_macio_kl66_timings;
  823. } else {
  824. priv->kind = controller_kl_ata3;
  825. priv->timings = pata_macio_kl33_timings;
  826. }
  827. } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
  828. priv->kind = controller_heathrow;
  829. priv->timings = pata_macio_heathrow_timings;
  830. } else {
  831. priv->kind = controller_ohare;
  832. priv->timings = pata_macio_ohare_timings;
  833. }
  834. /* XXX FIXME --- setup priv->mediabay here */
  835. /* Get Apple bus ID (for clock and ASIC control) */
  836. bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
  837. priv->aapl_bus_id = bidp ? *bidp : 0;
  838. /* Fixup missing Apple bus ID in case of media-bay */
  839. if (priv->mediabay && !bidp)
  840. priv->aapl_bus_id = 1;
  841. }
  842. static void pata_macio_setup_ios(struct ata_ioports *ioaddr,
  843. void __iomem * base, void __iomem * dma)
  844. {
  845. /* cmd_addr is the base of regs for that port */
  846. ioaddr->cmd_addr = base;
  847. /* taskfile registers */
  848. ioaddr->data_addr = base + (ATA_REG_DATA << 4);
  849. ioaddr->error_addr = base + (ATA_REG_ERR << 4);
  850. ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
  851. ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
  852. ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
  853. ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
  854. ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
  855. ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
  856. ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
  857. ioaddr->command_addr = base + (ATA_REG_CMD << 4);
  858. ioaddr->altstatus_addr = base + 0x160;
  859. ioaddr->ctl_addr = base + 0x160;
  860. ioaddr->bmdma_addr = dma;
  861. }
  862. static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
  863. struct ata_port_info *pinfo)
  864. {
  865. int i = 0;
  866. pinfo->pio_mask = 0;
  867. pinfo->mwdma_mask = 0;
  868. pinfo->udma_mask = 0;
  869. while (priv->timings[i].mode > 0) {
  870. unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
  871. switch(priv->timings[i].mode & 0xf0) {
  872. case 0x00: /* PIO */
  873. pinfo->pio_mask |= (mask >> 8);
  874. break;
  875. case 0x20: /* MWDMA */
  876. pinfo->mwdma_mask |= mask;
  877. break;
  878. case 0x40: /* UDMA */
  879. pinfo->udma_mask |= mask;
  880. break;
  881. }
  882. i++;
  883. }
  884. dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n",
  885. pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
  886. }
  887. static int pata_macio_common_init(struct pata_macio_priv *priv,
  888. resource_size_t tfregs,
  889. resource_size_t dmaregs,
  890. resource_size_t fcregs,
  891. unsigned long irq)
  892. {
  893. struct ata_port_info pinfo;
  894. const struct ata_port_info *ppi[] = { &pinfo, NULL };
  895. void __iomem *dma_regs = NULL;
  896. /* Fill up privates with various invariants collected from the
  897. * device-tree
  898. */
  899. pata_macio_invariants(priv);
  900. /* Make sure we have sane initial timings in the cache */
  901. pata_macio_default_timings(priv);
  902. /* Allocate libata host for 1 port */
  903. memset(&pinfo, 0, sizeof(struct ata_port_info));
  904. pmac_macio_calc_timing_masks(priv, &pinfo);
  905. pinfo.flags = ATA_FLAG_SLAVE_POSS;
  906. pinfo.port_ops = &pata_macio_ops;
  907. pinfo.private_data = priv;
  908. priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
  909. if (priv->host == NULL) {
  910. dev_err(priv->dev, "Failed to allocate ATA port structure\n");
  911. return -ENOMEM;
  912. }
  913. /* Setup the private data in host too */
  914. priv->host->private_data = priv;
  915. /* Map base registers */
  916. priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
  917. if (priv->tfregs == NULL) {
  918. dev_err(priv->dev, "Failed to map ATA ports\n");
  919. return -ENOMEM;
  920. }
  921. priv->host->iomap = &priv->tfregs;
  922. /* Map DMA regs */
  923. if (dmaregs != 0) {
  924. dma_regs = devm_ioremap(priv->dev, dmaregs,
  925. sizeof(struct dbdma_regs));
  926. if (dma_regs == NULL)
  927. dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
  928. }
  929. /* If chip has local feature control, map those regs too */
  930. if (fcregs != 0) {
  931. priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
  932. if (priv->kauai_fcr == NULL) {
  933. dev_err(priv->dev, "Failed to map ATA FCR register\n");
  934. return -ENOMEM;
  935. }
  936. }
  937. /* Setup port data structure */
  938. pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
  939. priv->tfregs, dma_regs);
  940. priv->host->ports[0]->private_data = priv;
  941. /* hard-reset the controller */
  942. pata_macio_reset_hw(priv, 0);
  943. pata_macio_apply_timings(priv->host->ports[0], 0);
  944. /* Enable bus master if necessary */
  945. if (priv->pdev && dma_regs)
  946. pci_set_master(priv->pdev);
  947. dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
  948. macio_ata_names[priv->kind], priv->aapl_bus_id);
  949. /* Start it up */
  950. priv->irq = irq;
  951. return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
  952. &pata_macio_sht);
  953. }
  954. static int pata_macio_attach(struct macio_dev *mdev,
  955. const struct of_device_id *match)
  956. {
  957. struct pata_macio_priv *priv;
  958. resource_size_t tfregs, dmaregs = 0;
  959. unsigned long irq;
  960. int rc;
  961. /* Check for broken device-trees */
  962. if (macio_resource_count(mdev) == 0) {
  963. dev_err(&mdev->ofdev.dev,
  964. "No addresses for controller\n");
  965. return -ENXIO;
  966. }
  967. /* Enable managed resources */
  968. macio_enable_devres(mdev);
  969. /* Allocate and init private data structure */
  970. priv = devm_kzalloc(&mdev->ofdev.dev,
  971. sizeof(struct pata_macio_priv), GFP_KERNEL);
  972. if (!priv)
  973. return -ENOMEM;
  974. priv->node = of_node_get(mdev->ofdev.dev.of_node);
  975. priv->mdev = mdev;
  976. priv->dev = &mdev->ofdev.dev;
  977. /* Request memory resource for taskfile registers */
  978. if (macio_request_resource(mdev, 0, "pata-macio")) {
  979. dev_err(&mdev->ofdev.dev,
  980. "Cannot obtain taskfile resource\n");
  981. return -EBUSY;
  982. }
  983. tfregs = macio_resource_start(mdev, 0);
  984. /* Request resources for DMA registers if any */
  985. if (macio_resource_count(mdev) >= 2) {
  986. if (macio_request_resource(mdev, 1, "pata-macio-dma"))
  987. dev_err(&mdev->ofdev.dev,
  988. "Cannot obtain DMA resource\n");
  989. else
  990. dmaregs = macio_resource_start(mdev, 1);
  991. }
  992. /*
  993. * Fixup missing IRQ for some old implementations with broken
  994. * device-trees.
  995. *
  996. * This is a bit bogus, it should be fixed in the device-tree itself,
  997. * via the existing macio fixups, based on the type of interrupt
  998. * controller in the machine. However, I have no test HW for this case,
  999. * and this trick works well enough on those old machines...
  1000. */
  1001. if (macio_irq_count(mdev) == 0) {
  1002. dev_warn(&mdev->ofdev.dev,
  1003. "No interrupts for controller, using 13\n");
  1004. irq = irq_create_mapping(NULL, 13);
  1005. } else
  1006. irq = macio_irq(mdev, 0);
  1007. /* Prevvent media bay callbacks until fully registered */
  1008. lock_media_bay(priv->mdev->media_bay);
  1009. /* Get register addresses and call common initialization */
  1010. rc = pata_macio_common_init(priv,
  1011. tfregs, /* Taskfile regs */
  1012. dmaregs, /* DBDMA regs */
  1013. 0, /* Feature control */
  1014. irq);
  1015. unlock_media_bay(priv->mdev->media_bay);
  1016. return rc;
  1017. }
  1018. static int pata_macio_detach(struct macio_dev *mdev)
  1019. {
  1020. struct ata_host *host = macio_get_drvdata(mdev);
  1021. struct pata_macio_priv *priv = host->private_data;
  1022. lock_media_bay(priv->mdev->media_bay);
  1023. /* Make sure the mediabay callback doesn't try to access
  1024. * dead stuff
  1025. */
  1026. priv->host->private_data = NULL;
  1027. ata_host_detach(host);
  1028. unlock_media_bay(priv->mdev->media_bay);
  1029. return 0;
  1030. }
  1031. #ifdef CONFIG_PM_SLEEP
  1032. static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
  1033. {
  1034. struct ata_host *host = macio_get_drvdata(mdev);
  1035. return pata_macio_do_suspend(host->private_data, mesg);
  1036. }
  1037. static int pata_macio_resume(struct macio_dev *mdev)
  1038. {
  1039. struct ata_host *host = macio_get_drvdata(mdev);
  1040. return pata_macio_do_resume(host->private_data);
  1041. }
  1042. #endif /* CONFIG_PM_SLEEP */
  1043. #ifdef CONFIG_PMAC_MEDIABAY
  1044. static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
  1045. {
  1046. struct ata_host *host = macio_get_drvdata(mdev);
  1047. struct ata_port *ap;
  1048. struct ata_eh_info *ehi;
  1049. struct ata_device *dev;
  1050. unsigned long flags;
  1051. if (!host || !host->private_data)
  1052. return;
  1053. ap = host->ports[0];
  1054. spin_lock_irqsave(ap->lock, flags);
  1055. ehi = &ap->link.eh_info;
  1056. if (mb_state == MB_CD) {
  1057. ata_ehi_push_desc(ehi, "mediabay plug");
  1058. ata_ehi_hotplugged(ehi);
  1059. ata_port_freeze(ap);
  1060. } else {
  1061. ata_ehi_push_desc(ehi, "mediabay unplug");
  1062. ata_for_each_dev(dev, &ap->link, ALL)
  1063. dev->flags |= ATA_DFLAG_DETACH;
  1064. ata_port_abort(ap);
  1065. }
  1066. spin_unlock_irqrestore(ap->lock, flags);
  1067. }
  1068. #endif /* CONFIG_PMAC_MEDIABAY */
  1069. static int pata_macio_pci_attach(struct pci_dev *pdev,
  1070. const struct pci_device_id *id)
  1071. {
  1072. struct pata_macio_priv *priv;
  1073. struct device_node *np;
  1074. resource_size_t rbase;
  1075. /* We cannot use a MacIO controller without its OF device node */
  1076. np = pci_device_to_OF_node(pdev);
  1077. if (np == NULL) {
  1078. dev_err(&pdev->dev,
  1079. "Cannot find OF device node for controller\n");
  1080. return -ENODEV;
  1081. }
  1082. /* Check that it can be enabled */
  1083. if (pcim_enable_device(pdev)) {
  1084. dev_err(&pdev->dev,
  1085. "Cannot enable controller PCI device\n");
  1086. return -ENXIO;
  1087. }
  1088. /* Allocate and init private data structure */
  1089. priv = devm_kzalloc(&pdev->dev,
  1090. sizeof(struct pata_macio_priv), GFP_KERNEL);
  1091. if (!priv)
  1092. return -ENOMEM;
  1093. priv->node = of_node_get(np);
  1094. priv->pdev = pdev;
  1095. priv->dev = &pdev->dev;
  1096. /* Get MMIO regions */
  1097. if (pci_request_regions(pdev, "pata-macio")) {
  1098. dev_err(&pdev->dev,
  1099. "Cannot obtain PCI resources\n");
  1100. return -EBUSY;
  1101. }
  1102. /* Get register addresses and call common initialization */
  1103. rbase = pci_resource_start(pdev, 0);
  1104. if (pata_macio_common_init(priv,
  1105. rbase + 0x2000, /* Taskfile regs */
  1106. rbase + 0x1000, /* DBDMA regs */
  1107. rbase, /* Feature control */
  1108. pdev->irq))
  1109. return -ENXIO;
  1110. return 0;
  1111. }
  1112. static void pata_macio_pci_detach(struct pci_dev *pdev)
  1113. {
  1114. struct ata_host *host = pci_get_drvdata(pdev);
  1115. ata_host_detach(host);
  1116. }
  1117. #ifdef CONFIG_PM_SLEEP
  1118. static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
  1119. {
  1120. struct ata_host *host = pci_get_drvdata(pdev);
  1121. return pata_macio_do_suspend(host->private_data, mesg);
  1122. }
  1123. static int pata_macio_pci_resume(struct pci_dev *pdev)
  1124. {
  1125. struct ata_host *host = pci_get_drvdata(pdev);
  1126. return pata_macio_do_resume(host->private_data);
  1127. }
  1128. #endif /* CONFIG_PM_SLEEP */
  1129. static const struct of_device_id pata_macio_match[] =
  1130. {
  1131. { .name = "IDE", },
  1132. { .name = "ATA", },
  1133. { .type = "ide", },
  1134. { .type = "ata", },
  1135. { /* sentinel */ }
  1136. };
  1137. MODULE_DEVICE_TABLE(of, pata_macio_match);
  1138. static struct macio_driver pata_macio_driver =
  1139. {
  1140. .driver = {
  1141. .name = "pata-macio",
  1142. .owner = THIS_MODULE,
  1143. .of_match_table = pata_macio_match,
  1144. },
  1145. .probe = pata_macio_attach,
  1146. .remove = pata_macio_detach,
  1147. #ifdef CONFIG_PM_SLEEP
  1148. .suspend = pata_macio_suspend,
  1149. .resume = pata_macio_resume,
  1150. #endif
  1151. #ifdef CONFIG_PMAC_MEDIABAY
  1152. .mediabay_event = pata_macio_mb_event,
  1153. #endif
  1154. };
  1155. static const struct pci_device_id pata_macio_pci_match[] = {
  1156. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
  1157. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
  1158. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
  1159. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
  1160. { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
  1161. {},
  1162. };
  1163. static struct pci_driver pata_macio_pci_driver = {
  1164. .name = "pata-pci-macio",
  1165. .id_table = pata_macio_pci_match,
  1166. .probe = pata_macio_pci_attach,
  1167. .remove = pata_macio_pci_detach,
  1168. #ifdef CONFIG_PM_SLEEP
  1169. .suspend = pata_macio_pci_suspend,
  1170. .resume = pata_macio_pci_resume,
  1171. #endif
  1172. .driver = {
  1173. .owner = THIS_MODULE,
  1174. },
  1175. };
  1176. MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
  1177. static int __init pata_macio_init(void)
  1178. {
  1179. int rc;
  1180. if (!machine_is(powermac))
  1181. return -ENODEV;
  1182. rc = pci_register_driver(&pata_macio_pci_driver);
  1183. if (rc)
  1184. return rc;
  1185. rc = macio_register_driver(&pata_macio_driver);
  1186. if (rc) {
  1187. pci_unregister_driver(&pata_macio_pci_driver);
  1188. return rc;
  1189. }
  1190. return 0;
  1191. }
  1192. static void __exit pata_macio_exit(void)
  1193. {
  1194. macio_unregister_driver(&pata_macio_driver);
  1195. pci_unregister_driver(&pata_macio_pci_driver);
  1196. }
  1197. module_init(pata_macio_init);
  1198. module_exit(pata_macio_exit);
  1199. MODULE_AUTHOR("Benjamin Herrenschmidt");
  1200. MODULE_DESCRIPTION("Apple MacIO PATA driver");
  1201. MODULE_LICENSE("GPL");
  1202. MODULE_VERSION(DRV_VERSION);