pata_legacy.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * pata-legacy.c - Legacy port PATA/SATA controller driver.
  4. * Copyright 2005/2006 Red Hat, all rights reserved.
  5. *
  6. * An ATA driver for the legacy ATA ports.
  7. *
  8. * Data Sources:
  9. * Opti 82C465/82C611 support: Data sheets at opti-inc.com
  10. * HT6560 series:
  11. * Promise 20230/20620:
  12. * http://www.ryston.cz/petr/vlb/pdc20230b.html
  13. * http://www.ryston.cz/petr/vlb/pdc20230c.html
  14. * http://www.ryston.cz/petr/vlb/pdc20630.html
  15. * QDI65x0:
  16. * http://www.ryston.cz/petr/vlb/qd6500.html
  17. * http://www.ryston.cz/petr/vlb/qd6580.html
  18. *
  19. * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
  20. * Rewritten from the work of Colten Edwards <[email protected]> by
  21. * Samuel Thibault <[email protected]>
  22. *
  23. * Unsupported but docs exist:
  24. * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
  25. *
  26. * This driver handles legacy (that is "ISA/VLB side") IDE ports found
  27. * on PC class systems. There are three hybrid devices that are exceptions
  28. * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
  29. * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
  30. *
  31. * Specific support is included for the ht6560a/ht6560b/opti82c611a/
  32. * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
  33. *
  34. * Support for the Winbond 83759A when operating in advanced mode.
  35. * Multichip mode is not currently supported.
  36. *
  37. * Use the autospeed and pio_mask options with:
  38. * Appian ADI/2 aka CLPD7220 or AIC25VL01.
  39. * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
  40. * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
  41. * Winbond W83759A, Promise PDC20230-B
  42. *
  43. * For now use autospeed and pio_mask as above with the W83759A. This may
  44. * change.
  45. */
  46. #include <linux/async.h>
  47. #include <linux/kernel.h>
  48. #include <linux/module.h>
  49. #include <linux/pci.h>
  50. #include <linux/init.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <scsi/scsi_host.h>
  54. #include <linux/ata.h>
  55. #include <linux/libata.h>
  56. #include <linux/platform_device.h>
  57. #define DRV_NAME "pata_legacy"
  58. #define DRV_VERSION "0.6.5"
  59. #define NR_HOST 6
  60. static int all;
  61. module_param(all, int, 0444);
  62. MODULE_PARM_DESC(all,
  63. "Set to probe unclaimed pri/sec ISA port ranges even if PCI");
  64. static int probe_all;
  65. module_param(probe_all, int, 0);
  66. MODULE_PARM_DESC(probe_all,
  67. "Set to probe tertiary+ ISA port ranges even if PCI");
  68. static int probe_mask = ~0;
  69. module_param(probe_mask, int, 0);
  70. MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports");
  71. static int autospeed;
  72. module_param(autospeed, int, 0);
  73. MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes");
  74. static int pio_mask = ATA_PIO4;
  75. module_param(pio_mask, int, 0);
  76. MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices");
  77. static int iordy_mask = 0xFFFFFFFF;
  78. module_param(iordy_mask, int, 0);
  79. MODULE_PARM_DESC(iordy_mask, "Use IORDY if available");
  80. static int ht6560a;
  81. module_param(ht6560a, int, 0);
  82. MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3");
  83. static int ht6560b;
  84. module_param(ht6560b, int, 0);
  85. MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3");
  86. static int opti82c611a;
  87. module_param(opti82c611a, int, 0);
  88. MODULE_PARM_DESC(opti82c611a,
  89. "Opti 82c611A on primary 1, secondary 2, both 3");
  90. static int opti82c46x;
  91. module_param(opti82c46x, int, 0);
  92. MODULE_PARM_DESC(opti82c46x,
  93. "Opti 82c465MV on primary 1, secondary 2, both 3");
  94. #ifdef CONFIG_PATA_QDI_MODULE
  95. static int qdi = 1;
  96. #else
  97. static int qdi;
  98. #endif
  99. module_param(qdi, int, 0);
  100. MODULE_PARM_DESC(qdi, "Set to probe QDI controllers");
  101. #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
  102. static int winbond = 1;
  103. #else
  104. static int winbond;
  105. #endif
  106. module_param(winbond, int, 0);
  107. MODULE_PARM_DESC(winbond,
  108. "Set to probe Winbond controllers, "
  109. "give I/O port if non standard");
  110. enum controller {
  111. BIOS = 0,
  112. SNOOP = 1,
  113. PDC20230 = 2,
  114. HT6560A = 3,
  115. HT6560B = 4,
  116. OPTI611A = 5,
  117. OPTI46X = 6,
  118. QDI6500 = 7,
  119. QDI6580 = 8,
  120. QDI6580DP = 9, /* Dual channel mode is different */
  121. W83759A = 10,
  122. UNKNOWN = -1
  123. };
  124. struct legacy_data {
  125. unsigned long timing;
  126. u8 clock[2];
  127. u8 last;
  128. int fast;
  129. enum controller type;
  130. struct platform_device *platform_dev;
  131. };
  132. struct legacy_probe {
  133. unsigned char *name;
  134. unsigned long port;
  135. unsigned int irq;
  136. unsigned int slot;
  137. enum controller type;
  138. unsigned long private;
  139. };
  140. struct legacy_controller {
  141. const char *name;
  142. struct ata_port_operations *ops;
  143. unsigned int pio_mask;
  144. unsigned int flags;
  145. unsigned int pflags;
  146. int (*setup)(struct platform_device *, struct legacy_probe *probe,
  147. struct legacy_data *data);
  148. };
  149. static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
  150. static struct legacy_probe probe_list[NR_HOST];
  151. static struct legacy_data legacy_data[NR_HOST];
  152. static struct ata_host *legacy_host[NR_HOST];
  153. static int nr_legacy_host;
  154. /**
  155. * legacy_probe_add - Add interface to probe list
  156. * @port: Controller port
  157. * @irq: IRQ number
  158. * @type: Controller type
  159. * @private: Controller specific info
  160. *
  161. * Add an entry into the probe list for ATA controllers. This is used
  162. * to add the default ISA slots and then to build up the table
  163. * further according to other ISA/VLB/Weird device scans
  164. *
  165. * An I/O port list is used to keep ordering stable and sane, as we
  166. * don't have any good way to talk about ordering otherwise
  167. */
  168. static int legacy_probe_add(unsigned long port, unsigned int irq,
  169. enum controller type, unsigned long private)
  170. {
  171. struct legacy_probe *lp = &probe_list[0];
  172. int i;
  173. struct legacy_probe *free = NULL;
  174. for (i = 0; i < NR_HOST; i++) {
  175. if (lp->port == 0 && free == NULL)
  176. free = lp;
  177. /* Matching port, or the correct slot for ordering */
  178. if (lp->port == port || legacy_port[i] == port) {
  179. if (!(probe_mask & 1 << i))
  180. return -1;
  181. free = lp;
  182. break;
  183. }
  184. lp++;
  185. }
  186. if (free == NULL) {
  187. printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
  188. return -1;
  189. }
  190. /* Fill in the entry for later probing */
  191. free->port = port;
  192. free->irq = irq;
  193. free->type = type;
  194. free->private = private;
  195. return 0;
  196. }
  197. /**
  198. * legacy_set_mode - mode setting
  199. * @link: IDE link
  200. * @unused: Device that failed when error is returned
  201. *
  202. * Use a non standard set_mode function. We don't want to be tuned.
  203. *
  204. * The BIOS configured everything. Our job is not to fiddle. Just use
  205. * whatever PIO the hardware is using and leave it at that. When we
  206. * get some kind of nice user driven API for control then we can
  207. * expand on this as per hdparm in the base kernel.
  208. */
  209. static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
  210. {
  211. struct ata_device *dev;
  212. ata_for_each_dev(dev, link, ENABLED) {
  213. ata_dev_info(dev, "configured for PIO\n");
  214. dev->pio_mode = XFER_PIO_0;
  215. dev->xfer_mode = XFER_PIO_0;
  216. dev->xfer_shift = ATA_SHIFT_PIO;
  217. dev->flags |= ATA_DFLAG_PIO;
  218. }
  219. return 0;
  220. }
  221. static struct scsi_host_template legacy_sht = {
  222. ATA_PIO_SHT(DRV_NAME),
  223. };
  224. static const struct ata_port_operations legacy_base_port_ops = {
  225. .inherits = &ata_sff_port_ops,
  226. .cable_detect = ata_cable_40wire,
  227. };
  228. /*
  229. * These ops are used if the user indicates the hardware
  230. * snoops the commands to decide on the mode and handles the
  231. * mode selection "magically" itself. Several legacy controllers
  232. * do this. The mode range can be set if it is not 0x1F by setting
  233. * pio_mask as well.
  234. */
  235. static struct ata_port_operations simple_port_ops = {
  236. .inherits = &legacy_base_port_ops,
  237. .sff_data_xfer = ata_sff_data_xfer32,
  238. };
  239. static struct ata_port_operations legacy_port_ops = {
  240. .inherits = &legacy_base_port_ops,
  241. .sff_data_xfer = ata_sff_data_xfer32,
  242. .set_mode = legacy_set_mode,
  243. };
  244. /*
  245. * Promise 20230C and 20620 support
  246. *
  247. * This controller supports PIO0 to PIO2. We set PIO timings
  248. * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
  249. * support is weird being DMA to controller and PIO'd to the host
  250. * and not supported.
  251. */
  252. static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
  253. {
  254. int tries = 5;
  255. int pio = adev->pio_mode - XFER_PIO_0;
  256. u8 rt;
  257. unsigned long flags;
  258. /* Safe as UP only. Force I/Os to occur together */
  259. local_irq_save(flags);
  260. /* Unlock the control interface */
  261. do {
  262. inb(0x1F5);
  263. outb(inb(0x1F2) | 0x80, 0x1F2);
  264. inb(0x1F2);
  265. inb(0x3F6);
  266. inb(0x3F6);
  267. inb(0x1F2);
  268. inb(0x1F2);
  269. }
  270. while ((inb(0x1F2) & 0x80) && --tries);
  271. local_irq_restore(flags);
  272. outb(inb(0x1F4) & 0x07, 0x1F4);
  273. rt = inb(0x1F3);
  274. rt &= ~(0x07 << (3 * !adev->devno));
  275. if (pio)
  276. rt |= (1 + 3 * pio) << (3 * !adev->devno);
  277. outb(rt, 0x1F3);
  278. udelay(100);
  279. outb(inb(0x1F2) | 0x01, 0x1F2);
  280. udelay(100);
  281. inb(0x1F5);
  282. }
  283. static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
  284. unsigned char *buf, unsigned int buflen, int rw)
  285. {
  286. struct ata_device *dev = qc->dev;
  287. struct ata_port *ap = dev->link->ap;
  288. int slop = buflen & 3;
  289. /* 32bit I/O capable *and* we need to write a whole number of dwords */
  290. if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
  291. && (ap->pflags & ATA_PFLAG_PIO32)) {
  292. unsigned long flags;
  293. local_irq_save(flags);
  294. /* Perform the 32bit I/O synchronization sequence */
  295. ioread8(ap->ioaddr.nsect_addr);
  296. ioread8(ap->ioaddr.nsect_addr);
  297. ioread8(ap->ioaddr.nsect_addr);
  298. /* Now the data */
  299. if (rw == READ)
  300. ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
  301. else
  302. iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
  303. if (unlikely(slop)) {
  304. __le32 pad = 0;
  305. if (rw == READ) {
  306. pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
  307. memcpy(buf + buflen - slop, &pad, slop);
  308. } else {
  309. memcpy(&pad, buf + buflen - slop, slop);
  310. iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
  311. }
  312. buflen += 4 - slop;
  313. }
  314. local_irq_restore(flags);
  315. } else
  316. buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
  317. return buflen;
  318. }
  319. static struct ata_port_operations pdc20230_port_ops = {
  320. .inherits = &legacy_base_port_ops,
  321. .set_piomode = pdc20230_set_piomode,
  322. .sff_data_xfer = pdc_data_xfer_vlb,
  323. };
  324. /*
  325. * Holtek 6560A support
  326. *
  327. * This controller supports PIO0 to PIO2 (no IORDY even though higher
  328. * timings can be loaded).
  329. */
  330. static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
  331. {
  332. u8 active, recover;
  333. struct ata_timing t;
  334. /* Get the timing data in cycles. For now play safe at 50Mhz */
  335. ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
  336. active = clamp_val(t.active, 2, 15);
  337. recover = clamp_val(t.recover, 4, 15);
  338. inb(0x3E6);
  339. inb(0x3E6);
  340. inb(0x3E6);
  341. inb(0x3E6);
  342. iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
  343. ioread8(ap->ioaddr.status_addr);
  344. }
  345. static struct ata_port_operations ht6560a_port_ops = {
  346. .inherits = &legacy_base_port_ops,
  347. .set_piomode = ht6560a_set_piomode,
  348. };
  349. /*
  350. * Holtek 6560B support
  351. *
  352. * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
  353. * setting unless we see an ATAPI device in which case we force it off.
  354. *
  355. * FIXME: need to implement 2nd channel support.
  356. */
  357. static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
  358. {
  359. u8 active, recover;
  360. struct ata_timing t;
  361. /* Get the timing data in cycles. For now play safe at 50Mhz */
  362. ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
  363. active = clamp_val(t.active, 2, 15);
  364. recover = clamp_val(t.recover, 2, 16) & 0x0F;
  365. inb(0x3E6);
  366. inb(0x3E6);
  367. inb(0x3E6);
  368. inb(0x3E6);
  369. iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
  370. if (adev->class != ATA_DEV_ATA) {
  371. u8 rconf = inb(0x3E6);
  372. if (rconf & 0x24) {
  373. rconf &= ~0x24;
  374. outb(rconf, 0x3E6);
  375. }
  376. }
  377. ioread8(ap->ioaddr.status_addr);
  378. }
  379. static struct ata_port_operations ht6560b_port_ops = {
  380. .inherits = &legacy_base_port_ops,
  381. .set_piomode = ht6560b_set_piomode,
  382. };
  383. /*
  384. * Opti core chipset helpers
  385. */
  386. /**
  387. * opti_syscfg - read OPTI chipset configuration
  388. * @reg: Configuration register to read
  389. *
  390. * Returns the value of an OPTI system board configuration register.
  391. */
  392. static u8 opti_syscfg(u8 reg)
  393. {
  394. unsigned long flags;
  395. u8 r;
  396. /* Uniprocessor chipset and must force cycles adjancent */
  397. local_irq_save(flags);
  398. outb(reg, 0x22);
  399. r = inb(0x24);
  400. local_irq_restore(flags);
  401. return r;
  402. }
  403. /*
  404. * Opti 82C611A
  405. *
  406. * This controller supports PIO0 to PIO3.
  407. */
  408. static void opti82c611a_set_piomode(struct ata_port *ap,
  409. struct ata_device *adev)
  410. {
  411. u8 active, recover, setup;
  412. struct ata_timing t;
  413. struct ata_device *pair = ata_dev_pair(adev);
  414. int clock;
  415. int khz[4] = { 50000, 40000, 33000, 25000 };
  416. u8 rc;
  417. /* Enter configuration mode */
  418. ioread16(ap->ioaddr.error_addr);
  419. ioread16(ap->ioaddr.error_addr);
  420. iowrite8(3, ap->ioaddr.nsect_addr);
  421. /* Read VLB clock strapping */
  422. clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
  423. /* Get the timing data in cycles */
  424. ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
  425. /* Setup timing is shared */
  426. if (pair) {
  427. struct ata_timing tp;
  428. ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
  429. ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
  430. }
  431. active = clamp_val(t.active, 2, 17) - 2;
  432. recover = clamp_val(t.recover, 1, 16) - 1;
  433. setup = clamp_val(t.setup, 1, 4) - 1;
  434. /* Select the right timing bank for write timing */
  435. rc = ioread8(ap->ioaddr.lbal_addr);
  436. rc &= 0x7F;
  437. rc |= (adev->devno << 7);
  438. iowrite8(rc, ap->ioaddr.lbal_addr);
  439. /* Write the timings */
  440. iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
  441. /* Select the right bank for read timings, also
  442. load the shared timings for address */
  443. rc = ioread8(ap->ioaddr.device_addr);
  444. rc &= 0xC0;
  445. rc |= adev->devno; /* Index select */
  446. rc |= (setup << 4) | 0x04;
  447. iowrite8(rc, ap->ioaddr.device_addr);
  448. /* Load the read timings */
  449. iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
  450. /* Ensure the timing register mode is right */
  451. rc = ioread8(ap->ioaddr.lbal_addr);
  452. rc &= 0x73;
  453. rc |= 0x84;
  454. iowrite8(rc, ap->ioaddr.lbal_addr);
  455. /* Exit command mode */
  456. iowrite8(0x83, ap->ioaddr.nsect_addr);
  457. }
  458. static struct ata_port_operations opti82c611a_port_ops = {
  459. .inherits = &legacy_base_port_ops,
  460. .set_piomode = opti82c611a_set_piomode,
  461. };
  462. /*
  463. * Opti 82C465MV
  464. *
  465. * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
  466. * version is dual channel but doesn't have a lot of unique registers.
  467. */
  468. static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
  469. {
  470. u8 active, recover, setup;
  471. struct ata_timing t;
  472. struct ata_device *pair = ata_dev_pair(adev);
  473. int clock;
  474. int khz[4] = { 50000, 40000, 33000, 25000 };
  475. u8 rc;
  476. u8 sysclk;
  477. /* Get the clock */
  478. sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
  479. /* Enter configuration mode */
  480. ioread16(ap->ioaddr.error_addr);
  481. ioread16(ap->ioaddr.error_addr);
  482. iowrite8(3, ap->ioaddr.nsect_addr);
  483. /* Read VLB clock strapping */
  484. clock = 1000000000 / khz[sysclk];
  485. /* Get the timing data in cycles */
  486. ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
  487. /* Setup timing is shared */
  488. if (pair) {
  489. struct ata_timing tp;
  490. ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
  491. ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
  492. }
  493. active = clamp_val(t.active, 2, 17) - 2;
  494. recover = clamp_val(t.recover, 1, 16) - 1;
  495. setup = clamp_val(t.setup, 1, 4) - 1;
  496. /* Select the right timing bank for write timing */
  497. rc = ioread8(ap->ioaddr.lbal_addr);
  498. rc &= 0x7F;
  499. rc |= (adev->devno << 7);
  500. iowrite8(rc, ap->ioaddr.lbal_addr);
  501. /* Write the timings */
  502. iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
  503. /* Select the right bank for read timings, also
  504. load the shared timings for address */
  505. rc = ioread8(ap->ioaddr.device_addr);
  506. rc &= 0xC0;
  507. rc |= adev->devno; /* Index select */
  508. rc |= (setup << 4) | 0x04;
  509. iowrite8(rc, ap->ioaddr.device_addr);
  510. /* Load the read timings */
  511. iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
  512. /* Ensure the timing register mode is right */
  513. rc = ioread8(ap->ioaddr.lbal_addr);
  514. rc &= 0x73;
  515. rc |= 0x84;
  516. iowrite8(rc, ap->ioaddr.lbal_addr);
  517. /* Exit command mode */
  518. iowrite8(0x83, ap->ioaddr.nsect_addr);
  519. /* We need to know this for quad device on the MVB */
  520. ap->host->private_data = ap;
  521. }
  522. /**
  523. * opti82c46x_qc_issue - command issue
  524. * @qc: command pending
  525. *
  526. * Called when the libata layer is about to issue a command. We wrap
  527. * this interface so that we can load the correct ATA timings. The
  528. * MVB has a single set of timing registers and these are shared
  529. * across channels. As there are two registers we really ought to
  530. * track the last two used values as a sort of register window. For
  531. * now we just reload on a channel switch. On the single channel
  532. * setup this condition never fires so we do nothing extra.
  533. *
  534. * FIXME: dual channel needs ->serialize support
  535. */
  536. static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
  537. {
  538. struct ata_port *ap = qc->ap;
  539. struct ata_device *adev = qc->dev;
  540. /* If timings are set and for the wrong channel (2nd test is
  541. due to a libata shortcoming and will eventually go I hope) */
  542. if (ap->host->private_data != ap->host
  543. && ap->host->private_data != NULL)
  544. opti82c46x_set_piomode(ap, adev);
  545. return ata_sff_qc_issue(qc);
  546. }
  547. static struct ata_port_operations opti82c46x_port_ops = {
  548. .inherits = &legacy_base_port_ops,
  549. .set_piomode = opti82c46x_set_piomode,
  550. .qc_issue = opti82c46x_qc_issue,
  551. };
  552. /**
  553. * qdi65x0_set_piomode - PIO setup for QDI65x0
  554. * @ap: Port
  555. * @adev: Device
  556. *
  557. * In single channel mode the 6580 has one clock per device and we can
  558. * avoid the requirement to clock switch. We also have to load the timing
  559. * into the right clock according to whether we are master or slave.
  560. *
  561. * In dual channel mode the 6580 has one clock per channel and we have
  562. * to software clockswitch in qc_issue.
  563. */
  564. static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
  565. {
  566. struct ata_timing t;
  567. struct legacy_data *ld_qdi = ap->host->private_data;
  568. int active, recovery;
  569. u8 timing;
  570. /* Get the timing data in cycles */
  571. ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
  572. if (ld_qdi->fast) {
  573. active = 8 - clamp_val(t.active, 1, 8);
  574. recovery = 18 - clamp_val(t.recover, 3, 18);
  575. } else {
  576. active = 9 - clamp_val(t.active, 2, 9);
  577. recovery = 15 - clamp_val(t.recover, 0, 15);
  578. }
  579. timing = (recovery << 4) | active | 0x08;
  580. ld_qdi->clock[adev->devno] = timing;
  581. if (ld_qdi->type == QDI6580)
  582. outb(timing, ld_qdi->timing + 2 * adev->devno);
  583. else
  584. outb(timing, ld_qdi->timing + 2 * ap->port_no);
  585. /* Clear the FIFO */
  586. if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
  587. outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
  588. }
  589. /**
  590. * qdi_qc_issue - command issue
  591. * @qc: command pending
  592. *
  593. * Called when the libata layer is about to issue a command. We wrap
  594. * this interface so that we can load the correct ATA timings.
  595. */
  596. static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
  597. {
  598. struct ata_port *ap = qc->ap;
  599. struct ata_device *adev = qc->dev;
  600. struct legacy_data *ld_qdi = ap->host->private_data;
  601. if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
  602. if (adev->pio_mode) {
  603. ld_qdi->last = ld_qdi->clock[adev->devno];
  604. outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
  605. 2 * ap->port_no);
  606. }
  607. }
  608. return ata_sff_qc_issue(qc);
  609. }
  610. static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
  611. unsigned char *buf,
  612. unsigned int buflen, int rw)
  613. {
  614. struct ata_device *adev = qc->dev;
  615. struct ata_port *ap = adev->link->ap;
  616. int slop = buflen & 3;
  617. if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
  618. && (ap->pflags & ATA_PFLAG_PIO32)) {
  619. if (rw == WRITE)
  620. iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
  621. else
  622. ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
  623. if (unlikely(slop)) {
  624. __le32 pad = 0;
  625. if (rw == WRITE) {
  626. memcpy(&pad, buf + buflen - slop, slop);
  627. iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
  628. } else {
  629. pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
  630. memcpy(buf + buflen - slop, &pad, slop);
  631. }
  632. }
  633. return (buflen + 3) & ~3;
  634. } else
  635. return ata_sff_data_xfer(qc, buf, buflen, rw);
  636. }
  637. static int qdi_port(struct platform_device *dev,
  638. struct legacy_probe *lp, struct legacy_data *ld)
  639. {
  640. if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
  641. return -EBUSY;
  642. ld->timing = lp->private;
  643. return 0;
  644. }
  645. static struct ata_port_operations qdi6500_port_ops = {
  646. .inherits = &legacy_base_port_ops,
  647. .set_piomode = qdi65x0_set_piomode,
  648. .qc_issue = qdi_qc_issue,
  649. .sff_data_xfer = vlb32_data_xfer,
  650. };
  651. static struct ata_port_operations qdi6580_port_ops = {
  652. .inherits = &legacy_base_port_ops,
  653. .set_piomode = qdi65x0_set_piomode,
  654. .sff_data_xfer = vlb32_data_xfer,
  655. };
  656. static struct ata_port_operations qdi6580dp_port_ops = {
  657. .inherits = &legacy_base_port_ops,
  658. .set_piomode = qdi65x0_set_piomode,
  659. .qc_issue = qdi_qc_issue,
  660. .sff_data_xfer = vlb32_data_xfer,
  661. };
  662. static DEFINE_SPINLOCK(winbond_lock);
  663. static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
  664. {
  665. unsigned long flags;
  666. spin_lock_irqsave(&winbond_lock, flags);
  667. outb(reg, port + 0x01);
  668. outb(val, port + 0x02);
  669. spin_unlock_irqrestore(&winbond_lock, flags);
  670. }
  671. static u8 winbond_readcfg(unsigned long port, u8 reg)
  672. {
  673. u8 val;
  674. unsigned long flags;
  675. spin_lock_irqsave(&winbond_lock, flags);
  676. outb(reg, port + 0x01);
  677. val = inb(port + 0x02);
  678. spin_unlock_irqrestore(&winbond_lock, flags);
  679. return val;
  680. }
  681. static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
  682. {
  683. struct ata_timing t;
  684. struct legacy_data *ld_winbond = ap->host->private_data;
  685. int active, recovery;
  686. u8 reg;
  687. int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
  688. reg = winbond_readcfg(ld_winbond->timing, 0x81);
  689. /* Get the timing data in cycles */
  690. if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
  691. ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
  692. else
  693. ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
  694. active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
  695. recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
  696. timing = (active << 4) | recovery;
  697. winbond_writecfg(ld_winbond->timing, timing, reg);
  698. /* Load the setup timing */
  699. reg = 0x35;
  700. if (adev->class != ATA_DEV_ATA)
  701. reg |= 0x08; /* FIFO off */
  702. if (!ata_pio_need_iordy(adev))
  703. reg |= 0x02; /* IORDY off */
  704. reg |= (clamp_val(t.setup, 0, 3) << 6);
  705. winbond_writecfg(ld_winbond->timing, timing + 1, reg);
  706. }
  707. static int winbond_port(struct platform_device *dev,
  708. struct legacy_probe *lp, struct legacy_data *ld)
  709. {
  710. if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
  711. return -EBUSY;
  712. ld->timing = lp->private;
  713. return 0;
  714. }
  715. static struct ata_port_operations winbond_port_ops = {
  716. .inherits = &legacy_base_port_ops,
  717. .set_piomode = winbond_set_piomode,
  718. .sff_data_xfer = vlb32_data_xfer,
  719. };
  720. static struct legacy_controller controllers[] = {
  721. {"BIOS", &legacy_port_ops, ATA_PIO4,
  722. ATA_FLAG_NO_IORDY, 0, NULL },
  723. {"Snooping", &simple_port_ops, ATA_PIO4,
  724. 0, 0, NULL },
  725. {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
  726. ATA_FLAG_NO_IORDY,
  727. ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
  728. {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
  729. ATA_FLAG_NO_IORDY, 0, NULL },
  730. {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
  731. ATA_FLAG_NO_IORDY, 0, NULL },
  732. {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
  733. 0, 0, NULL },
  734. {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
  735. 0, 0, NULL },
  736. {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
  737. ATA_FLAG_NO_IORDY,
  738. ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
  739. {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
  740. 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
  741. {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
  742. 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
  743. {"W83759A", &winbond_port_ops, ATA_PIO4,
  744. 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
  745. winbond_port }
  746. };
  747. /**
  748. * probe_chip_type - Discover controller
  749. * @probe: Probe entry to check
  750. *
  751. * Probe an ATA port and identify the type of controller. We don't
  752. * check if the controller appears to be driveless at this point.
  753. */
  754. static __init int probe_chip_type(struct legacy_probe *probe)
  755. {
  756. int mask = 1 << probe->slot;
  757. if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
  758. u8 reg = winbond_readcfg(winbond, 0x81);
  759. reg |= 0x80; /* jumpered mode off */
  760. winbond_writecfg(winbond, 0x81, reg);
  761. reg = winbond_readcfg(winbond, 0x83);
  762. reg |= 0xF0; /* local control */
  763. winbond_writecfg(winbond, 0x83, reg);
  764. reg = winbond_readcfg(winbond, 0x85);
  765. reg |= 0xF0; /* programmable timing */
  766. winbond_writecfg(winbond, 0x85, reg);
  767. reg = winbond_readcfg(winbond, 0x81);
  768. if (reg & mask)
  769. return W83759A;
  770. }
  771. if (probe->port == 0x1F0) {
  772. unsigned long flags;
  773. local_irq_save(flags);
  774. /* Probes */
  775. outb(inb(0x1F2) | 0x80, 0x1F2);
  776. inb(0x1F5);
  777. inb(0x1F2);
  778. inb(0x3F6);
  779. inb(0x3F6);
  780. inb(0x1F2);
  781. inb(0x1F2);
  782. if ((inb(0x1F2) & 0x80) == 0) {
  783. /* PDC20230c or 20630 ? */
  784. printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
  785. " detected.\n");
  786. udelay(100);
  787. inb(0x1F5);
  788. local_irq_restore(flags);
  789. return PDC20230;
  790. } else {
  791. outb(0x55, 0x1F2);
  792. inb(0x1F2);
  793. inb(0x1F2);
  794. if (inb(0x1F2) == 0x00)
  795. printk(KERN_INFO "PDC20230-B VLB ATA "
  796. "controller detected.\n");
  797. local_irq_restore(flags);
  798. return BIOS;
  799. }
  800. }
  801. if (ht6560a & mask)
  802. return HT6560A;
  803. if (ht6560b & mask)
  804. return HT6560B;
  805. if (opti82c611a & mask)
  806. return OPTI611A;
  807. if (opti82c46x & mask)
  808. return OPTI46X;
  809. if (autospeed & mask)
  810. return SNOOP;
  811. return BIOS;
  812. }
  813. /**
  814. * legacy_init_one - attach a legacy interface
  815. * @probe: probe record
  816. *
  817. * Register an ISA bus IDE interface. Such interfaces are PIO and we
  818. * assume do not support IRQ sharing.
  819. */
  820. static __init int legacy_init_one(struct legacy_probe *probe)
  821. {
  822. struct legacy_controller *controller = &controllers[probe->type];
  823. int pio_modes = controller->pio_mask;
  824. unsigned long io = probe->port;
  825. u32 mask = (1 << probe->slot);
  826. struct ata_port_operations *ops = controller->ops;
  827. struct legacy_data *ld = &legacy_data[probe->slot];
  828. struct ata_host *host = NULL;
  829. struct ata_port *ap;
  830. struct platform_device *pdev;
  831. struct ata_device *dev;
  832. void __iomem *io_addr, *ctrl_addr;
  833. u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
  834. int ret;
  835. iordy |= controller->flags;
  836. pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
  837. if (IS_ERR(pdev))
  838. return PTR_ERR(pdev);
  839. ret = -EBUSY;
  840. if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
  841. devm_request_region(&pdev->dev, io + 0x0206, 1,
  842. "pata_legacy") == NULL)
  843. goto fail;
  844. ret = -ENOMEM;
  845. io_addr = devm_ioport_map(&pdev->dev, io, 8);
  846. ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
  847. if (!io_addr || !ctrl_addr)
  848. goto fail;
  849. ld->type = probe->type;
  850. if (controller->setup)
  851. if (controller->setup(pdev, probe, ld) < 0)
  852. goto fail;
  853. host = ata_host_alloc(&pdev->dev, 1);
  854. if (!host)
  855. goto fail;
  856. ap = host->ports[0];
  857. ap->ops = ops;
  858. ap->pio_mask = pio_modes;
  859. ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
  860. ap->pflags |= controller->pflags;
  861. ap->ioaddr.cmd_addr = io_addr;
  862. ap->ioaddr.altstatus_addr = ctrl_addr;
  863. ap->ioaddr.ctl_addr = ctrl_addr;
  864. ata_sff_std_ports(&ap->ioaddr);
  865. ap->host->private_data = ld;
  866. ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
  867. ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
  868. &legacy_sht);
  869. if (ret)
  870. goto fail;
  871. async_synchronize_full();
  872. ld->platform_dev = pdev;
  873. /* Nothing found means we drop the port as its probably not there */
  874. ret = -ENODEV;
  875. ata_for_each_dev(dev, &ap->link, ALL) {
  876. if (!ata_dev_absent(dev)) {
  877. legacy_host[probe->slot] = host;
  878. ld->platform_dev = pdev;
  879. return 0;
  880. }
  881. }
  882. ata_host_detach(host);
  883. fail:
  884. platform_device_unregister(pdev);
  885. return ret;
  886. }
  887. /**
  888. * legacy_check_special_cases - ATA special cases
  889. * @p: PCI device to check
  890. * @primary: set this if we find an ATA master
  891. * @secondary: set this if we find an ATA secondary
  892. *
  893. * A small number of vendors implemented early PCI ATA interfaces
  894. * on bridge logic without the ATA interface being PCI visible.
  895. * Where we have a matching PCI driver we must skip the relevant
  896. * device here. If we don't know about it then the legacy driver
  897. * is the right driver anyway.
  898. */
  899. static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
  900. int *secondary)
  901. {
  902. /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
  903. if (p->vendor == 0x1078 && p->device == 0x0000) {
  904. *primary = *secondary = 1;
  905. return;
  906. }
  907. /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
  908. if (p->vendor == 0x1078 && p->device == 0x0002) {
  909. *primary = *secondary = 1;
  910. return;
  911. }
  912. /* Intel MPIIX - PIO ATA on non PCI side of bridge */
  913. if (p->vendor == 0x8086 && p->device == 0x1234) {
  914. u16 r;
  915. pci_read_config_word(p, 0x6C, &r);
  916. if (r & 0x8000) {
  917. /* ATA port enabled */
  918. if (r & 0x4000)
  919. *secondary = 1;
  920. else
  921. *primary = 1;
  922. }
  923. return;
  924. }
  925. }
  926. static __init void probe_opti_vlb(void)
  927. {
  928. /* If an OPTI 82C46X is present find out where the channels are */
  929. static const char *optis[4] = {
  930. "3/463MV", "5MV",
  931. "5MVA", "5MVB"
  932. };
  933. u8 chans = 1;
  934. u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
  935. opti82c46x = 3; /* Assume master and slave first */
  936. printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
  937. optis[ctrl]);
  938. if (ctrl == 3)
  939. chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
  940. ctrl = opti_syscfg(0xAC);
  941. /* Check enabled and this port is the 465MV port. On the
  942. MVB we may have two channels */
  943. if (ctrl & 8) {
  944. if (chans == 2) {
  945. legacy_probe_add(0x1F0, 14, OPTI46X, 0);
  946. legacy_probe_add(0x170, 15, OPTI46X, 0);
  947. }
  948. if (ctrl & 4)
  949. legacy_probe_add(0x170, 15, OPTI46X, 0);
  950. else
  951. legacy_probe_add(0x1F0, 14, OPTI46X, 0);
  952. } else
  953. legacy_probe_add(0x1F0, 14, OPTI46X, 0);
  954. }
  955. static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
  956. {
  957. static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
  958. /* Check card type */
  959. if ((r & 0xF0) == 0xC0) {
  960. /* QD6500: single channel */
  961. if (r & 8)
  962. /* Disabled ? */
  963. return;
  964. legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
  965. QDI6500, port);
  966. }
  967. if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
  968. /* QD6580: dual channel */
  969. if (!request_region(port + 2 , 2, "pata_qdi")) {
  970. release_region(port, 2);
  971. return;
  972. }
  973. res = inb(port + 3);
  974. /* Single channel mode ? */
  975. if (res & 1)
  976. legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
  977. QDI6580, port);
  978. else { /* Dual channel mode */
  979. legacy_probe_add(0x1F0, 14, QDI6580DP, port);
  980. /* port + 0x02, r & 0x04 */
  981. legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
  982. }
  983. release_region(port + 2, 2);
  984. }
  985. }
  986. static __init void probe_qdi_vlb(void)
  987. {
  988. unsigned long flags;
  989. static const unsigned long qd_port[2] = { 0x30, 0xB0 };
  990. int i;
  991. /*
  992. * Check each possible QD65xx base address
  993. */
  994. for (i = 0; i < 2; i++) {
  995. unsigned long port = qd_port[i];
  996. u8 r, res;
  997. if (request_region(port, 2, "pata_qdi")) {
  998. /* Check for a card */
  999. local_irq_save(flags);
  1000. /* I have no h/w that needs this delay but it
  1001. is present in the historic code */
  1002. r = inb(port);
  1003. udelay(1);
  1004. outb(0x19, port);
  1005. udelay(1);
  1006. res = inb(port);
  1007. udelay(1);
  1008. outb(r, port);
  1009. udelay(1);
  1010. local_irq_restore(flags);
  1011. /* Fail */
  1012. if (res == 0x19) {
  1013. release_region(port, 2);
  1014. continue;
  1015. }
  1016. /* Passes the presence test */
  1017. r = inb(port + 1);
  1018. udelay(1);
  1019. /* Check port agrees with port set */
  1020. if ((r & 2) >> 1 == i)
  1021. qdi65_identify_port(r, res, port);
  1022. release_region(port, 2);
  1023. }
  1024. }
  1025. }
  1026. /**
  1027. * legacy_init - attach legacy interfaces
  1028. *
  1029. * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
  1030. * Right now we do not scan the ide0 and ide1 address but should do so
  1031. * for non PCI systems or systems with no PCI IDE legacy mode devices.
  1032. * If you fix that note there are special cases to consider like VLB
  1033. * drivers and CS5510/20.
  1034. */
  1035. static __init int legacy_init(void)
  1036. {
  1037. int i;
  1038. int ct = 0;
  1039. int primary = 0;
  1040. int secondary = 0;
  1041. int pci_present = 0;
  1042. struct legacy_probe *pl = &probe_list[0];
  1043. int slot = 0;
  1044. struct pci_dev *p = NULL;
  1045. for_each_pci_dev(p) {
  1046. int r;
  1047. /* Check for any overlap of the system ATA mappings. Native
  1048. mode controllers stuck on these addresses or some devices
  1049. in 'raid' mode won't be found by the storage class test */
  1050. for (r = 0; r < 6; r++) {
  1051. if (pci_resource_start(p, r) == 0x1f0)
  1052. primary = 1;
  1053. if (pci_resource_start(p, r) == 0x170)
  1054. secondary = 1;
  1055. }
  1056. /* Check for special cases */
  1057. legacy_check_special_cases(p, &primary, &secondary);
  1058. /* If PCI bus is present then don't probe for tertiary
  1059. legacy ports */
  1060. pci_present = 1;
  1061. }
  1062. if (winbond == 1)
  1063. winbond = 0x130; /* Default port, alt is 1B0 */
  1064. if (primary == 0 || all)
  1065. legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
  1066. if (secondary == 0 || all)
  1067. legacy_probe_add(0x170, 15, UNKNOWN, 0);
  1068. if (probe_all || !pci_present) {
  1069. /* ISA/VLB extra ports */
  1070. legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
  1071. legacy_probe_add(0x168, 10, UNKNOWN, 0);
  1072. legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
  1073. legacy_probe_add(0x160, 12, UNKNOWN, 0);
  1074. }
  1075. if (opti82c46x)
  1076. probe_opti_vlb();
  1077. if (qdi)
  1078. probe_qdi_vlb();
  1079. for (i = 0; i < NR_HOST; i++, pl++) {
  1080. if (pl->port == 0)
  1081. continue;
  1082. if (pl->type == UNKNOWN)
  1083. pl->type = probe_chip_type(pl);
  1084. pl->slot = slot++;
  1085. if (legacy_init_one(pl) == 0)
  1086. ct++;
  1087. }
  1088. if (ct != 0)
  1089. return 0;
  1090. return -ENODEV;
  1091. }
  1092. static __exit void legacy_exit(void)
  1093. {
  1094. int i;
  1095. for (i = 0; i < nr_legacy_host; i++) {
  1096. struct legacy_data *ld = &legacy_data[i];
  1097. ata_host_detach(legacy_host[i]);
  1098. platform_device_unregister(ld->platform_dev);
  1099. }
  1100. }
  1101. MODULE_AUTHOR("Alan Cox");
  1102. MODULE_DESCRIPTION("low-level driver for legacy ATA");
  1103. MODULE_LICENSE("GPL");
  1104. MODULE_VERSION(DRV_VERSION);
  1105. MODULE_ALIAS("pata_qdi");
  1106. MODULE_ALIAS("pata_winbond");
  1107. module_init(legacy_init);
  1108. module_exit(legacy_exit);