pata_artop.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_artop.c - ARTOP ATA controller driver
  4. *
  5. * (C) 2006 Red Hat
  6. * (C) 2007,2011 Bartlomiej Zolnierkiewicz
  7. *
  8. * Based in part on drivers/ide/pci/aec62xx.c
  9. * Copyright (C) 1999-2002 Andre Hedrick <[email protected]>
  10. * 865/865R fixes for Macintosh card version from a patch to the old
  11. * driver by Thibaut VARENE <[email protected]>
  12. * When setting the PCI latency we must set 0x80 or higher for burst
  13. * performance Alessandro Zummo <[email protected]>
  14. *
  15. * TODO
  16. * Investigate no_dsc on 850R
  17. * Clock detect
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/delay.h>
  24. #include <linux/device.h>
  25. #include <scsi/scsi_host.h>
  26. #include <linux/libata.h>
  27. #include <linux/ata.h>
  28. #define DRV_NAME "pata_artop"
  29. #define DRV_VERSION "0.4.8"
  30. /*
  31. * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
  32. * get PCI bus speed functionality we leave this as 0. Its a variable
  33. * for when we get the functionality and also for folks wanting to
  34. * test stuff.
  35. */
  36. static int clock = 0;
  37. /**
  38. * artop62x0_pre_reset - probe begin
  39. * @link: link
  40. * @deadline: deadline jiffies for the operation
  41. *
  42. * Nothing complicated needed here.
  43. */
  44. static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
  45. {
  46. static const struct pci_bits artop_enable_bits[] = {
  47. { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
  48. { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
  49. };
  50. struct ata_port *ap = link->ap;
  51. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  52. /* Odd numbered device ids are the units with enable bits. */
  53. if ((pdev->device & 1) &&
  54. !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
  55. return -ENOENT;
  56. return ata_sff_prereset(link, deadline);
  57. }
  58. /**
  59. * artop6260_cable_detect - identify cable type
  60. * @ap: Port
  61. *
  62. * Identify the cable type for the ARTOP interface in question
  63. */
  64. static int artop6260_cable_detect(struct ata_port *ap)
  65. {
  66. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  67. u8 tmp;
  68. pci_read_config_byte(pdev, 0x49, &tmp);
  69. if (tmp & (1 << ap->port_no))
  70. return ATA_CBL_PATA40;
  71. return ATA_CBL_PATA80;
  72. }
  73. /**
  74. * artop6210_load_piomode - Load a set of PATA PIO timings
  75. * @ap: Port whose timings we are configuring
  76. * @adev: Device
  77. * @pio: PIO mode
  78. *
  79. * Set PIO mode for device, in host controller PCI config space. This
  80. * is used both to set PIO timings in PIO mode and also to set the
  81. * matching PIO clocking for UDMA, as well as the MWDMA timings.
  82. *
  83. * LOCKING:
  84. * None (inherited from caller).
  85. */
  86. static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
  87. {
  88. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  89. int dn = adev->devno + 2 * ap->port_no;
  90. static const u16 timing[2][5] = {
  91. { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
  92. { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
  93. };
  94. /* Load the PIO timing active/recovery bits */
  95. pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
  96. }
  97. /**
  98. * artop6210_set_piomode - Initialize host controller PATA PIO timings
  99. * @ap: Port whose timings we are configuring
  100. * @adev: Device we are configuring
  101. *
  102. * Set PIO mode for device, in host controller PCI config space. For
  103. * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
  104. * the event UDMA is used the later call to set_dmamode will set the
  105. * bits as required.
  106. *
  107. * LOCKING:
  108. * None (inherited from caller).
  109. */
  110. static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
  111. {
  112. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  113. int dn = adev->devno + 2 * ap->port_no;
  114. u8 ultra;
  115. artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
  116. /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
  117. pci_read_config_byte(pdev, 0x54, &ultra);
  118. ultra &= ~(3 << (2 * dn));
  119. pci_write_config_byte(pdev, 0x54, ultra);
  120. }
  121. /**
  122. * artop6260_load_piomode - Initialize host controller PATA PIO timings
  123. * @ap: Port whose timings we are configuring
  124. * @adev: Device we are configuring
  125. * @pio: PIO mode
  126. *
  127. * Set PIO mode for device, in host controller PCI config space. The
  128. * ARTOP6260 and relatives store the timing data differently.
  129. *
  130. * LOCKING:
  131. * None (inherited from caller).
  132. */
  133. static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
  134. {
  135. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  136. int dn = adev->devno + 2 * ap->port_no;
  137. static const u8 timing[2][5] = {
  138. { 0x00, 0x0A, 0x08, 0x33, 0x31 },
  139. { 0x70, 0x7A, 0x78, 0x43, 0x41 }
  140. };
  141. /* Load the PIO timing active/recovery bits */
  142. pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
  143. }
  144. /**
  145. * artop6260_set_piomode - Initialize host controller PATA PIO timings
  146. * @ap: Port whose timings we are configuring
  147. * @adev: Device we are configuring
  148. *
  149. * Set PIO mode for device, in host controller PCI config space. For
  150. * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
  151. * the event UDMA is used the later call to set_dmamode will set the
  152. * bits as required.
  153. *
  154. * LOCKING:
  155. * None (inherited from caller).
  156. */
  157. static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
  158. {
  159. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  160. u8 ultra;
  161. artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
  162. /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
  163. pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
  164. ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
  165. pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
  166. }
  167. /**
  168. * artop6210_set_dmamode - Initialize host controller PATA PIO timings
  169. * @ap: Port whose timings we are configuring
  170. * @adev: Device whose timings we are configuring
  171. *
  172. * Set DMA mode for device, in host controller PCI config space.
  173. *
  174. * LOCKING:
  175. * None (inherited from caller).
  176. */
  177. static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  178. {
  179. unsigned int pio;
  180. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  181. int dn = adev->devno + 2 * ap->port_no;
  182. u8 ultra;
  183. if (adev->dma_mode == XFER_MW_DMA_0)
  184. pio = 1;
  185. else
  186. pio = 4;
  187. /* Load the PIO timing active/recovery bits */
  188. artop6210_load_piomode(ap, adev, pio);
  189. pci_read_config_byte(pdev, 0x54, &ultra);
  190. ultra &= ~(3 << (2 * dn));
  191. /* Add ultra DMA bits if in UDMA mode */
  192. if (adev->dma_mode >= XFER_UDMA_0) {
  193. u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
  194. if (mode == 0)
  195. mode = 1;
  196. ultra |= (mode << (2 * dn));
  197. }
  198. pci_write_config_byte(pdev, 0x54, ultra);
  199. }
  200. /**
  201. * artop6260_set_dmamode - Initialize host controller PATA PIO timings
  202. * @ap: Port whose timings we are configuring
  203. * @adev: Device we are configuring
  204. *
  205. * Set DMA mode for device, in host controller PCI config space. The
  206. * ARTOP6260 and relatives store the timing data differently.
  207. *
  208. * LOCKING:
  209. * None (inherited from caller).
  210. */
  211. static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  212. {
  213. unsigned int pio;
  214. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  215. u8 ultra;
  216. if (adev->dma_mode == XFER_MW_DMA_0)
  217. pio = 1;
  218. else
  219. pio = 4;
  220. /* Load the PIO timing active/recovery bits */
  221. artop6260_load_piomode(ap, adev, pio);
  222. /* Add ultra DMA bits if in UDMA mode */
  223. pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
  224. ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
  225. if (adev->dma_mode >= XFER_UDMA_0) {
  226. u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
  227. if (mode == 0)
  228. mode = 1;
  229. ultra |= (mode << (4 * adev->devno));
  230. }
  231. pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
  232. }
  233. /**
  234. * artop6210_qc_defer - implement serialization
  235. * @qc: command
  236. *
  237. * Issue commands per host on this chip.
  238. */
  239. static int artop6210_qc_defer(struct ata_queued_cmd *qc)
  240. {
  241. struct ata_host *host = qc->ap->host;
  242. struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
  243. int rc;
  244. /* First apply the usual rules */
  245. rc = ata_std_qc_defer(qc);
  246. if (rc != 0)
  247. return rc;
  248. /* Now apply serialization rules. Only allow a command if the
  249. other channel state machine is idle */
  250. if (alt && alt->qc_active)
  251. return ATA_DEFER_PORT;
  252. return 0;
  253. }
  254. static struct scsi_host_template artop_sht = {
  255. ATA_BMDMA_SHT(DRV_NAME),
  256. };
  257. static struct ata_port_operations artop6210_ops = {
  258. .inherits = &ata_bmdma_port_ops,
  259. .cable_detect = ata_cable_40wire,
  260. .set_piomode = artop6210_set_piomode,
  261. .set_dmamode = artop6210_set_dmamode,
  262. .prereset = artop62x0_pre_reset,
  263. .qc_defer = artop6210_qc_defer,
  264. };
  265. static struct ata_port_operations artop6260_ops = {
  266. .inherits = &ata_bmdma_port_ops,
  267. .cable_detect = artop6260_cable_detect,
  268. .set_piomode = artop6260_set_piomode,
  269. .set_dmamode = artop6260_set_dmamode,
  270. .prereset = artop62x0_pre_reset,
  271. };
  272. static void atp8xx_fixup(struct pci_dev *pdev)
  273. {
  274. u8 reg;
  275. switch (pdev->device) {
  276. case 0x0005:
  277. /* BIOS may have left us in UDMA, clear it before libata probe */
  278. pci_write_config_byte(pdev, 0x54, 0);
  279. break;
  280. case 0x0008:
  281. case 0x0009:
  282. /* Mac systems come up with some registers not set as we
  283. will need them */
  284. /* Clear reset & test bits */
  285. pci_read_config_byte(pdev, 0x49, &reg);
  286. pci_write_config_byte(pdev, 0x49, reg & ~0x30);
  287. /* PCI latency must be > 0x80 for burst mode, tweak it
  288. * if required.
  289. */
  290. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
  291. if (reg <= 0x80)
  292. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
  293. /* Enable IRQ output and burst mode */
  294. pci_read_config_byte(pdev, 0x4a, &reg);
  295. pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
  296. break;
  297. }
  298. }
  299. /**
  300. * artop_init_one - Register ARTOP ATA PCI device with kernel services
  301. * @pdev: PCI device to register
  302. * @id: PCI device ID
  303. *
  304. * Called from kernel PCI layer.
  305. *
  306. * LOCKING:
  307. * Inherited from PCI layer (may sleep).
  308. *
  309. * RETURNS:
  310. * Zero on success, or -ERRNO value.
  311. */
  312. static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
  313. {
  314. static const struct ata_port_info info_6210 = {
  315. .flags = ATA_FLAG_SLAVE_POSS,
  316. .pio_mask = ATA_PIO4,
  317. .mwdma_mask = ATA_MWDMA2,
  318. .udma_mask = ATA_UDMA2,
  319. .port_ops = &artop6210_ops,
  320. };
  321. static const struct ata_port_info info_626x = {
  322. .flags = ATA_FLAG_SLAVE_POSS,
  323. .pio_mask = ATA_PIO4,
  324. .mwdma_mask = ATA_MWDMA2,
  325. .udma_mask = ATA_UDMA4,
  326. .port_ops = &artop6260_ops,
  327. };
  328. static const struct ata_port_info info_628x = {
  329. .flags = ATA_FLAG_SLAVE_POSS,
  330. .pio_mask = ATA_PIO4,
  331. .mwdma_mask = ATA_MWDMA2,
  332. .udma_mask = ATA_UDMA5,
  333. .port_ops = &artop6260_ops,
  334. };
  335. static const struct ata_port_info info_628x_fast = {
  336. .flags = ATA_FLAG_SLAVE_POSS,
  337. .pio_mask = ATA_PIO4,
  338. .mwdma_mask = ATA_MWDMA2,
  339. .udma_mask = ATA_UDMA6,
  340. .port_ops = &artop6260_ops,
  341. };
  342. const struct ata_port_info *ppi[] = { NULL, NULL };
  343. int rc;
  344. ata_print_version_once(&pdev->dev, DRV_VERSION);
  345. rc = pcim_enable_device(pdev);
  346. if (rc)
  347. return rc;
  348. switch (id->driver_data) {
  349. case 0: /* 6210 variant */
  350. ppi[0] = &info_6210;
  351. break;
  352. case 1: /* 6260 */
  353. ppi[0] = &info_626x;
  354. break;
  355. case 2: /* 6280 or 6280 + fast */
  356. if (inb(pci_resource_start(pdev, 4)) & 0x10)
  357. ppi[0] = &info_628x_fast;
  358. else
  359. ppi[0] = &info_628x;
  360. break;
  361. }
  362. BUG_ON(ppi[0] == NULL);
  363. atp8xx_fixup(pdev);
  364. return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
  365. }
  366. static const struct pci_device_id artop_pci_tbl[] = {
  367. { PCI_VDEVICE(ARTOP, 0x0005), 0 },
  368. { PCI_VDEVICE(ARTOP, 0x0006), 1 },
  369. { PCI_VDEVICE(ARTOP, 0x0007), 1 },
  370. { PCI_VDEVICE(ARTOP, 0x0008), 2 },
  371. { PCI_VDEVICE(ARTOP, 0x0009), 2 },
  372. { } /* terminate list */
  373. };
  374. #ifdef CONFIG_PM_SLEEP
  375. static int atp8xx_reinit_one(struct pci_dev *pdev)
  376. {
  377. struct ata_host *host = pci_get_drvdata(pdev);
  378. int rc;
  379. rc = ata_pci_device_do_resume(pdev);
  380. if (rc)
  381. return rc;
  382. atp8xx_fixup(pdev);
  383. ata_host_resume(host);
  384. return 0;
  385. }
  386. #endif
  387. static struct pci_driver artop_pci_driver = {
  388. .name = DRV_NAME,
  389. .id_table = artop_pci_tbl,
  390. .probe = artop_init_one,
  391. .remove = ata_pci_remove_one,
  392. #ifdef CONFIG_PM_SLEEP
  393. .suspend = ata_pci_device_suspend,
  394. .resume = atp8xx_reinit_one,
  395. #endif
  396. };
  397. module_pci_driver(artop_pci_driver);
  398. MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
  399. MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
  400. MODULE_LICENSE("GPL");
  401. MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
  402. MODULE_VERSION(DRV_VERSION);