ahci_tegra.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/ata/ahci_tegra.c
  4. *
  5. * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Author:
  8. * Mikko Perttunen <[email protected]>
  9. */
  10. #include <linux/ahci_platform.h>
  11. #include <linux/errno.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/reset.h>
  18. #include <soc/tegra/fuse.h>
  19. #include <soc/tegra/pmc.h>
  20. #include "ahci.h"
  21. #define DRV_NAME "tegra-ahci"
  22. #define SATA_CONFIGURATION_0 0x180
  23. #define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
  24. #define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
  25. #define SCFG_OFFSET 0x1000
  26. #define T_SATA0_CFG_1 0x04
  27. #define T_SATA0_CFG_1_IO_SPACE BIT(0)
  28. #define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
  29. #define T_SATA0_CFG_1_BUS_MASTER BIT(2)
  30. #define T_SATA0_CFG_1_SERR BIT(8)
  31. #define T_SATA0_CFG_9 0x24
  32. #define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
  33. #define SATA_FPCI_BAR5 0x94
  34. #define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
  35. #define SATA_FPCI_BAR5_START (0x0040020 << 4)
  36. #define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
  37. #define SATA_INTR_MASK 0x188
  38. #define SATA_INTR_MASK_IP_INT_MASK BIT(16)
  39. #define T_SATA0_CFG_35 0x94
  40. #define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
  41. #define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
  42. #define T_SATA0_AHCI_IDP1 0x98
  43. #define T_SATA0_AHCI_IDP1_DATA (0x400040)
  44. #define T_SATA0_CFG_PHY_1 0x12c
  45. #define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
  46. #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
  47. #define T_SATA0_NVOOB 0x114
  48. #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
  49. #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
  50. #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
  51. #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
  52. #define T_SATA_CFG_PHY_0 0x120
  53. #define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
  54. #define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
  55. #define T_SATA0_CFG2NVOOB_2 0x134
  56. #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
  57. #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
  58. #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
  59. #define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
  60. #define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
  61. #define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
  62. #define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
  63. #define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
  64. #define T_SATA0_BKDOOR_CC 0x4a4
  65. #define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
  66. #define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
  67. #define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
  68. #define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
  69. #define T_SATA0_CFG_SATA 0x54c
  70. #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
  71. #define T_SATA0_CFG_MISC 0x550
  72. #define T_SATA0_INDEX 0x680
  73. #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
  74. #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
  75. #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
  76. #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
  77. #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
  78. #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
  79. #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
  80. #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
  81. #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
  82. #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
  83. #define T_SATA0_CHX_PHY_CTRL2 0x69c
  84. #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
  85. #define T_SATA0_CHX_PHY_CTRL11 0x6d0
  86. #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
  87. #define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
  88. #define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
  89. #define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
  90. #define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
  91. #define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
  92. #define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
  93. #define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
  94. #define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
  95. /* AUX Registers */
  96. #define SATA_AUX_MISC_CNTL_1_0 0x8
  97. #define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
  98. #define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
  99. #define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
  100. #define SATA_AUX_RX_STAT_INT_0 0xc
  101. #define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
  102. #define SATA_AUX_SPARE_CFG0_0 0x18
  103. #define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
  104. #define FUSE_SATA_CALIB 0x124
  105. #define FUSE_SATA_CALIB_MASK 0x3
  106. struct sata_pad_calibration {
  107. u8 gen1_tx_amp;
  108. u8 gen1_tx_peak;
  109. u8 gen2_tx_amp;
  110. u8 gen2_tx_peak;
  111. };
  112. static const struct sata_pad_calibration tegra124_pad_calibration[] = {
  113. {0x18, 0x04, 0x18, 0x0a},
  114. {0x0e, 0x04, 0x14, 0x0a},
  115. {0x0e, 0x07, 0x1a, 0x0e},
  116. {0x14, 0x0e, 0x1a, 0x0e},
  117. };
  118. struct tegra_ahci_ops {
  119. int (*init)(struct ahci_host_priv *hpriv);
  120. };
  121. struct tegra_ahci_regs {
  122. unsigned int nvoob_comma_cnt_mask;
  123. unsigned int nvoob_comma_cnt_val;
  124. };
  125. struct tegra_ahci_soc {
  126. const char *const *supply_names;
  127. u32 num_supplies;
  128. bool supports_devslp;
  129. bool has_sata_oob_rst;
  130. const struct tegra_ahci_ops *ops;
  131. const struct tegra_ahci_regs *regs;
  132. };
  133. struct tegra_ahci_priv {
  134. struct platform_device *pdev;
  135. void __iomem *sata_regs;
  136. void __iomem *sata_aux_regs;
  137. struct reset_control *sata_rst;
  138. struct reset_control *sata_oob_rst;
  139. struct reset_control *sata_cold_rst;
  140. /* Needs special handling, cannot use ahci_platform */
  141. struct clk *sata_clk;
  142. struct regulator_bulk_data *supplies;
  143. const struct tegra_ahci_soc *soc;
  144. };
  145. static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
  146. {
  147. struct tegra_ahci_priv *tegra = hpriv->plat_data;
  148. u32 val;
  149. if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
  150. val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
  151. val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
  152. writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
  153. }
  154. }
  155. static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
  156. {
  157. struct tegra_ahci_priv *tegra = hpriv->plat_data;
  158. struct sata_pad_calibration calib;
  159. int ret;
  160. u32 val;
  161. /* Pad calibration */
  162. ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
  163. if (ret)
  164. return ret;
  165. calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
  166. writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
  167. val = readl(tegra->sata_regs +
  168. SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
  169. val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
  170. val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
  171. val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
  172. val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
  173. writel(val, tegra->sata_regs + SCFG_OFFSET +
  174. T_SATA0_CHX_PHY_CTRL1_GEN1);
  175. val = readl(tegra->sata_regs +
  176. SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
  177. val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
  178. val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
  179. val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
  180. val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
  181. writel(val, tegra->sata_regs + SCFG_OFFSET +
  182. T_SATA0_CHX_PHY_CTRL1_GEN2);
  183. writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
  184. tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
  185. writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
  186. tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
  187. writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
  188. return 0;
  189. }
  190. static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
  191. {
  192. struct tegra_ahci_priv *tegra = hpriv->plat_data;
  193. int ret;
  194. ret = regulator_bulk_enable(tegra->soc->num_supplies,
  195. tegra->supplies);
  196. if (ret)
  197. return ret;
  198. if (!tegra->pdev->dev.pm_domain) {
  199. ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
  200. tegra->sata_clk,
  201. tegra->sata_rst);
  202. if (ret)
  203. goto disable_regulators;
  204. }
  205. reset_control_assert(tegra->sata_oob_rst);
  206. reset_control_assert(tegra->sata_cold_rst);
  207. ret = ahci_platform_enable_resources(hpriv);
  208. if (ret)
  209. goto disable_power;
  210. reset_control_deassert(tegra->sata_cold_rst);
  211. reset_control_deassert(tegra->sata_oob_rst);
  212. return 0;
  213. disable_power:
  214. clk_disable_unprepare(tegra->sata_clk);
  215. if (!tegra->pdev->dev.pm_domain)
  216. tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
  217. disable_regulators:
  218. regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
  219. return ret;
  220. }
  221. static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
  222. {
  223. struct tegra_ahci_priv *tegra = hpriv->plat_data;
  224. ahci_platform_disable_resources(hpriv);
  225. reset_control_assert(tegra->sata_rst);
  226. reset_control_assert(tegra->sata_oob_rst);
  227. reset_control_assert(tegra->sata_cold_rst);
  228. clk_disable_unprepare(tegra->sata_clk);
  229. if (!tegra->pdev->dev.pm_domain)
  230. tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
  231. regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
  232. }
  233. static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
  234. {
  235. struct tegra_ahci_priv *tegra = hpriv->plat_data;
  236. int ret;
  237. u32 val;
  238. ret = tegra_ahci_power_on(hpriv);
  239. if (ret) {
  240. dev_err(&tegra->pdev->dev,
  241. "failed to power on AHCI controller: %d\n", ret);
  242. return ret;
  243. }
  244. /*
  245. * Program the following SATA IPFS registers to allow SW accesses to
  246. * SATA's MMIO register range.
  247. */
  248. val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
  249. val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
  250. val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
  251. writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
  252. /* Program the following SATA IPFS register to enable the SATA */
  253. val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
  254. val |= SATA_CONFIGURATION_0_EN_FPCI;
  255. writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
  256. /* Electrical settings for better link stability */
  257. val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
  258. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
  259. val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
  260. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
  261. val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
  262. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
  263. val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
  264. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
  265. /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
  266. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
  267. val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
  268. val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
  269. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
  270. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
  271. val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask |
  272. T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
  273. T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
  274. val |= (tegra->soc->regs->nvoob_comma_cnt_val |
  275. T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
  276. T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
  277. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
  278. /*
  279. * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
  280. */
  281. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
  282. val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
  283. val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
  284. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
  285. if (tegra->soc->ops && tegra->soc->ops->init)
  286. tegra->soc->ops->init(hpriv);
  287. /*
  288. * Program the following SATA configuration registers to
  289. * initialize SATA
  290. */
  291. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
  292. val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
  293. T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
  294. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
  295. val = T_SATA0_CFG_9_BASE_ADDRESS;
  296. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
  297. /* Program Class Code and Programming interface for SATA */
  298. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
  299. val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
  300. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
  301. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
  302. val &=
  303. ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
  304. T_SATA0_BKDOOR_CC_PROG_IF_MASK);
  305. val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
  306. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
  307. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
  308. val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
  309. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
  310. /* Enabling LPM capabilities through Backdoor Programming */
  311. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
  312. val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
  313. T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
  314. T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
  315. T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
  316. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
  317. /* SATA Second Level Clock Gating configuration
  318. * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
  319. * IDDQ Signals
  320. */
  321. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
  322. val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
  323. val |= T_SATA0_CFG_35_IDP_INDEX;
  324. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
  325. val = T_SATA0_AHCI_IDP1_DATA;
  326. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
  327. val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
  328. val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
  329. T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
  330. writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
  331. /* Enabling IPFS Clock Gating */
  332. val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
  333. val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
  334. writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
  335. tegra_ahci_handle_quirks(hpriv);
  336. /* Unmask SATA interrupts */
  337. val = readl(tegra->sata_regs + SATA_INTR_MASK);
  338. val |= SATA_INTR_MASK_IP_INT_MASK;
  339. writel(val, tegra->sata_regs + SATA_INTR_MASK);
  340. return 0;
  341. }
  342. static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
  343. {
  344. tegra_ahci_power_off(hpriv);
  345. }
  346. static void tegra_ahci_host_stop(struct ata_host *host)
  347. {
  348. struct ahci_host_priv *hpriv = host->private_data;
  349. tegra_ahci_controller_deinit(hpriv);
  350. }
  351. static struct ata_port_operations ahci_tegra_port_ops = {
  352. .inherits = &ahci_ops,
  353. .host_stop = tegra_ahci_host_stop,
  354. };
  355. static const struct ata_port_info ahci_tegra_port_info = {
  356. .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
  357. .pio_mask = ATA_PIO4,
  358. .udma_mask = ATA_UDMA6,
  359. .port_ops = &ahci_tegra_port_ops,
  360. };
  361. static const char *const tegra124_supply_names[] = {
  362. "avdd", "hvdd", "vddio", "target-5v", "target-12v"
  363. };
  364. static const struct tegra_ahci_ops tegra124_ahci_ops = {
  365. .init = tegra124_ahci_init,
  366. };
  367. static const struct tegra_ahci_regs tegra124_ahci_regs = {
  368. .nvoob_comma_cnt_mask = GENMASK(30, 28),
  369. .nvoob_comma_cnt_val = (7 << 28),
  370. };
  371. static const struct tegra_ahci_soc tegra124_ahci_soc = {
  372. .supply_names = tegra124_supply_names,
  373. .num_supplies = ARRAY_SIZE(tegra124_supply_names),
  374. .supports_devslp = false,
  375. .has_sata_oob_rst = true,
  376. .ops = &tegra124_ahci_ops,
  377. .regs = &tegra124_ahci_regs,
  378. };
  379. static const struct tegra_ahci_soc tegra210_ahci_soc = {
  380. .supports_devslp = false,
  381. .has_sata_oob_rst = true,
  382. .regs = &tegra124_ahci_regs,
  383. };
  384. static const struct tegra_ahci_regs tegra186_ahci_regs = {
  385. .nvoob_comma_cnt_mask = GENMASK(23, 16),
  386. .nvoob_comma_cnt_val = (7 << 16),
  387. };
  388. static const struct tegra_ahci_soc tegra186_ahci_soc = {
  389. .supports_devslp = false,
  390. .has_sata_oob_rst = false,
  391. .regs = &tegra186_ahci_regs,
  392. };
  393. static const struct of_device_id tegra_ahci_of_match[] = {
  394. {
  395. .compatible = "nvidia,tegra124-ahci",
  396. .data = &tegra124_ahci_soc
  397. },
  398. {
  399. .compatible = "nvidia,tegra210-ahci",
  400. .data = &tegra210_ahci_soc
  401. },
  402. {
  403. .compatible = "nvidia,tegra186-ahci",
  404. .data = &tegra186_ahci_soc
  405. },
  406. {}
  407. };
  408. MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
  409. static struct scsi_host_template ahci_platform_sht = {
  410. AHCI_SHT(DRV_NAME),
  411. };
  412. static int tegra_ahci_probe(struct platform_device *pdev)
  413. {
  414. struct ahci_host_priv *hpriv;
  415. struct tegra_ahci_priv *tegra;
  416. struct resource *res;
  417. int ret;
  418. hpriv = ahci_platform_get_resources(pdev, 0);
  419. if (IS_ERR(hpriv))
  420. return PTR_ERR(hpriv);
  421. tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
  422. if (!tegra)
  423. return -ENOMEM;
  424. hpriv->plat_data = tegra;
  425. tegra->pdev = pdev;
  426. tegra->soc = of_device_get_match_data(&pdev->dev);
  427. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  428. tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
  429. if (IS_ERR(tegra->sata_regs))
  430. return PTR_ERR(tegra->sata_regs);
  431. /*
  432. * AUX registers is optional.
  433. */
  434. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  435. if (res) {
  436. tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
  437. if (IS_ERR(tegra->sata_aux_regs))
  438. return PTR_ERR(tegra->sata_aux_regs);
  439. }
  440. tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
  441. if (IS_ERR(tegra->sata_rst)) {
  442. dev_err(&pdev->dev, "Failed to get sata reset\n");
  443. return PTR_ERR(tegra->sata_rst);
  444. }
  445. if (tegra->soc->has_sata_oob_rst) {
  446. tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev,
  447. "sata-oob");
  448. if (IS_ERR(tegra->sata_oob_rst)) {
  449. dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
  450. return PTR_ERR(tegra->sata_oob_rst);
  451. }
  452. }
  453. tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
  454. if (IS_ERR(tegra->sata_cold_rst)) {
  455. dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
  456. return PTR_ERR(tegra->sata_cold_rst);
  457. }
  458. tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
  459. if (IS_ERR(tegra->sata_clk)) {
  460. dev_err(&pdev->dev, "Failed to get sata clock\n");
  461. return PTR_ERR(tegra->sata_clk);
  462. }
  463. tegra->supplies = devm_kcalloc(&pdev->dev,
  464. tegra->soc->num_supplies,
  465. sizeof(*tegra->supplies), GFP_KERNEL);
  466. if (!tegra->supplies)
  467. return -ENOMEM;
  468. regulator_bulk_set_supply_names(tegra->supplies,
  469. tegra->soc->supply_names,
  470. tegra->soc->num_supplies);
  471. ret = devm_regulator_bulk_get(&pdev->dev,
  472. tegra->soc->num_supplies,
  473. tegra->supplies);
  474. if (ret) {
  475. dev_err(&pdev->dev, "Failed to get regulators\n");
  476. return ret;
  477. }
  478. ret = tegra_ahci_controller_init(hpriv);
  479. if (ret)
  480. return ret;
  481. ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
  482. &ahci_platform_sht);
  483. if (ret)
  484. goto deinit_controller;
  485. return 0;
  486. deinit_controller:
  487. tegra_ahci_controller_deinit(hpriv);
  488. return ret;
  489. };
  490. static struct platform_driver tegra_ahci_driver = {
  491. .probe = tegra_ahci_probe,
  492. .remove = ata_platform_remove_one,
  493. .driver = {
  494. .name = DRV_NAME,
  495. .of_match_table = tegra_ahci_of_match,
  496. },
  497. /* LP0 suspend support not implemented */
  498. };
  499. module_platform_driver(tegra_ahci_driver);
  500. MODULE_AUTHOR("Mikko Perttunen <[email protected]>");
  501. MODULE_DESCRIPTION("Tegra AHCI SATA driver");
  502. MODULE_LICENSE("GPL v2");