ahci_qoriq.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale QorIQ AHCI SATA platform driver
  4. *
  5. * Copyright 2015 Freescale, Inc.
  6. * Tang Yuantian <[email protected]>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/pm.h>
  12. #include <linux/ahci_platform.h>
  13. #include <linux/device.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/libata.h>
  19. #include "ahci.h"
  20. #define DRV_NAME "ahci-qoriq"
  21. /* port register definition */
  22. #define PORT_PHY1 0xA8
  23. #define PORT_PHY2 0xAC
  24. #define PORT_PHY3 0xB0
  25. #define PORT_PHY4 0xB4
  26. #define PORT_PHY5 0xB8
  27. #define PORT_AXICC 0xBC
  28. #define PORT_TRANS 0xC8
  29. /* port register default value */
  30. #define AHCI_PORT_PHY_1_CFG 0xa003fffe
  31. #define AHCI_PORT_PHY2_CFG 0x28184d1f
  32. #define AHCI_PORT_PHY3_CFG 0x0e081509
  33. #define AHCI_PORT_TRANS_CFG 0x08000029
  34. #define AHCI_PORT_AXICC_CFG 0x3fffffff
  35. /* for ls1021a */
  36. #define LS1021A_PORT_PHY2 0x28183414
  37. #define LS1021A_PORT_PHY3 0x0e080e06
  38. #define LS1021A_PORT_PHY4 0x064a080b
  39. #define LS1021A_PORT_PHY5 0x2aa86470
  40. #define LS1021A_AXICC_ADDR 0xC0
  41. #define SATA_ECC_DISABLE 0x00020000
  42. #define ECC_DIS_ARMV8_CH2 0x80000000
  43. #define ECC_DIS_LS1088A 0x40000000
  44. enum ahci_qoriq_type {
  45. AHCI_LS1021A,
  46. AHCI_LS1028A,
  47. AHCI_LS1043A,
  48. AHCI_LS2080A,
  49. AHCI_LS1046A,
  50. AHCI_LS1088A,
  51. AHCI_LS2088A,
  52. AHCI_LX2160A,
  53. };
  54. struct ahci_qoriq_priv {
  55. struct ccsr_ahci *reg_base;
  56. enum ahci_qoriq_type type;
  57. void __iomem *ecc_addr;
  58. bool is_dmacoherent;
  59. };
  60. static bool ecc_initialized;
  61. static const struct of_device_id ahci_qoriq_of_match[] = {
  62. { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  63. { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
  64. { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  65. { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  66. { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
  67. { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
  68. { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
  69. { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
  70. { /* sentinel */ }
  71. };
  72. MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  73. static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
  74. {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
  75. { }
  76. };
  77. MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
  78. static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  79. unsigned long deadline)
  80. {
  81. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  82. void __iomem *port_mmio = ahci_port_base(link->ap);
  83. u32 px_cmd, px_is, px_val;
  84. struct ata_port *ap = link->ap;
  85. struct ahci_port_priv *pp = ap->private_data;
  86. struct ahci_host_priv *hpriv = ap->host->private_data;
  87. struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
  88. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  89. struct ata_taskfile tf;
  90. bool online;
  91. int rc;
  92. bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
  93. hpriv->stop_engine(ap);
  94. /*
  95. * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
  96. * A-009042: The device detection initialization sequence
  97. * mistakenly resets some registers.
  98. *
  99. * Workaround for this is:
  100. * The software should read and store PxCMD and PxIS values
  101. * before issuing the device detection initialization sequence.
  102. * After the sequence is complete, software should restore the
  103. * PxCMD and PxIS with the stored values.
  104. */
  105. if (ls1021a_workaround) {
  106. px_cmd = readl(port_mmio + PORT_CMD);
  107. px_is = readl(port_mmio + PORT_IRQ_STAT);
  108. }
  109. /* clear D2H reception area to properly wait for D2H FIS */
  110. ata_tf_init(link->device, &tf);
  111. tf.status = ATA_BUSY;
  112. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  113. rc = sata_link_hardreset(link, timing, deadline, &online,
  114. ahci_check_ready);
  115. /* restore the PxCMD and PxIS on ls1021 */
  116. if (ls1021a_workaround) {
  117. px_val = readl(port_mmio + PORT_CMD);
  118. if (px_val != px_cmd)
  119. writel(px_cmd, port_mmio + PORT_CMD);
  120. px_val = readl(port_mmio + PORT_IRQ_STAT);
  121. if (px_val != px_is)
  122. writel(px_is, port_mmio + PORT_IRQ_STAT);
  123. }
  124. hpriv->start_engine(ap);
  125. if (online)
  126. *class = ahci_dev_classify(ap);
  127. return rc;
  128. }
  129. static struct ata_port_operations ahci_qoriq_ops = {
  130. .inherits = &ahci_ops,
  131. .hardreset = ahci_qoriq_hardreset,
  132. };
  133. static const struct ata_port_info ahci_qoriq_port_info = {
  134. .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
  135. .pio_mask = ATA_PIO4,
  136. .udma_mask = ATA_UDMA6,
  137. .port_ops = &ahci_qoriq_ops,
  138. };
  139. static struct scsi_host_template ahci_qoriq_sht = {
  140. AHCI_SHT(DRV_NAME),
  141. };
  142. static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
  143. {
  144. struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
  145. void __iomem *reg_base = hpriv->mmio;
  146. switch (qpriv->type) {
  147. case AHCI_LS1021A:
  148. if (!(qpriv->ecc_addr || ecc_initialized))
  149. return -EINVAL;
  150. else if (qpriv->ecc_addr && !ecc_initialized)
  151. writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
  152. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  153. writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
  154. writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
  155. writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
  156. writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
  157. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  158. if (qpriv->is_dmacoherent)
  159. writel(AHCI_PORT_AXICC_CFG,
  160. reg_base + LS1021A_AXICC_ADDR);
  161. break;
  162. case AHCI_LS1043A:
  163. if (!(qpriv->ecc_addr || ecc_initialized))
  164. return -EINVAL;
  165. else if (qpriv->ecc_addr && !ecc_initialized)
  166. writel(readl(qpriv->ecc_addr) |
  167. ECC_DIS_ARMV8_CH2,
  168. qpriv->ecc_addr);
  169. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  170. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  171. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  172. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  173. if (qpriv->is_dmacoherent)
  174. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  175. break;
  176. case AHCI_LS2080A:
  177. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  178. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  179. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  180. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  181. if (qpriv->is_dmacoherent)
  182. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  183. break;
  184. case AHCI_LS1046A:
  185. if (!(qpriv->ecc_addr || ecc_initialized))
  186. return -EINVAL;
  187. else if (qpriv->ecc_addr && !ecc_initialized)
  188. writel(readl(qpriv->ecc_addr) |
  189. ECC_DIS_ARMV8_CH2,
  190. qpriv->ecc_addr);
  191. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  192. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  193. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  194. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  195. if (qpriv->is_dmacoherent)
  196. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  197. break;
  198. case AHCI_LS1028A:
  199. case AHCI_LS1088A:
  200. case AHCI_LX2160A:
  201. if (!(qpriv->ecc_addr || ecc_initialized))
  202. return -EINVAL;
  203. else if (qpriv->ecc_addr && !ecc_initialized)
  204. writel(readl(qpriv->ecc_addr) |
  205. ECC_DIS_LS1088A,
  206. qpriv->ecc_addr);
  207. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  208. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  209. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  210. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  211. if (qpriv->is_dmacoherent)
  212. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  213. break;
  214. case AHCI_LS2088A:
  215. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  216. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  217. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  218. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  219. if (qpriv->is_dmacoherent)
  220. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  221. break;
  222. }
  223. ecc_initialized = true;
  224. return 0;
  225. }
  226. static int ahci_qoriq_probe(struct platform_device *pdev)
  227. {
  228. struct device_node *np = pdev->dev.of_node;
  229. const struct acpi_device_id *acpi_id;
  230. struct device *dev = &pdev->dev;
  231. struct ahci_host_priv *hpriv;
  232. struct ahci_qoriq_priv *qoriq_priv;
  233. const struct of_device_id *of_id;
  234. struct resource *res;
  235. int rc;
  236. hpriv = ahci_platform_get_resources(pdev, 0);
  237. if (IS_ERR(hpriv))
  238. return PTR_ERR(hpriv);
  239. of_id = of_match_node(ahci_qoriq_of_match, np);
  240. acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
  241. if (!(of_id || acpi_id))
  242. return -ENODEV;
  243. qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
  244. if (!qoriq_priv)
  245. return -ENOMEM;
  246. if (of_id)
  247. qoriq_priv->type = (unsigned long)of_id->data;
  248. else
  249. qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
  250. if (unlikely(!ecc_initialized)) {
  251. res = platform_get_resource_byname(pdev,
  252. IORESOURCE_MEM,
  253. "sata-ecc");
  254. if (res) {
  255. qoriq_priv->ecc_addr =
  256. devm_ioremap_resource(dev, res);
  257. if (IS_ERR(qoriq_priv->ecc_addr))
  258. return PTR_ERR(qoriq_priv->ecc_addr);
  259. }
  260. }
  261. if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
  262. qoriq_priv->is_dmacoherent = true;
  263. rc = ahci_platform_enable_resources(hpriv);
  264. if (rc)
  265. return rc;
  266. hpriv->plat_data = qoriq_priv;
  267. rc = ahci_qoriq_phy_init(hpriv);
  268. if (rc)
  269. goto disable_resources;
  270. rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
  271. &ahci_qoriq_sht);
  272. if (rc)
  273. goto disable_resources;
  274. return 0;
  275. disable_resources:
  276. ahci_platform_disable_resources(hpriv);
  277. return rc;
  278. }
  279. #ifdef CONFIG_PM_SLEEP
  280. static int ahci_qoriq_resume(struct device *dev)
  281. {
  282. struct ata_host *host = dev_get_drvdata(dev);
  283. struct ahci_host_priv *hpriv = host->private_data;
  284. int rc;
  285. rc = ahci_platform_enable_resources(hpriv);
  286. if (rc)
  287. return rc;
  288. rc = ahci_qoriq_phy_init(hpriv);
  289. if (rc)
  290. goto disable_resources;
  291. rc = ahci_platform_resume_host(dev);
  292. if (rc)
  293. goto disable_resources;
  294. /* We resumed so update PM runtime state */
  295. pm_runtime_disable(dev);
  296. pm_runtime_set_active(dev);
  297. pm_runtime_enable(dev);
  298. return 0;
  299. disable_resources:
  300. ahci_platform_disable_resources(hpriv);
  301. return rc;
  302. }
  303. #endif
  304. static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
  305. ahci_qoriq_resume);
  306. static struct platform_driver ahci_qoriq_driver = {
  307. .probe = ahci_qoriq_probe,
  308. .remove = ata_platform_remove_one,
  309. .driver = {
  310. .name = DRV_NAME,
  311. .of_match_table = ahci_qoriq_of_match,
  312. .acpi_match_table = ahci_qoriq_acpi_match,
  313. .pm = &ahci_qoriq_pm_ops,
  314. },
  315. };
  316. module_platform_driver(ahci_qoriq_driver);
  317. MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
  318. MODULE_AUTHOR("Tang Yuantian <[email protected]>");
  319. MODULE_LICENSE("GPL");