ahci_da850.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DaVinci DA850 AHCI SATA platform driver
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/module.h>
  7. #include <linux/pm.h>
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/libata.h>
  11. #include <linux/ahci_platform.h>
  12. #include "ahci.h"
  13. #define DRV_NAME "ahci_da850"
  14. #define HARDRESET_RETRIES 5
  15. /* SATA PHY Control Register offset from AHCI base */
  16. #define SATA_P0PHYCR_REG 0x178
  17. #define SATA_PHY_MPY(x) ((x) << 0)
  18. #define SATA_PHY_LOS(x) ((x) << 6)
  19. #define SATA_PHY_RXCDR(x) ((x) << 10)
  20. #define SATA_PHY_RXEQ(x) ((x) << 13)
  21. #define SATA_PHY_TXSWING(x) ((x) << 19)
  22. #define SATA_PHY_ENPLL(x) ((x) << 31)
  23. static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
  24. void __iomem *ahci_base, u32 mpy)
  25. {
  26. unsigned int val;
  27. /* Enable SATA clock receiver */
  28. val = readl(pwrdn_reg);
  29. val &= ~BIT(0);
  30. writel(val, pwrdn_reg);
  31. val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
  32. SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);
  33. writel(val, ahci_base + SATA_P0PHYCR_REG);
  34. }
  35. static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
  36. {
  37. u32 pll_output = 1500000000, needed;
  38. /*
  39. * We need to determine the value of the multiplier (MPY) bits.
  40. * In order to include the 12.5 multiplier we need to first divide
  41. * the refclk rate by ten.
  42. *
  43. * __div64_32() turned out to be unreliable, sometimes returning
  44. * false results.
  45. */
  46. WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
  47. needed = pll_output / (refclk_rate / 10);
  48. /*
  49. * What we have now is (multiplier * 10).
  50. *
  51. * Let's determine the actual register value we need to write.
  52. */
  53. switch (needed) {
  54. case 50:
  55. return 0x1;
  56. case 60:
  57. return 0x2;
  58. case 80:
  59. return 0x4;
  60. case 100:
  61. return 0x5;
  62. case 120:
  63. return 0x6;
  64. case 125:
  65. return 0x7;
  66. case 150:
  67. return 0x8;
  68. case 200:
  69. return 0x9;
  70. case 250:
  71. return 0xa;
  72. default:
  73. /*
  74. * We should have divided evenly - if not, return an invalid
  75. * value.
  76. */
  77. return 0;
  78. }
  79. }
  80. static int ahci_da850_softreset(struct ata_link *link,
  81. unsigned int *class, unsigned long deadline)
  82. {
  83. int pmp, ret;
  84. pmp = sata_srst_pmp(link);
  85. /*
  86. * There's an issue with the SATA controller on da850 SoCs: if we
  87. * enable Port Multiplier support, but the drive is connected directly
  88. * to the board, it can't be detected. As a workaround: if PMP is
  89. * enabled, we first call ahci_do_softreset() and pass it the result of
  90. * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
  91. */
  92. ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
  93. if (pmp && ret == -EBUSY)
  94. return ahci_do_softreset(link, class, 0,
  95. deadline, ahci_check_ready);
  96. return ret;
  97. }
  98. static int ahci_da850_hardreset(struct ata_link *link,
  99. unsigned int *class, unsigned long deadline)
  100. {
  101. int ret, retry = HARDRESET_RETRIES;
  102. bool online;
  103. /*
  104. * In order to correctly service the LCD controller of the da850 SoC,
  105. * we increased the PLL0 frequency to 456MHz from the default 300MHz.
  106. *
  107. * This made the SATA controller unstable and the hardreset operation
  108. * does not always succeed the first time. Before really giving up to
  109. * bring up the link, retry the reset a couple times.
  110. */
  111. do {
  112. ret = ahci_do_hardreset(link, class, deadline, &online);
  113. if (online)
  114. return ret;
  115. } while (retry--);
  116. return ret;
  117. }
  118. static struct ata_port_operations ahci_da850_port_ops = {
  119. .inherits = &ahci_platform_ops,
  120. .softreset = ahci_da850_softreset,
  121. /*
  122. * No need to override .pmp_softreset - it's only used for actual
  123. * PMP-enabled ports.
  124. */
  125. .hardreset = ahci_da850_hardreset,
  126. .pmp_hardreset = ahci_da850_hardreset,
  127. };
  128. static const struct ata_port_info ahci_da850_port_info = {
  129. .flags = AHCI_FLAG_COMMON,
  130. .pio_mask = ATA_PIO4,
  131. .udma_mask = ATA_UDMA6,
  132. .port_ops = &ahci_da850_port_ops,
  133. };
  134. static struct scsi_host_template ahci_platform_sht = {
  135. AHCI_SHT(DRV_NAME),
  136. };
  137. static int ahci_da850_probe(struct platform_device *pdev)
  138. {
  139. struct device *dev = &pdev->dev;
  140. struct ahci_host_priv *hpriv;
  141. void __iomem *pwrdn_reg;
  142. struct resource *res;
  143. u32 mpy;
  144. int rc;
  145. hpriv = ahci_platform_get_resources(pdev, 0);
  146. if (IS_ERR(hpriv))
  147. return PTR_ERR(hpriv);
  148. /*
  149. * Internally ahci_platform_get_resources() calls the bulk clocks
  150. * get method or falls back to using a single clk_get_optional().
  151. * This AHCI SATA controller uses two clocks: functional clock
  152. * with "fck" connection id and external reference clock with
  153. * "refclk" id. If we haven't got all of them re-try the clocks
  154. * getting procedure with the explicitly specified ids.
  155. */
  156. if (hpriv->n_clks < 2) {
  157. hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);
  158. if (!hpriv->clks)
  159. return -ENOMEM;
  160. hpriv->clks[0].id = "fck";
  161. hpriv->clks[1].id = "refclk";
  162. hpriv->n_clks = 2;
  163. rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);
  164. if (rc)
  165. return rc;
  166. }
  167. mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));
  168. if (mpy == 0) {
  169. dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
  170. return -EINVAL;
  171. }
  172. rc = ahci_platform_enable_resources(hpriv);
  173. if (rc)
  174. return rc;
  175. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  176. if (!res) {
  177. rc = -ENODEV;
  178. goto disable_resources;
  179. }
  180. pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
  181. if (!pwrdn_reg) {
  182. rc = -ENOMEM;
  183. goto disable_resources;
  184. }
  185. da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
  186. rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
  187. &ahci_platform_sht);
  188. if (rc)
  189. goto disable_resources;
  190. return 0;
  191. disable_resources:
  192. ahci_platform_disable_resources(hpriv);
  193. return rc;
  194. }
  195. static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
  196. ahci_platform_resume);
  197. static const struct of_device_id ahci_da850_of_match[] = {
  198. { .compatible = "ti,da850-ahci", },
  199. { /* sentinel */ }
  200. };
  201. MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
  202. static struct platform_driver ahci_da850_driver = {
  203. .probe = ahci_da850_probe,
  204. .remove = ata_platform_remove_one,
  205. .driver = {
  206. .name = DRV_NAME,
  207. .of_match_table = ahci_da850_of_match,
  208. .pm = &ahci_da850_pm_ops,
  209. },
  210. };
  211. module_platform_driver(ahci_da850_driver);
  212. MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
  213. MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <[email protected]>");
  214. MODULE_LICENSE("GPL");