tps68470_pmic.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TI TPS68470 PMIC operation region driver
  4. *
  5. * Copyright (C) 2017 Intel Corporation. All rights reserved.
  6. *
  7. * Author: Rajmohan Mani <[email protected]>
  8. *
  9. * Based on drivers/acpi/pmic/intel_pmic* drivers
  10. */
  11. #include <linux/acpi.h>
  12. #include <linux/init.h>
  13. #include <linux/mfd/tps68470.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. struct tps68470_pmic_table {
  17. u32 address; /* operation region address */
  18. u32 reg; /* corresponding register */
  19. u32 bitmask; /* bit mask for power, clock */
  20. };
  21. #define TI_PMIC_POWER_OPREGION_ID 0xB0
  22. #define TI_PMIC_VR_VAL_OPREGION_ID 0xB1
  23. #define TI_PMIC_CLOCK_OPREGION_ID 0xB2
  24. #define TI_PMIC_CLKFREQ_OPREGION_ID 0xB3
  25. struct tps68470_pmic_opregion {
  26. struct mutex lock;
  27. struct regmap *regmap;
  28. };
  29. #define S_IO_I2C_EN (BIT(0) | BIT(1))
  30. static const struct tps68470_pmic_table power_table[] = {
  31. {
  32. .address = 0x00,
  33. .reg = TPS68470_REG_S_I2C_CTL,
  34. .bitmask = S_IO_I2C_EN,
  35. /* S_I2C_CTL */
  36. },
  37. {
  38. .address = 0x04,
  39. .reg = TPS68470_REG_VCMCTL,
  40. .bitmask = BIT(0),
  41. /* VCMCTL */
  42. },
  43. {
  44. .address = 0x08,
  45. .reg = TPS68470_REG_VAUX1CTL,
  46. .bitmask = BIT(0),
  47. /* VAUX1_CTL */
  48. },
  49. {
  50. .address = 0x0C,
  51. .reg = TPS68470_REG_VAUX2CTL,
  52. .bitmask = BIT(0),
  53. /* VAUX2CTL */
  54. },
  55. {
  56. .address = 0x10,
  57. .reg = TPS68470_REG_VACTL,
  58. .bitmask = BIT(0),
  59. /* VACTL */
  60. },
  61. {
  62. .address = 0x14,
  63. .reg = TPS68470_REG_VDCTL,
  64. .bitmask = BIT(0),
  65. /* VDCTL */
  66. },
  67. };
  68. /* Table to set voltage regulator value */
  69. static const struct tps68470_pmic_table vr_val_table[] = {
  70. {
  71. .address = 0x00,
  72. .reg = TPS68470_REG_VSIOVAL,
  73. .bitmask = TPS68470_VSIOVAL_IOVOLT_MASK,
  74. /* TPS68470_REG_VSIOVAL */
  75. },
  76. {
  77. .address = 0x04,
  78. .reg = TPS68470_REG_VIOVAL,
  79. .bitmask = TPS68470_VIOVAL_IOVOLT_MASK,
  80. /* TPS68470_REG_VIOVAL */
  81. },
  82. {
  83. .address = 0x08,
  84. .reg = TPS68470_REG_VCMVAL,
  85. .bitmask = TPS68470_VCMVAL_VCVOLT_MASK,
  86. /* TPS68470_REG_VCMVAL */
  87. },
  88. {
  89. .address = 0x0C,
  90. .reg = TPS68470_REG_VAUX1VAL,
  91. .bitmask = TPS68470_VAUX1VAL_AUX1VOLT_MASK,
  92. /* TPS68470_REG_VAUX1VAL */
  93. },
  94. {
  95. .address = 0x10,
  96. .reg = TPS68470_REG_VAUX2VAL,
  97. .bitmask = TPS68470_VAUX2VAL_AUX2VOLT_MASK,
  98. /* TPS68470_REG_VAUX2VAL */
  99. },
  100. {
  101. .address = 0x14,
  102. .reg = TPS68470_REG_VAVAL,
  103. .bitmask = TPS68470_VAVAL_AVOLT_MASK,
  104. /* TPS68470_REG_VAVAL */
  105. },
  106. {
  107. .address = 0x18,
  108. .reg = TPS68470_REG_VDVAL,
  109. .bitmask = TPS68470_VDVAL_DVOLT_MASK,
  110. /* TPS68470_REG_VDVAL */
  111. },
  112. };
  113. /* Table to configure clock frequency */
  114. static const struct tps68470_pmic_table clk_freq_table[] = {
  115. {
  116. .address = 0x00,
  117. .reg = TPS68470_REG_POSTDIV2,
  118. .bitmask = BIT(0) | BIT(1),
  119. /* TPS68470_REG_POSTDIV2 */
  120. },
  121. {
  122. .address = 0x04,
  123. .reg = TPS68470_REG_BOOSTDIV,
  124. .bitmask = 0x1F,
  125. /* TPS68470_REG_BOOSTDIV */
  126. },
  127. {
  128. .address = 0x08,
  129. .reg = TPS68470_REG_BUCKDIV,
  130. .bitmask = 0x0F,
  131. /* TPS68470_REG_BUCKDIV */
  132. },
  133. {
  134. .address = 0x0C,
  135. .reg = TPS68470_REG_PLLSWR,
  136. .bitmask = 0x13,
  137. /* TPS68470_REG_PLLSWR */
  138. },
  139. {
  140. .address = 0x10,
  141. .reg = TPS68470_REG_XTALDIV,
  142. .bitmask = 0xFF,
  143. /* TPS68470_REG_XTALDIV */
  144. },
  145. {
  146. .address = 0x14,
  147. .reg = TPS68470_REG_PLLDIV,
  148. .bitmask = 0xFF,
  149. /* TPS68470_REG_PLLDIV */
  150. },
  151. {
  152. .address = 0x18,
  153. .reg = TPS68470_REG_POSTDIV,
  154. .bitmask = 0x83,
  155. /* TPS68470_REG_POSTDIV */
  156. },
  157. };
  158. /* Table to configure and enable clocks */
  159. static const struct tps68470_pmic_table clk_table[] = {
  160. {
  161. .address = 0x00,
  162. .reg = TPS68470_REG_PLLCTL,
  163. .bitmask = 0xF5,
  164. /* TPS68470_REG_PLLCTL */
  165. },
  166. {
  167. .address = 0x04,
  168. .reg = TPS68470_REG_PLLCTL2,
  169. .bitmask = BIT(0),
  170. /* TPS68470_REG_PLLCTL2 */
  171. },
  172. {
  173. .address = 0x08,
  174. .reg = TPS68470_REG_CLKCFG1,
  175. .bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
  176. TPS68470_CLKCFG1_MODE_B_MASK,
  177. /* TPS68470_REG_CLKCFG1 */
  178. },
  179. {
  180. .address = 0x0C,
  181. .reg = TPS68470_REG_CLKCFG2,
  182. .bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
  183. TPS68470_CLKCFG1_MODE_B_MASK,
  184. /* TPS68470_REG_CLKCFG2 */
  185. },
  186. };
  187. static int pmic_get_reg_bit(u64 address,
  188. const struct tps68470_pmic_table *table,
  189. const unsigned int table_size, int *reg,
  190. int *bitmask)
  191. {
  192. u64 i;
  193. i = address / 4;
  194. if (i >= table_size)
  195. return -ENOENT;
  196. if (!reg || !bitmask)
  197. return -EINVAL;
  198. *reg = table[i].reg;
  199. *bitmask = table[i].bitmask;
  200. return 0;
  201. }
  202. static int tps68470_pmic_get_power(struct regmap *regmap, int reg,
  203. int bitmask, u64 *value)
  204. {
  205. unsigned int data;
  206. if (regmap_read(regmap, reg, &data))
  207. return -EIO;
  208. *value = (data & bitmask) ? 1 : 0;
  209. return 0;
  210. }
  211. static int tps68470_pmic_get_vr_val(struct regmap *regmap, int reg,
  212. int bitmask, u64 *value)
  213. {
  214. unsigned int data;
  215. if (regmap_read(regmap, reg, &data))
  216. return -EIO;
  217. *value = data & bitmask;
  218. return 0;
  219. }
  220. static int tps68470_pmic_get_clk(struct regmap *regmap, int reg,
  221. int bitmask, u64 *value)
  222. {
  223. unsigned int data;
  224. if (regmap_read(regmap, reg, &data))
  225. return -EIO;
  226. *value = (data & bitmask) ? 1 : 0;
  227. return 0;
  228. }
  229. static int tps68470_pmic_get_clk_freq(struct regmap *regmap, int reg,
  230. int bitmask, u64 *value)
  231. {
  232. unsigned int data;
  233. if (regmap_read(regmap, reg, &data))
  234. return -EIO;
  235. *value = data & bitmask;
  236. return 0;
  237. }
  238. static int ti_tps68470_regmap_update_bits(struct regmap *regmap, int reg,
  239. int bitmask, u64 value)
  240. {
  241. return regmap_update_bits(regmap, reg, bitmask, value);
  242. }
  243. static acpi_status tps68470_pmic_common_handler(u32 function,
  244. acpi_physical_address address,
  245. u32 bits, u64 *value,
  246. void *region_context,
  247. int (*get)(struct regmap *,
  248. int, int, u64 *),
  249. int (*update)(struct regmap *,
  250. int, int, u64),
  251. const struct tps68470_pmic_table *tbl,
  252. unsigned int tbl_size)
  253. {
  254. struct tps68470_pmic_opregion *opregion = region_context;
  255. struct regmap *regmap = opregion->regmap;
  256. int reg, ret, bitmask;
  257. if (bits != 32)
  258. return AE_BAD_PARAMETER;
  259. ret = pmic_get_reg_bit(address, tbl, tbl_size, &reg, &bitmask);
  260. if (ret < 0)
  261. return AE_BAD_PARAMETER;
  262. if (function == ACPI_WRITE && *value > bitmask)
  263. return AE_BAD_PARAMETER;
  264. mutex_lock(&opregion->lock);
  265. ret = (function == ACPI_READ) ?
  266. get(regmap, reg, bitmask, value) :
  267. update(regmap, reg, bitmask, *value);
  268. mutex_unlock(&opregion->lock);
  269. return ret ? AE_ERROR : AE_OK;
  270. }
  271. static acpi_status tps68470_pmic_cfreq_handler(u32 function,
  272. acpi_physical_address address,
  273. u32 bits, u64 *value,
  274. void *handler_context,
  275. void *region_context)
  276. {
  277. return tps68470_pmic_common_handler(function, address, bits, value,
  278. region_context,
  279. tps68470_pmic_get_clk_freq,
  280. ti_tps68470_regmap_update_bits,
  281. clk_freq_table,
  282. ARRAY_SIZE(clk_freq_table));
  283. }
  284. static acpi_status tps68470_pmic_clk_handler(u32 function,
  285. acpi_physical_address address, u32 bits,
  286. u64 *value, void *handler_context,
  287. void *region_context)
  288. {
  289. return tps68470_pmic_common_handler(function, address, bits, value,
  290. region_context,
  291. tps68470_pmic_get_clk,
  292. ti_tps68470_regmap_update_bits,
  293. clk_table,
  294. ARRAY_SIZE(clk_table));
  295. }
  296. static acpi_status tps68470_pmic_vrval_handler(u32 function,
  297. acpi_physical_address address,
  298. u32 bits, u64 *value,
  299. void *handler_context,
  300. void *region_context)
  301. {
  302. return tps68470_pmic_common_handler(function, address, bits, value,
  303. region_context,
  304. tps68470_pmic_get_vr_val,
  305. ti_tps68470_regmap_update_bits,
  306. vr_val_table,
  307. ARRAY_SIZE(vr_val_table));
  308. }
  309. static acpi_status tps68470_pmic_pwr_handler(u32 function,
  310. acpi_physical_address address,
  311. u32 bits, u64 *value,
  312. void *handler_context,
  313. void *region_context)
  314. {
  315. if (bits != 32)
  316. return AE_BAD_PARAMETER;
  317. /* set/clear for bit 0, bits 0 and 1 together */
  318. if (function == ACPI_WRITE &&
  319. !(*value == 0 || *value == 1 || *value == 3)) {
  320. return AE_BAD_PARAMETER;
  321. }
  322. return tps68470_pmic_common_handler(function, address, bits, value,
  323. region_context,
  324. tps68470_pmic_get_power,
  325. ti_tps68470_regmap_update_bits,
  326. power_table,
  327. ARRAY_SIZE(power_table));
  328. }
  329. static int tps68470_pmic_opregion_probe(struct platform_device *pdev)
  330. {
  331. struct regmap *tps68470_regmap = dev_get_drvdata(pdev->dev.parent);
  332. acpi_handle handle = ACPI_HANDLE(pdev->dev.parent);
  333. struct device *dev = &pdev->dev;
  334. struct tps68470_pmic_opregion *opregion;
  335. acpi_status status;
  336. if (!dev || !tps68470_regmap) {
  337. dev_warn(dev, "dev or regmap is NULL\n");
  338. return -EINVAL;
  339. }
  340. if (!handle) {
  341. dev_warn(dev, "acpi handle is NULL\n");
  342. return -ENODEV;
  343. }
  344. opregion = devm_kzalloc(dev, sizeof(*opregion), GFP_KERNEL);
  345. if (!opregion)
  346. return -ENOMEM;
  347. mutex_init(&opregion->lock);
  348. opregion->regmap = tps68470_regmap;
  349. status = acpi_install_address_space_handler(handle,
  350. TI_PMIC_POWER_OPREGION_ID,
  351. tps68470_pmic_pwr_handler,
  352. NULL, opregion);
  353. if (ACPI_FAILURE(status))
  354. goto out_mutex_destroy;
  355. status = acpi_install_address_space_handler(handle,
  356. TI_PMIC_VR_VAL_OPREGION_ID,
  357. tps68470_pmic_vrval_handler,
  358. NULL, opregion);
  359. if (ACPI_FAILURE(status))
  360. goto out_remove_power_handler;
  361. status = acpi_install_address_space_handler(handle,
  362. TI_PMIC_CLOCK_OPREGION_ID,
  363. tps68470_pmic_clk_handler,
  364. NULL, opregion);
  365. if (ACPI_FAILURE(status))
  366. goto out_remove_vr_val_handler;
  367. status = acpi_install_address_space_handler(handle,
  368. TI_PMIC_CLKFREQ_OPREGION_ID,
  369. tps68470_pmic_cfreq_handler,
  370. NULL, opregion);
  371. if (ACPI_FAILURE(status))
  372. goto out_remove_clk_handler;
  373. return 0;
  374. out_remove_clk_handler:
  375. acpi_remove_address_space_handler(handle, TI_PMIC_CLOCK_OPREGION_ID,
  376. tps68470_pmic_clk_handler);
  377. out_remove_vr_val_handler:
  378. acpi_remove_address_space_handler(handle, TI_PMIC_VR_VAL_OPREGION_ID,
  379. tps68470_pmic_vrval_handler);
  380. out_remove_power_handler:
  381. acpi_remove_address_space_handler(handle, TI_PMIC_POWER_OPREGION_ID,
  382. tps68470_pmic_pwr_handler);
  383. out_mutex_destroy:
  384. mutex_destroy(&opregion->lock);
  385. return -ENODEV;
  386. }
  387. static struct platform_driver tps68470_pmic_opregion_driver = {
  388. .probe = tps68470_pmic_opregion_probe,
  389. .driver = {
  390. .name = "tps68470_pmic_opregion",
  391. },
  392. };
  393. builtin_platform_driver(tps68470_pmic_opregion_driver)