cppc_acpi.c 46 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
  4. *
  5. * (C) Copyright 2014, 2015 Linaro Ltd.
  6. * Author: Ashwin Chaugule <[email protected]>
  7. *
  8. * CPPC describes a few methods for controlling CPU performance using
  9. * information from a per CPU table called CPC. This table is described in
  10. * the ACPI v5.0+ specification. The table consists of a list of
  11. * registers which may be memory mapped or hardware registers and also may
  12. * include some static integer values.
  13. *
  14. * CPU performance is on an abstract continuous scale as against a discretized
  15. * P-state scale which is tied to CPU frequency only. In brief, the basic
  16. * operation involves:
  17. *
  18. * - OS makes a CPU performance request. (Can provide min and max bounds)
  19. *
  20. * - Platform (such as BMC) is free to optimize request within requested bounds
  21. * depending on power/thermal budgets etc.
  22. *
  23. * - Platform conveys its decision back to OS
  24. *
  25. * The communication between OS and platform occurs through another medium
  26. * called (PCC) Platform Communication Channel. This is a generic mailbox like
  27. * mechanism which includes doorbell semantics to indicate register updates.
  28. * See drivers/mailbox/pcc.c for details on PCC.
  29. *
  30. * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  31. * above specifications.
  32. */
  33. #define pr_fmt(fmt) "ACPI CPPC: " fmt
  34. #include <linux/delay.h>
  35. #include <linux/iopoll.h>
  36. #include <linux/ktime.h>
  37. #include <linux/rwsem.h>
  38. #include <linux/wait.h>
  39. #include <linux/topology.h>
  40. #include <acpi/cppc_acpi.h>
  41. struct cppc_pcc_data {
  42. struct pcc_mbox_chan *pcc_channel;
  43. void __iomem *pcc_comm_addr;
  44. bool pcc_channel_acquired;
  45. unsigned int deadline_us;
  46. unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  47. bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
  48. bool platform_owns_pcc; /* Ownership of PCC subspace */
  49. unsigned int pcc_write_cnt; /* Running count of PCC write commands */
  50. /*
  51. * Lock to provide controlled access to the PCC channel.
  52. *
  53. * For performance critical usecases(currently cppc_set_perf)
  54. * We need to take read_lock and check if channel belongs to OSPM
  55. * before reading or writing to PCC subspace
  56. * We need to take write_lock before transferring the channel
  57. * ownership to the platform via a Doorbell
  58. * This allows us to batch a number of CPPC requests if they happen
  59. * to originate in about the same time
  60. *
  61. * For non-performance critical usecases(init)
  62. * Take write_lock for all purposes which gives exclusive access
  63. */
  64. struct rw_semaphore pcc_lock;
  65. /* Wait queue for CPUs whose requests were batched */
  66. wait_queue_head_t pcc_write_wait_q;
  67. ktime_t last_cmd_cmpl_time;
  68. ktime_t last_mpar_reset;
  69. int mpar_count;
  70. int refcount;
  71. };
  72. /* Array to represent the PCC channel per subspace ID */
  73. static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
  74. /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
  75. static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  76. /*
  77. * The cpc_desc structure contains the ACPI register details
  78. * as described in the per CPU _CPC tables. The details
  79. * include the type of register (e.g. PCC, System IO, FFH etc.)
  80. * and destination addresses which lets us READ/WRITE CPU performance
  81. * information using the appropriate I/O methods.
  82. */
  83. static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  84. /* pcc mapped address + header size + offset within PCC subspace */
  85. #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
  86. 0x8 + (offs))
  87. /* Check if a CPC register is in PCC */
  88. #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
  89. (cpc)->cpc_entry.reg.space_id == \
  90. ACPI_ADR_SPACE_PLATFORM_COMM)
  91. /* Check if a CPC register is in SystemMemory */
  92. #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
  93. (cpc)->cpc_entry.reg.space_id == \
  94. ACPI_ADR_SPACE_SYSTEM_MEMORY)
  95. /* Check if a CPC register is in SystemIo */
  96. #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
  97. (cpc)->cpc_entry.reg.space_id == \
  98. ACPI_ADR_SPACE_SYSTEM_IO)
  99. /* Evaluates to True if reg is a NULL register descriptor */
  100. #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
  101. (reg)->address == 0 && \
  102. (reg)->bit_width == 0 && \
  103. (reg)->bit_offset == 0 && \
  104. (reg)->access_width == 0)
  105. /* Evaluates to True if an optional cpc field is supported */
  106. #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
  107. !!(cpc)->cpc_entry.int_value : \
  108. !IS_NULL_REG(&(cpc)->cpc_entry.reg))
  109. /*
  110. * Arbitrary Retries in case the remote processor is slow to respond
  111. * to PCC commands. Keeping it high enough to cover emulators where
  112. * the processors run painfully slow.
  113. */
  114. #define NUM_RETRIES 500ULL
  115. #define OVER_16BTS_MASK ~0xFFFFULL
  116. #define define_one_cppc_ro(_name) \
  117. static struct kobj_attribute _name = \
  118. __ATTR(_name, 0444, show_##_name, NULL)
  119. #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
  120. #define show_cppc_data(access_fn, struct_name, member_name) \
  121. static ssize_t show_##member_name(struct kobject *kobj, \
  122. struct kobj_attribute *attr, char *buf) \
  123. { \
  124. struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
  125. struct struct_name st_name = {0}; \
  126. int ret; \
  127. \
  128. ret = access_fn(cpc_ptr->cpu_id, &st_name); \
  129. if (ret) \
  130. return ret; \
  131. \
  132. return scnprintf(buf, PAGE_SIZE, "%llu\n", \
  133. (u64)st_name.member_name); \
  134. } \
  135. define_one_cppc_ro(member_name)
  136. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
  137. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
  138. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
  139. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
  140. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
  141. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
  142. show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
  143. show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
  144. static ssize_t show_feedback_ctrs(struct kobject *kobj,
  145. struct kobj_attribute *attr, char *buf)
  146. {
  147. struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
  148. struct cppc_perf_fb_ctrs fb_ctrs = {0};
  149. int ret;
  150. ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
  151. if (ret)
  152. return ret;
  153. return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
  154. fb_ctrs.reference, fb_ctrs.delivered);
  155. }
  156. define_one_cppc_ro(feedback_ctrs);
  157. static struct attribute *cppc_attrs[] = {
  158. &feedback_ctrs.attr,
  159. &reference_perf.attr,
  160. &wraparound_time.attr,
  161. &highest_perf.attr,
  162. &lowest_perf.attr,
  163. &lowest_nonlinear_perf.attr,
  164. &nominal_perf.attr,
  165. &nominal_freq.attr,
  166. &lowest_freq.attr,
  167. NULL
  168. };
  169. ATTRIBUTE_GROUPS(cppc);
  170. static struct kobj_type cppc_ktype = {
  171. .sysfs_ops = &kobj_sysfs_ops,
  172. .default_groups = cppc_groups,
  173. };
  174. static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
  175. {
  176. int ret, status;
  177. struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
  178. struct acpi_pcct_shared_memory __iomem *generic_comm_base =
  179. pcc_ss_data->pcc_comm_addr;
  180. if (!pcc_ss_data->platform_owns_pcc)
  181. return 0;
  182. /*
  183. * Poll PCC status register every 3us(delay_us) for maximum of
  184. * deadline_us(timeout_us) until PCC command complete bit is set(cond)
  185. */
  186. ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
  187. status & PCC_CMD_COMPLETE_MASK, 3,
  188. pcc_ss_data->deadline_us);
  189. if (likely(!ret)) {
  190. pcc_ss_data->platform_owns_pcc = false;
  191. if (chk_err_bit && (status & PCC_ERROR_MASK))
  192. ret = -EIO;
  193. }
  194. if (unlikely(ret))
  195. pr_err("PCC check channel failed for ss: %d. ret=%d\n",
  196. pcc_ss_id, ret);
  197. return ret;
  198. }
  199. /*
  200. * This function transfers the ownership of the PCC to the platform
  201. * So it must be called while holding write_lock(pcc_lock)
  202. */
  203. static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
  204. {
  205. int ret = -EIO, i;
  206. struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
  207. struct acpi_pcct_shared_memory __iomem *generic_comm_base =
  208. pcc_ss_data->pcc_comm_addr;
  209. unsigned int time_delta;
  210. /*
  211. * For CMD_WRITE we know for a fact the caller should have checked
  212. * the channel before writing to PCC space
  213. */
  214. if (cmd == CMD_READ) {
  215. /*
  216. * If there are pending cpc_writes, then we stole the channel
  217. * before write completion, so first send a WRITE command to
  218. * platform
  219. */
  220. if (pcc_ss_data->pending_pcc_write_cmd)
  221. send_pcc_cmd(pcc_ss_id, CMD_WRITE);
  222. ret = check_pcc_chan(pcc_ss_id, false);
  223. if (ret)
  224. goto end;
  225. } else /* CMD_WRITE */
  226. pcc_ss_data->pending_pcc_write_cmd = FALSE;
  227. /*
  228. * Handle the Minimum Request Turnaround Time(MRTT)
  229. * "The minimum amount of time that OSPM must wait after the completion
  230. * of a command before issuing the next command, in microseconds"
  231. */
  232. if (pcc_ss_data->pcc_mrtt) {
  233. time_delta = ktime_us_delta(ktime_get(),
  234. pcc_ss_data->last_cmd_cmpl_time);
  235. if (pcc_ss_data->pcc_mrtt > time_delta)
  236. udelay(pcc_ss_data->pcc_mrtt - time_delta);
  237. }
  238. /*
  239. * Handle the non-zero Maximum Periodic Access Rate(MPAR)
  240. * "The maximum number of periodic requests that the subspace channel can
  241. * support, reported in commands per minute. 0 indicates no limitation."
  242. *
  243. * This parameter should be ideally zero or large enough so that it can
  244. * handle maximum number of requests that all the cores in the system can
  245. * collectively generate. If it is not, we will follow the spec and just
  246. * not send the request to the platform after hitting the MPAR limit in
  247. * any 60s window
  248. */
  249. if (pcc_ss_data->pcc_mpar) {
  250. if (pcc_ss_data->mpar_count == 0) {
  251. time_delta = ktime_ms_delta(ktime_get(),
  252. pcc_ss_data->last_mpar_reset);
  253. if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
  254. pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
  255. pcc_ss_id);
  256. ret = -EIO;
  257. goto end;
  258. }
  259. pcc_ss_data->last_mpar_reset = ktime_get();
  260. pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
  261. }
  262. pcc_ss_data->mpar_count--;
  263. }
  264. /* Write to the shared comm region. */
  265. writew_relaxed(cmd, &generic_comm_base->command);
  266. /* Flip CMD COMPLETE bit */
  267. writew_relaxed(0, &generic_comm_base->status);
  268. pcc_ss_data->platform_owns_pcc = true;
  269. /* Ring doorbell */
  270. ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
  271. if (ret < 0) {
  272. pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
  273. pcc_ss_id, cmd, ret);
  274. goto end;
  275. }
  276. /* wait for completion and check for PCC error bit */
  277. ret = check_pcc_chan(pcc_ss_id, true);
  278. if (pcc_ss_data->pcc_mrtt)
  279. pcc_ss_data->last_cmd_cmpl_time = ktime_get();
  280. if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
  281. mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
  282. else
  283. mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
  284. end:
  285. if (cmd == CMD_WRITE) {
  286. if (unlikely(ret)) {
  287. for_each_possible_cpu(i) {
  288. struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
  289. if (!desc)
  290. continue;
  291. if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
  292. desc->write_cmd_status = ret;
  293. }
  294. }
  295. pcc_ss_data->pcc_write_cnt++;
  296. wake_up_all(&pcc_ss_data->pcc_write_wait_q);
  297. }
  298. return ret;
  299. }
  300. static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
  301. {
  302. if (ret < 0)
  303. pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
  304. *(u16 *)msg, ret);
  305. else
  306. pr_debug("TX completed. CMD sent:%x, ret:%d\n",
  307. *(u16 *)msg, ret);
  308. }
  309. static struct mbox_client cppc_mbox_cl = {
  310. .tx_done = cppc_chan_tx_done,
  311. .knows_txdone = true,
  312. };
  313. static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
  314. {
  315. int result = -EFAULT;
  316. acpi_status status = AE_OK;
  317. struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
  318. struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
  319. struct acpi_buffer state = {0, NULL};
  320. union acpi_object *psd = NULL;
  321. struct acpi_psd_package *pdomain;
  322. status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
  323. &buffer, ACPI_TYPE_PACKAGE);
  324. if (status == AE_NOT_FOUND) /* _PSD is optional */
  325. return 0;
  326. if (ACPI_FAILURE(status))
  327. return -ENODEV;
  328. psd = buffer.pointer;
  329. if (!psd || psd->package.count != 1) {
  330. pr_debug("Invalid _PSD data\n");
  331. goto end;
  332. }
  333. pdomain = &(cpc_ptr->domain_info);
  334. state.length = sizeof(struct acpi_psd_package);
  335. state.pointer = pdomain;
  336. status = acpi_extract_package(&(psd->package.elements[0]),
  337. &format, &state);
  338. if (ACPI_FAILURE(status)) {
  339. pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
  340. goto end;
  341. }
  342. if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
  343. pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
  344. goto end;
  345. }
  346. if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
  347. pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
  348. goto end;
  349. }
  350. if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
  351. pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
  352. pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
  353. pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
  354. goto end;
  355. }
  356. result = 0;
  357. end:
  358. kfree(buffer.pointer);
  359. return result;
  360. }
  361. bool acpi_cpc_valid(void)
  362. {
  363. struct cpc_desc *cpc_ptr;
  364. int cpu;
  365. if (acpi_disabled)
  366. return false;
  367. for_each_present_cpu(cpu) {
  368. cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
  369. if (!cpc_ptr)
  370. return false;
  371. }
  372. return true;
  373. }
  374. EXPORT_SYMBOL_GPL(acpi_cpc_valid);
  375. bool cppc_allow_fast_switch(void)
  376. {
  377. struct cpc_register_resource *desired_reg;
  378. struct cpc_desc *cpc_ptr;
  379. int cpu;
  380. for_each_possible_cpu(cpu) {
  381. cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
  382. desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
  383. if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
  384. !CPC_IN_SYSTEM_IO(desired_reg))
  385. return false;
  386. }
  387. return true;
  388. }
  389. EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
  390. /**
  391. * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
  392. * @cpu: Find all CPUs that share a domain with cpu.
  393. * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
  394. *
  395. * Return: 0 for success or negative value for err.
  396. */
  397. int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
  398. {
  399. struct cpc_desc *cpc_ptr, *match_cpc_ptr;
  400. struct acpi_psd_package *match_pdomain;
  401. struct acpi_psd_package *pdomain;
  402. int count_target, i;
  403. /*
  404. * Now that we have _PSD data from all CPUs, let's setup P-state
  405. * domain info.
  406. */
  407. cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
  408. if (!cpc_ptr)
  409. return -EFAULT;
  410. pdomain = &(cpc_ptr->domain_info);
  411. cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
  412. if (pdomain->num_processors <= 1)
  413. return 0;
  414. /* Validate the Domain info */
  415. count_target = pdomain->num_processors;
  416. if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
  417. cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
  418. else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
  419. cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
  420. else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
  421. cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
  422. for_each_possible_cpu(i) {
  423. if (i == cpu)
  424. continue;
  425. match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
  426. if (!match_cpc_ptr)
  427. goto err_fault;
  428. match_pdomain = &(match_cpc_ptr->domain_info);
  429. if (match_pdomain->domain != pdomain->domain)
  430. continue;
  431. /* Here i and cpu are in the same domain */
  432. if (match_pdomain->num_processors != count_target)
  433. goto err_fault;
  434. if (pdomain->coord_type != match_pdomain->coord_type)
  435. goto err_fault;
  436. cpumask_set_cpu(i, cpu_data->shared_cpu_map);
  437. }
  438. return 0;
  439. err_fault:
  440. /* Assume no coordination on any error parsing domain info */
  441. cpumask_clear(cpu_data->shared_cpu_map);
  442. cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
  443. cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
  444. return -EFAULT;
  445. }
  446. EXPORT_SYMBOL_GPL(acpi_get_psd_map);
  447. static int register_pcc_channel(int pcc_ss_idx)
  448. {
  449. struct pcc_mbox_chan *pcc_chan;
  450. u64 usecs_lat;
  451. if (pcc_ss_idx >= 0) {
  452. pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
  453. if (IS_ERR(pcc_chan)) {
  454. pr_err("Failed to find PCC channel for subspace %d\n",
  455. pcc_ss_idx);
  456. return -ENODEV;
  457. }
  458. pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
  459. /*
  460. * cppc_ss->latency is just a Nominal value. In reality
  461. * the remote processor could be much slower to reply.
  462. * So add an arbitrary amount of wait on top of Nominal.
  463. */
  464. usecs_lat = NUM_RETRIES * pcc_chan->latency;
  465. pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
  466. pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
  467. pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
  468. pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
  469. pcc_data[pcc_ss_idx]->pcc_comm_addr =
  470. acpi_os_ioremap(pcc_chan->shmem_base_addr,
  471. pcc_chan->shmem_size);
  472. if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
  473. pr_err("Failed to ioremap PCC comm region mem for %d\n",
  474. pcc_ss_idx);
  475. return -ENOMEM;
  476. }
  477. /* Set flag so that we don't come here for each CPU. */
  478. pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
  479. }
  480. return 0;
  481. }
  482. /**
  483. * cpc_ffh_supported() - check if FFH reading supported
  484. *
  485. * Check if the architecture has support for functional fixed hardware
  486. * read/write capability.
  487. *
  488. * Return: true for supported, false for not supported
  489. */
  490. bool __weak cpc_ffh_supported(void)
  491. {
  492. return false;
  493. }
  494. /**
  495. * cpc_supported_by_cpu() - check if CPPC is supported by CPU
  496. *
  497. * Check if the architectural support for CPPC is present even
  498. * if the _OSC hasn't prescribed it
  499. *
  500. * Return: true for supported, false for not supported
  501. */
  502. bool __weak cpc_supported_by_cpu(void)
  503. {
  504. return false;
  505. }
  506. /**
  507. * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
  508. *
  509. * Check and allocate the cppc_pcc_data memory.
  510. * In some processor configurations it is possible that same subspace
  511. * is shared between multiple CPUs. This is seen especially in CPUs
  512. * with hardware multi-threading support.
  513. *
  514. * Return: 0 for success, errno for failure
  515. */
  516. static int pcc_data_alloc(int pcc_ss_id)
  517. {
  518. if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
  519. return -EINVAL;
  520. if (pcc_data[pcc_ss_id]) {
  521. pcc_data[pcc_ss_id]->refcount++;
  522. } else {
  523. pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
  524. GFP_KERNEL);
  525. if (!pcc_data[pcc_ss_id])
  526. return -ENOMEM;
  527. pcc_data[pcc_ss_id]->refcount++;
  528. }
  529. return 0;
  530. }
  531. /*
  532. * An example CPC table looks like the following.
  533. *
  534. * Name (_CPC, Package() {
  535. * 17, // NumEntries
  536. * 1, // Revision
  537. * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
  538. * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
  539. * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
  540. * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
  541. * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
  542. * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
  543. * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
  544. * ...
  545. * ...
  546. * ...
  547. * }
  548. * Each Register() encodes how to access that specific register.
  549. * e.g. a sample PCC entry has the following encoding:
  550. *
  551. * Register (
  552. * PCC, // AddressSpaceKeyword
  553. * 8, // RegisterBitWidth
  554. * 8, // RegisterBitOffset
  555. * 0x30, // RegisterAddress
  556. * 9, // AccessSize (subspace ID)
  557. * )
  558. */
  559. #ifndef arch_init_invariance_cppc
  560. static inline void arch_init_invariance_cppc(void) { }
  561. #endif
  562. /**
  563. * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
  564. * @pr: Ptr to acpi_processor containing this CPU's logical ID.
  565. *
  566. * Return: 0 for success or negative value for err.
  567. */
  568. int acpi_cppc_processor_probe(struct acpi_processor *pr)
  569. {
  570. struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
  571. union acpi_object *out_obj, *cpc_obj;
  572. struct cpc_desc *cpc_ptr;
  573. struct cpc_reg *gas_t;
  574. struct device *cpu_dev;
  575. acpi_handle handle = pr->handle;
  576. unsigned int num_ent, i, cpc_rev;
  577. int pcc_subspace_id = -1;
  578. acpi_status status;
  579. int ret = -ENODATA;
  580. if (!osc_sb_cppc2_support_acked) {
  581. pr_debug("CPPC v2 _OSC not acked\n");
  582. if (!cpc_supported_by_cpu())
  583. return -ENODEV;
  584. }
  585. /* Parse the ACPI _CPC table for this CPU. */
  586. status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
  587. ACPI_TYPE_PACKAGE);
  588. if (ACPI_FAILURE(status)) {
  589. ret = -ENODEV;
  590. goto out_buf_free;
  591. }
  592. out_obj = (union acpi_object *) output.pointer;
  593. cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
  594. if (!cpc_ptr) {
  595. ret = -ENOMEM;
  596. goto out_buf_free;
  597. }
  598. /* First entry is NumEntries. */
  599. cpc_obj = &out_obj->package.elements[0];
  600. if (cpc_obj->type == ACPI_TYPE_INTEGER) {
  601. num_ent = cpc_obj->integer.value;
  602. if (num_ent <= 1) {
  603. pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
  604. num_ent, pr->id);
  605. goto out_free;
  606. }
  607. } else {
  608. pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
  609. cpc_obj->type, pr->id);
  610. goto out_free;
  611. }
  612. /* Second entry should be revision. */
  613. cpc_obj = &out_obj->package.elements[1];
  614. if (cpc_obj->type == ACPI_TYPE_INTEGER) {
  615. cpc_rev = cpc_obj->integer.value;
  616. } else {
  617. pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
  618. cpc_obj->type, pr->id);
  619. goto out_free;
  620. }
  621. if (cpc_rev < CPPC_V2_REV) {
  622. pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
  623. pr->id);
  624. goto out_free;
  625. }
  626. /*
  627. * Disregard _CPC if the number of entries in the return pachage is not
  628. * as expected, but support future revisions being proper supersets of
  629. * the v3 and only causing more entries to be returned by _CPC.
  630. */
  631. if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
  632. (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
  633. (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
  634. pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
  635. num_ent, pr->id);
  636. goto out_free;
  637. }
  638. if (cpc_rev > CPPC_V3_REV) {
  639. num_ent = CPPC_V3_NUM_ENT;
  640. cpc_rev = CPPC_V3_REV;
  641. }
  642. cpc_ptr->num_entries = num_ent;
  643. cpc_ptr->version = cpc_rev;
  644. /* Iterate through remaining entries in _CPC */
  645. for (i = 2; i < num_ent; i++) {
  646. cpc_obj = &out_obj->package.elements[i];
  647. if (cpc_obj->type == ACPI_TYPE_INTEGER) {
  648. cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
  649. cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
  650. } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
  651. gas_t = (struct cpc_reg *)
  652. cpc_obj->buffer.pointer;
  653. /*
  654. * The PCC Subspace index is encoded inside
  655. * the CPC table entries. The same PCC index
  656. * will be used for all the PCC entries,
  657. * so extract it only once.
  658. */
  659. if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
  660. if (pcc_subspace_id < 0) {
  661. pcc_subspace_id = gas_t->access_width;
  662. if (pcc_data_alloc(pcc_subspace_id))
  663. goto out_free;
  664. } else if (pcc_subspace_id != gas_t->access_width) {
  665. pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
  666. pr->id);
  667. goto out_free;
  668. }
  669. } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
  670. if (gas_t->address) {
  671. void __iomem *addr;
  672. if (!osc_cpc_flexible_adr_space_confirmed) {
  673. pr_debug("Flexible address space capability not supported\n");
  674. if (!cpc_supported_by_cpu())
  675. goto out_free;
  676. }
  677. addr = ioremap(gas_t->address, gas_t->bit_width/8);
  678. if (!addr)
  679. goto out_free;
  680. cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
  681. }
  682. } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
  683. if (gas_t->access_width < 1 || gas_t->access_width > 3) {
  684. /*
  685. * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
  686. * SystemIO doesn't implement 64-bit
  687. * registers.
  688. */
  689. pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
  690. gas_t->access_width);
  691. goto out_free;
  692. }
  693. if (gas_t->address & OVER_16BTS_MASK) {
  694. /* SystemIO registers use 16-bit integer addresses */
  695. pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
  696. gas_t->address);
  697. goto out_free;
  698. }
  699. if (!osc_cpc_flexible_adr_space_confirmed) {
  700. pr_debug("Flexible address space capability not supported\n");
  701. if (!cpc_supported_by_cpu())
  702. goto out_free;
  703. }
  704. } else {
  705. if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
  706. /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
  707. pr_debug("Unsupported register type (%d) in _CPC\n",
  708. gas_t->space_id);
  709. goto out_free;
  710. }
  711. }
  712. cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
  713. memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
  714. } else {
  715. pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
  716. i, pr->id);
  717. goto out_free;
  718. }
  719. }
  720. per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
  721. /*
  722. * Initialize the remaining cpc_regs as unsupported.
  723. * Example: In case FW exposes CPPC v2, the below loop will initialize
  724. * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
  725. */
  726. for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
  727. cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
  728. cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
  729. }
  730. /* Store CPU Logical ID */
  731. cpc_ptr->cpu_id = pr->id;
  732. /* Parse PSD data for this CPU */
  733. ret = acpi_get_psd(cpc_ptr, handle);
  734. if (ret)
  735. goto out_free;
  736. /* Register PCC channel once for all PCC subspace ID. */
  737. if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
  738. ret = register_pcc_channel(pcc_subspace_id);
  739. if (ret)
  740. goto out_free;
  741. init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
  742. init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
  743. }
  744. /* Everything looks okay */
  745. pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
  746. /* Add per logical CPU nodes for reading its feedback counters. */
  747. cpu_dev = get_cpu_device(pr->id);
  748. if (!cpu_dev) {
  749. ret = -EINVAL;
  750. goto out_free;
  751. }
  752. /* Plug PSD data into this CPU's CPC descriptor. */
  753. per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
  754. ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
  755. "acpi_cppc");
  756. if (ret) {
  757. per_cpu(cpc_desc_ptr, pr->id) = NULL;
  758. kobject_put(&cpc_ptr->kobj);
  759. goto out_free;
  760. }
  761. arch_init_invariance_cppc();
  762. kfree(output.pointer);
  763. return 0;
  764. out_free:
  765. /* Free all the mapped sys mem areas for this CPU */
  766. for (i = 2; i < cpc_ptr->num_entries; i++) {
  767. void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
  768. if (addr)
  769. iounmap(addr);
  770. }
  771. kfree(cpc_ptr);
  772. out_buf_free:
  773. kfree(output.pointer);
  774. return ret;
  775. }
  776. EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
  777. /**
  778. * acpi_cppc_processor_exit - Cleanup CPC structs.
  779. * @pr: Ptr to acpi_processor containing this CPU's logical ID.
  780. *
  781. * Return: Void
  782. */
  783. void acpi_cppc_processor_exit(struct acpi_processor *pr)
  784. {
  785. struct cpc_desc *cpc_ptr;
  786. unsigned int i;
  787. void __iomem *addr;
  788. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
  789. if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
  790. if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
  791. pcc_data[pcc_ss_id]->refcount--;
  792. if (!pcc_data[pcc_ss_id]->refcount) {
  793. pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
  794. kfree(pcc_data[pcc_ss_id]);
  795. pcc_data[pcc_ss_id] = NULL;
  796. }
  797. }
  798. }
  799. cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
  800. if (!cpc_ptr)
  801. return;
  802. /* Free all the mapped sys mem areas for this CPU */
  803. for (i = 2; i < cpc_ptr->num_entries; i++) {
  804. addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
  805. if (addr)
  806. iounmap(addr);
  807. }
  808. kobject_put(&cpc_ptr->kobj);
  809. kfree(cpc_ptr);
  810. }
  811. EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
  812. /**
  813. * cpc_read_ffh() - Read FFH register
  814. * @cpunum: CPU number to read
  815. * @reg: cppc register information
  816. * @val: place holder for return value
  817. *
  818. * Read bit_width bits from a specified address and bit_offset
  819. *
  820. * Return: 0 for success and error code
  821. */
  822. int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
  823. {
  824. return -ENOTSUPP;
  825. }
  826. /**
  827. * cpc_write_ffh() - Write FFH register
  828. * @cpunum: CPU number to write
  829. * @reg: cppc register information
  830. * @val: value to write
  831. *
  832. * Write value of bit_width bits to a specified address and bit_offset
  833. *
  834. * Return: 0 for success and error code
  835. */
  836. int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
  837. {
  838. return -ENOTSUPP;
  839. }
  840. /*
  841. * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
  842. * as fast as possible. We have already mapped the PCC subspace during init, so
  843. * we can directly write to it.
  844. */
  845. static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
  846. {
  847. void __iomem *vaddr = NULL;
  848. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  849. struct cpc_reg *reg = &reg_res->cpc_entry.reg;
  850. if (reg_res->type == ACPI_TYPE_INTEGER) {
  851. *val = reg_res->cpc_entry.int_value;
  852. return 0;
  853. }
  854. *val = 0;
  855. if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
  856. u32 width = 8 << (reg->access_width - 1);
  857. u32 val_u32;
  858. acpi_status status;
  859. status = acpi_os_read_port((acpi_io_address)reg->address,
  860. &val_u32, width);
  861. if (ACPI_FAILURE(status)) {
  862. pr_debug("Error: Failed to read SystemIO port %llx\n",
  863. reg->address);
  864. return -EFAULT;
  865. }
  866. *val = val_u32;
  867. return 0;
  868. } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
  869. vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
  870. else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
  871. vaddr = reg_res->sys_mem_vaddr;
  872. else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
  873. return cpc_read_ffh(cpu, reg, val);
  874. else
  875. return acpi_os_read_memory((acpi_physical_address)reg->address,
  876. val, reg->bit_width);
  877. switch (reg->bit_width) {
  878. case 8:
  879. *val = readb_relaxed(vaddr);
  880. break;
  881. case 16:
  882. *val = readw_relaxed(vaddr);
  883. break;
  884. case 32:
  885. *val = readl_relaxed(vaddr);
  886. break;
  887. case 64:
  888. *val = readq_relaxed(vaddr);
  889. break;
  890. default:
  891. pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
  892. reg->bit_width, pcc_ss_id);
  893. return -EFAULT;
  894. }
  895. return 0;
  896. }
  897. static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
  898. {
  899. int ret_val = 0;
  900. void __iomem *vaddr = NULL;
  901. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  902. struct cpc_reg *reg = &reg_res->cpc_entry.reg;
  903. if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
  904. u32 width = 8 << (reg->access_width - 1);
  905. acpi_status status;
  906. status = acpi_os_write_port((acpi_io_address)reg->address,
  907. (u32)val, width);
  908. if (ACPI_FAILURE(status)) {
  909. pr_debug("Error: Failed to write SystemIO port %llx\n",
  910. reg->address);
  911. return -EFAULT;
  912. }
  913. return 0;
  914. } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
  915. vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
  916. else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
  917. vaddr = reg_res->sys_mem_vaddr;
  918. else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
  919. return cpc_write_ffh(cpu, reg, val);
  920. else
  921. return acpi_os_write_memory((acpi_physical_address)reg->address,
  922. val, reg->bit_width);
  923. switch (reg->bit_width) {
  924. case 8:
  925. writeb_relaxed(val, vaddr);
  926. break;
  927. case 16:
  928. writew_relaxed(val, vaddr);
  929. break;
  930. case 32:
  931. writel_relaxed(val, vaddr);
  932. break;
  933. case 64:
  934. writeq_relaxed(val, vaddr);
  935. break;
  936. default:
  937. pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
  938. reg->bit_width, pcc_ss_id);
  939. ret_val = -EFAULT;
  940. break;
  941. }
  942. return ret_val;
  943. }
  944. static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
  945. {
  946. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
  947. struct cpc_register_resource *reg;
  948. if (!cpc_desc) {
  949. pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
  950. return -ENODEV;
  951. }
  952. reg = &cpc_desc->cpc_regs[reg_idx];
  953. if (CPC_IN_PCC(reg)) {
  954. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
  955. struct cppc_pcc_data *pcc_ss_data = NULL;
  956. int ret = 0;
  957. if (pcc_ss_id < 0)
  958. return -EIO;
  959. pcc_ss_data = pcc_data[pcc_ss_id];
  960. down_write(&pcc_ss_data->pcc_lock);
  961. if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
  962. cpc_read(cpunum, reg, perf);
  963. else
  964. ret = -EIO;
  965. up_write(&pcc_ss_data->pcc_lock);
  966. return ret;
  967. }
  968. cpc_read(cpunum, reg, perf);
  969. return 0;
  970. }
  971. /**
  972. * cppc_get_desired_perf - Get the desired performance register value.
  973. * @cpunum: CPU from which to get desired performance.
  974. * @desired_perf: Return address.
  975. *
  976. * Return: 0 for success, -EIO otherwise.
  977. */
  978. int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
  979. {
  980. return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
  981. }
  982. EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
  983. /**
  984. * cppc_get_nominal_perf - Get the nominal performance register value.
  985. * @cpunum: CPU from which to get nominal performance.
  986. * @nominal_perf: Return address.
  987. *
  988. * Return: 0 for success, -EIO otherwise.
  989. */
  990. int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
  991. {
  992. return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
  993. }
  994. /**
  995. * cppc_get_perf_caps - Get a CPU's performance capabilities.
  996. * @cpunum: CPU from which to get capabilities info.
  997. * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
  998. *
  999. * Return: 0 for success with perf_caps populated else -ERRNO.
  1000. */
  1001. int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
  1002. {
  1003. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
  1004. struct cpc_register_resource *highest_reg, *lowest_reg,
  1005. *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
  1006. *low_freq_reg = NULL, *nom_freq_reg = NULL;
  1007. u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
  1008. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
  1009. struct cppc_pcc_data *pcc_ss_data = NULL;
  1010. int ret = 0, regs_in_pcc = 0;
  1011. if (!cpc_desc) {
  1012. pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
  1013. return -ENODEV;
  1014. }
  1015. highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
  1016. lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
  1017. lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
  1018. nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
  1019. low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
  1020. nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
  1021. guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
  1022. /* Are any of the regs PCC ?*/
  1023. if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
  1024. CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
  1025. CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
  1026. if (pcc_ss_id < 0) {
  1027. pr_debug("Invalid pcc_ss_id\n");
  1028. return -ENODEV;
  1029. }
  1030. pcc_ss_data = pcc_data[pcc_ss_id];
  1031. regs_in_pcc = 1;
  1032. down_write(&pcc_ss_data->pcc_lock);
  1033. /* Ring doorbell once to update PCC subspace */
  1034. if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
  1035. ret = -EIO;
  1036. goto out_err;
  1037. }
  1038. }
  1039. cpc_read(cpunum, highest_reg, &high);
  1040. perf_caps->highest_perf = high;
  1041. cpc_read(cpunum, lowest_reg, &low);
  1042. perf_caps->lowest_perf = low;
  1043. cpc_read(cpunum, nominal_reg, &nom);
  1044. perf_caps->nominal_perf = nom;
  1045. if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
  1046. IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
  1047. perf_caps->guaranteed_perf = 0;
  1048. } else {
  1049. cpc_read(cpunum, guaranteed_reg, &guaranteed);
  1050. perf_caps->guaranteed_perf = guaranteed;
  1051. }
  1052. cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
  1053. perf_caps->lowest_nonlinear_perf = min_nonlinear;
  1054. if (!high || !low || !nom || !min_nonlinear)
  1055. ret = -EFAULT;
  1056. /* Read optional lowest and nominal frequencies if present */
  1057. if (CPC_SUPPORTED(low_freq_reg))
  1058. cpc_read(cpunum, low_freq_reg, &low_f);
  1059. if (CPC_SUPPORTED(nom_freq_reg))
  1060. cpc_read(cpunum, nom_freq_reg, &nom_f);
  1061. perf_caps->lowest_freq = low_f;
  1062. perf_caps->nominal_freq = nom_f;
  1063. out_err:
  1064. if (regs_in_pcc)
  1065. up_write(&pcc_ss_data->pcc_lock);
  1066. return ret;
  1067. }
  1068. EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
  1069. /**
  1070. * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
  1071. *
  1072. * CPPC has flexibility about how CPU performance counters are accessed.
  1073. * One of the choices is PCC regions, which can have a high access latency. This
  1074. * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
  1075. *
  1076. * Return: true if any of the counters are in PCC regions, false otherwise
  1077. */
  1078. bool cppc_perf_ctrs_in_pcc(void)
  1079. {
  1080. int cpu;
  1081. for_each_present_cpu(cpu) {
  1082. struct cpc_register_resource *ref_perf_reg;
  1083. struct cpc_desc *cpc_desc;
  1084. cpc_desc = per_cpu(cpc_desc_ptr, cpu);
  1085. if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
  1086. CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
  1087. CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
  1088. return true;
  1089. ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
  1090. /*
  1091. * If reference perf register is not supported then we should
  1092. * use the nominal perf value
  1093. */
  1094. if (!CPC_SUPPORTED(ref_perf_reg))
  1095. ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
  1096. if (CPC_IN_PCC(ref_perf_reg))
  1097. return true;
  1098. }
  1099. return false;
  1100. }
  1101. EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
  1102. /**
  1103. * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
  1104. * @cpunum: CPU from which to read counters.
  1105. * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
  1106. *
  1107. * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
  1108. */
  1109. int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
  1110. {
  1111. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
  1112. struct cpc_register_resource *delivered_reg, *reference_reg,
  1113. *ref_perf_reg, *ctr_wrap_reg;
  1114. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
  1115. struct cppc_pcc_data *pcc_ss_data = NULL;
  1116. u64 delivered, reference, ref_perf, ctr_wrap_time;
  1117. int ret = 0, regs_in_pcc = 0;
  1118. if (!cpc_desc) {
  1119. pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
  1120. return -ENODEV;
  1121. }
  1122. delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
  1123. reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
  1124. ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
  1125. ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
  1126. /*
  1127. * If reference perf register is not supported then we should
  1128. * use the nominal perf value
  1129. */
  1130. if (!CPC_SUPPORTED(ref_perf_reg))
  1131. ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
  1132. /* Are any of the regs PCC ?*/
  1133. if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
  1134. CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
  1135. if (pcc_ss_id < 0) {
  1136. pr_debug("Invalid pcc_ss_id\n");
  1137. return -ENODEV;
  1138. }
  1139. pcc_ss_data = pcc_data[pcc_ss_id];
  1140. down_write(&pcc_ss_data->pcc_lock);
  1141. regs_in_pcc = 1;
  1142. /* Ring doorbell once to update PCC subspace */
  1143. if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
  1144. ret = -EIO;
  1145. goto out_err;
  1146. }
  1147. }
  1148. cpc_read(cpunum, delivered_reg, &delivered);
  1149. cpc_read(cpunum, reference_reg, &reference);
  1150. cpc_read(cpunum, ref_perf_reg, &ref_perf);
  1151. /*
  1152. * Per spec, if ctr_wrap_time optional register is unsupported, then the
  1153. * performance counters are assumed to never wrap during the lifetime of
  1154. * platform
  1155. */
  1156. ctr_wrap_time = (u64)(~((u64)0));
  1157. if (CPC_SUPPORTED(ctr_wrap_reg))
  1158. cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
  1159. if (!delivered || !reference || !ref_perf) {
  1160. ret = -EFAULT;
  1161. goto out_err;
  1162. }
  1163. perf_fb_ctrs->delivered = delivered;
  1164. perf_fb_ctrs->reference = reference;
  1165. perf_fb_ctrs->reference_perf = ref_perf;
  1166. perf_fb_ctrs->wraparound_time = ctr_wrap_time;
  1167. out_err:
  1168. if (regs_in_pcc)
  1169. up_write(&pcc_ss_data->pcc_lock);
  1170. return ret;
  1171. }
  1172. EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
  1173. /**
  1174. * cppc_set_enable - Set to enable CPPC on the processor by writing the
  1175. * Continuous Performance Control package EnableRegister field.
  1176. * @cpu: CPU for which to enable CPPC register.
  1177. * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
  1178. *
  1179. * Return: 0 for success, -ERRNO or -EIO otherwise.
  1180. */
  1181. int cppc_set_enable(int cpu, bool enable)
  1182. {
  1183. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  1184. struct cpc_register_resource *enable_reg;
  1185. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
  1186. struct cppc_pcc_data *pcc_ss_data = NULL;
  1187. int ret = -EINVAL;
  1188. if (!cpc_desc) {
  1189. pr_debug("No CPC descriptor for CPU:%d\n", cpu);
  1190. return -EINVAL;
  1191. }
  1192. enable_reg = &cpc_desc->cpc_regs[ENABLE];
  1193. if (CPC_IN_PCC(enable_reg)) {
  1194. if (pcc_ss_id < 0)
  1195. return -EIO;
  1196. ret = cpc_write(cpu, enable_reg, enable);
  1197. if (ret)
  1198. return ret;
  1199. pcc_ss_data = pcc_data[pcc_ss_id];
  1200. down_write(&pcc_ss_data->pcc_lock);
  1201. /* after writing CPC, transfer the ownership of PCC to platfrom */
  1202. ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
  1203. up_write(&pcc_ss_data->pcc_lock);
  1204. return ret;
  1205. }
  1206. return cpc_write(cpu, enable_reg, enable);
  1207. }
  1208. EXPORT_SYMBOL_GPL(cppc_set_enable);
  1209. /**
  1210. * cppc_set_perf - Set a CPU's performance controls.
  1211. * @cpu: CPU for which to set performance controls.
  1212. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
  1213. *
  1214. * Return: 0 for success, -ERRNO otherwise.
  1215. */
  1216. int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
  1217. {
  1218. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
  1219. struct cpc_register_resource *desired_reg;
  1220. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  1221. struct cppc_pcc_data *pcc_ss_data = NULL;
  1222. int ret = 0;
  1223. if (!cpc_desc) {
  1224. pr_debug("No CPC descriptor for CPU:%d\n", cpu);
  1225. return -ENODEV;
  1226. }
  1227. desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
  1228. /*
  1229. * This is Phase-I where we want to write to CPC registers
  1230. * -> We want all CPUs to be able to execute this phase in parallel
  1231. *
  1232. * Since read_lock can be acquired by multiple CPUs simultaneously we
  1233. * achieve that goal here
  1234. */
  1235. if (CPC_IN_PCC(desired_reg)) {
  1236. if (pcc_ss_id < 0) {
  1237. pr_debug("Invalid pcc_ss_id\n");
  1238. return -ENODEV;
  1239. }
  1240. pcc_ss_data = pcc_data[pcc_ss_id];
  1241. down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
  1242. if (pcc_ss_data->platform_owns_pcc) {
  1243. ret = check_pcc_chan(pcc_ss_id, false);
  1244. if (ret) {
  1245. up_read(&pcc_ss_data->pcc_lock);
  1246. return ret;
  1247. }
  1248. }
  1249. /*
  1250. * Update the pending_write to make sure a PCC CMD_READ will not
  1251. * arrive and steal the channel during the switch to write lock
  1252. */
  1253. pcc_ss_data->pending_pcc_write_cmd = true;
  1254. cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
  1255. cpc_desc->write_cmd_status = 0;
  1256. }
  1257. /*
  1258. * Skip writing MIN/MAX until Linux knows how to come up with
  1259. * useful values.
  1260. */
  1261. cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
  1262. if (CPC_IN_PCC(desired_reg))
  1263. up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
  1264. /*
  1265. * This is Phase-II where we transfer the ownership of PCC to Platform
  1266. *
  1267. * Short Summary: Basically if we think of a group of cppc_set_perf
  1268. * requests that happened in short overlapping interval. The last CPU to
  1269. * come out of Phase-I will enter Phase-II and ring the doorbell.
  1270. *
  1271. * We have the following requirements for Phase-II:
  1272. * 1. We want to execute Phase-II only when there are no CPUs
  1273. * currently executing in Phase-I
  1274. * 2. Once we start Phase-II we want to avoid all other CPUs from
  1275. * entering Phase-I.
  1276. * 3. We want only one CPU among all those who went through Phase-I
  1277. * to run phase-II
  1278. *
  1279. * If write_trylock fails to get the lock and doesn't transfer the
  1280. * PCC ownership to the platform, then one of the following will be TRUE
  1281. * 1. There is at-least one CPU in Phase-I which will later execute
  1282. * write_trylock, so the CPUs in Phase-I will be responsible for
  1283. * executing the Phase-II.
  1284. * 2. Some other CPU has beaten this CPU to successfully execute the
  1285. * write_trylock and has already acquired the write_lock. We know for a
  1286. * fact it (other CPU acquiring the write_lock) couldn't have happened
  1287. * before this CPU's Phase-I as we held the read_lock.
  1288. * 3. Some other CPU executing pcc CMD_READ has stolen the
  1289. * down_write, in which case, send_pcc_cmd will check for pending
  1290. * CMD_WRITE commands by checking the pending_pcc_write_cmd.
  1291. * So this CPU can be certain that its request will be delivered
  1292. * So in all cases, this CPU knows that its request will be delivered
  1293. * by another CPU and can return
  1294. *
  1295. * After getting the down_write we still need to check for
  1296. * pending_pcc_write_cmd to take care of the following scenario
  1297. * The thread running this code could be scheduled out between
  1298. * Phase-I and Phase-II. Before it is scheduled back on, another CPU
  1299. * could have delivered the request to Platform by triggering the
  1300. * doorbell and transferred the ownership of PCC to platform. So this
  1301. * avoids triggering an unnecessary doorbell and more importantly before
  1302. * triggering the doorbell it makes sure that the PCC channel ownership
  1303. * is still with OSPM.
  1304. * pending_pcc_write_cmd can also be cleared by a different CPU, if
  1305. * there was a pcc CMD_READ waiting on down_write and it steals the lock
  1306. * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
  1307. * case during a CMD_READ and if there are pending writes it delivers
  1308. * the write command before servicing the read command
  1309. */
  1310. if (CPC_IN_PCC(desired_reg)) {
  1311. if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
  1312. /* Update only if there are pending write commands */
  1313. if (pcc_ss_data->pending_pcc_write_cmd)
  1314. send_pcc_cmd(pcc_ss_id, CMD_WRITE);
  1315. up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
  1316. } else
  1317. /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
  1318. wait_event(pcc_ss_data->pcc_write_wait_q,
  1319. cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
  1320. /* send_pcc_cmd updates the status in case of failure */
  1321. ret = cpc_desc->write_cmd_status;
  1322. }
  1323. return ret;
  1324. }
  1325. EXPORT_SYMBOL_GPL(cppc_set_perf);
  1326. /**
  1327. * cppc_get_transition_latency - returns frequency transition latency in ns
  1328. *
  1329. * ACPI CPPC does not explicitly specify how a platform can specify the
  1330. * transition latency for performance change requests. The closest we have
  1331. * is the timing information from the PCCT tables which provides the info
  1332. * on the number and frequency of PCC commands the platform can handle.
  1333. *
  1334. * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
  1335. * then assume there is no latency.
  1336. */
  1337. unsigned int cppc_get_transition_latency(int cpu_num)
  1338. {
  1339. /*
  1340. * Expected transition latency is based on the PCCT timing values
  1341. * Below are definition from ACPI spec:
  1342. * pcc_nominal- Expected latency to process a command, in microseconds
  1343. * pcc_mpar - The maximum number of periodic requests that the subspace
  1344. * channel can support, reported in commands per minute. 0
  1345. * indicates no limitation.
  1346. * pcc_mrtt - The minimum amount of time that OSPM must wait after the
  1347. * completion of a command before issuing the next command,
  1348. * in microseconds.
  1349. */
  1350. unsigned int latency_ns = 0;
  1351. struct cpc_desc *cpc_desc;
  1352. struct cpc_register_resource *desired_reg;
  1353. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
  1354. struct cppc_pcc_data *pcc_ss_data;
  1355. cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
  1356. if (!cpc_desc)
  1357. return CPUFREQ_ETERNAL;
  1358. desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
  1359. if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
  1360. return 0;
  1361. else if (!CPC_IN_PCC(desired_reg))
  1362. return CPUFREQ_ETERNAL;
  1363. if (pcc_ss_id < 0)
  1364. return CPUFREQ_ETERNAL;
  1365. pcc_ss_data = pcc_data[pcc_ss_id];
  1366. if (pcc_ss_data->pcc_mpar)
  1367. latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
  1368. latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
  1369. latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
  1370. return latency_ns;
  1371. }
  1372. EXPORT_SYMBOL_GPL(cppc_get_transition_latency);