acpi_lpss.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ACPI support for Intel Lynxpoint LPSS.
  4. *
  5. * Copyright (C) 2013, Intel Corporation
  6. * Authors: Mika Westerberg <[email protected]>
  7. * Rafael J. Wysocki <[email protected]>
  8. */
  9. #include <linux/acpi.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/dmi.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <linux/mutex.h>
  16. #include <linux/pci.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/platform_data/x86/clk-lpss.h>
  19. #include <linux/platform_data/x86/pmc_atom.h>
  20. #include <linux/pm_domain.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/pwm.h>
  23. #include <linux/pxa2xx_ssp.h>
  24. #include <linux/suspend.h>
  25. #include <linux/delay.h>
  26. #include "internal.h"
  27. #ifdef CONFIG_X86_INTEL_LPSS
  28. #include <asm/cpu_device_id.h>
  29. #include <asm/intel-family.h>
  30. #include <asm/iosf_mbi.h>
  31. #define LPSS_ADDR(desc) ((unsigned long)&desc)
  32. #define LPSS_CLK_SIZE 0x04
  33. #define LPSS_LTR_SIZE 0x18
  34. /* Offsets relative to LPSS_PRIVATE_OFFSET */
  35. #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
  36. #define LPSS_RESETS 0x04
  37. #define LPSS_RESETS_RESET_FUNC BIT(0)
  38. #define LPSS_RESETS_RESET_APB BIT(1)
  39. #define LPSS_GENERAL 0x08
  40. #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
  41. #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
  42. #define LPSS_SW_LTR 0x10
  43. #define LPSS_AUTO_LTR 0x14
  44. #define LPSS_LTR_SNOOP_REQ BIT(15)
  45. #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
  46. #define LPSS_LTR_SNOOP_LAT_1US 0x800
  47. #define LPSS_LTR_SNOOP_LAT_32US 0xC00
  48. #define LPSS_LTR_SNOOP_LAT_SHIFT 5
  49. #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
  50. #define LPSS_LTR_MAX_VAL 0x3FF
  51. #define LPSS_TX_INT 0x20
  52. #define LPSS_TX_INT_MASK BIT(1)
  53. #define LPSS_PRV_REG_COUNT 9
  54. /* LPSS Flags */
  55. #define LPSS_CLK BIT(0)
  56. #define LPSS_CLK_GATE BIT(1)
  57. #define LPSS_CLK_DIVIDER BIT(2)
  58. #define LPSS_LTR BIT(3)
  59. #define LPSS_SAVE_CTX BIT(4)
  60. /*
  61. * For some devices the DSDT AML code for another device turns off the device
  62. * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
  63. * as ctx register values.
  64. * Luckily these devices always use the same ctx register values, so we can
  65. * work around this by saving the ctx registers once on activation.
  66. */
  67. #define LPSS_SAVE_CTX_ONCE BIT(5)
  68. #define LPSS_NO_D3_DELAY BIT(6)
  69. struct lpss_private_data;
  70. struct lpss_device_desc {
  71. unsigned int flags;
  72. const char *clk_con_id;
  73. unsigned int prv_offset;
  74. size_t prv_size_override;
  75. const struct property_entry *properties;
  76. void (*setup)(struct lpss_private_data *pdata);
  77. bool resume_from_noirq;
  78. };
  79. static const struct lpss_device_desc lpss_dma_desc = {
  80. .flags = LPSS_CLK,
  81. };
  82. struct lpss_private_data {
  83. struct acpi_device *adev;
  84. void __iomem *mmio_base;
  85. resource_size_t mmio_size;
  86. unsigned int fixed_clk_rate;
  87. struct clk *clk;
  88. const struct lpss_device_desc *dev_desc;
  89. u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  90. };
  91. /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
  92. static u32 pmc_atom_d3_mask = 0xfe000ffe;
  93. /* LPSS run time quirks */
  94. static unsigned int lpss_quirks;
  95. /*
  96. * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
  97. *
  98. * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
  99. * it can be powered off automatically whenever the last LPSS device goes down.
  100. * In case of no power any access to the DMA controller will hang the system.
  101. * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
  102. * well as on ASuS T100TA transformer.
  103. *
  104. * This quirk overrides power state of entire LPSS island to keep DMA powered
  105. * on whenever we have at least one other device in use.
  106. */
  107. #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
  108. /* UART Component Parameter Register */
  109. #define LPSS_UART_CPR 0xF4
  110. #define LPSS_UART_CPR_AFCE BIT(4)
  111. static void lpss_uart_setup(struct lpss_private_data *pdata)
  112. {
  113. unsigned int offset;
  114. u32 val;
  115. offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
  116. val = readl(pdata->mmio_base + offset);
  117. writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
  118. val = readl(pdata->mmio_base + LPSS_UART_CPR);
  119. if (!(val & LPSS_UART_CPR_AFCE)) {
  120. offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
  121. val = readl(pdata->mmio_base + offset);
  122. val |= LPSS_GENERAL_UART_RTS_OVRD;
  123. writel(val, pdata->mmio_base + offset);
  124. }
  125. }
  126. static void lpss_deassert_reset(struct lpss_private_data *pdata)
  127. {
  128. unsigned int offset;
  129. u32 val;
  130. offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
  131. val = readl(pdata->mmio_base + offset);
  132. val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
  133. writel(val, pdata->mmio_base + offset);
  134. }
  135. /*
  136. * BYT PWM used for backlight control by the i915 driver on systems without
  137. * the Crystal Cove PMIC.
  138. */
  139. static struct pwm_lookup byt_pwm_lookup[] = {
  140. PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
  141. "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
  142. "pwm-lpss-platform"),
  143. };
  144. static void byt_pwm_setup(struct lpss_private_data *pdata)
  145. {
  146. u64 uid;
  147. /* Only call pwm_add_table for the first PWM controller */
  148. if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
  149. return;
  150. pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
  151. }
  152. #define LPSS_I2C_ENABLE 0x6c
  153. static void byt_i2c_setup(struct lpss_private_data *pdata)
  154. {
  155. acpi_handle handle = pdata->adev->handle;
  156. unsigned long long shared_host = 0;
  157. acpi_status status;
  158. u64 uid;
  159. /* Expected to always be successfull, but better safe then sorry */
  160. if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) {
  161. /* Detect I2C bus shared with PUNIT and ignore its d3 status */
  162. status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
  163. if (ACPI_SUCCESS(status) && shared_host)
  164. pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
  165. }
  166. lpss_deassert_reset(pdata);
  167. if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
  168. pdata->fixed_clk_rate = 133000000;
  169. writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
  170. }
  171. /* BSW PWM used for backlight control by the i915 driver */
  172. static struct pwm_lookup bsw_pwm_lookup[] = {
  173. PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
  174. "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
  175. "pwm-lpss-platform"),
  176. };
  177. static void bsw_pwm_setup(struct lpss_private_data *pdata)
  178. {
  179. u64 uid;
  180. /* Only call pwm_add_table for the first PWM controller */
  181. if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
  182. return;
  183. pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
  184. }
  185. static const struct property_entry lpt_spi_properties[] = {
  186. PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
  187. { }
  188. };
  189. static const struct lpss_device_desc lpt_spi_dev_desc = {
  190. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
  191. | LPSS_SAVE_CTX,
  192. .prv_offset = 0x800,
  193. .properties = lpt_spi_properties,
  194. };
  195. static const struct lpss_device_desc lpt_i2c_dev_desc = {
  196. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
  197. .prv_offset = 0x800,
  198. };
  199. static struct property_entry uart_properties[] = {
  200. PROPERTY_ENTRY_U32("reg-io-width", 4),
  201. PROPERTY_ENTRY_U32("reg-shift", 2),
  202. PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
  203. { },
  204. };
  205. static const struct lpss_device_desc lpt_uart_dev_desc = {
  206. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
  207. | LPSS_SAVE_CTX,
  208. .clk_con_id = "baudclk",
  209. .prv_offset = 0x800,
  210. .setup = lpss_uart_setup,
  211. .properties = uart_properties,
  212. };
  213. static const struct lpss_device_desc lpt_sdio_dev_desc = {
  214. .flags = LPSS_LTR,
  215. .prv_offset = 0x1000,
  216. .prv_size_override = 0x1018,
  217. };
  218. static const struct lpss_device_desc byt_pwm_dev_desc = {
  219. .flags = LPSS_SAVE_CTX,
  220. .prv_offset = 0x800,
  221. .setup = byt_pwm_setup,
  222. };
  223. static const struct lpss_device_desc bsw_pwm_dev_desc = {
  224. .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
  225. .prv_offset = 0x800,
  226. .setup = bsw_pwm_setup,
  227. .resume_from_noirq = true,
  228. };
  229. static const struct lpss_device_desc byt_uart_dev_desc = {
  230. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
  231. .clk_con_id = "baudclk",
  232. .prv_offset = 0x800,
  233. .setup = lpss_uart_setup,
  234. .properties = uart_properties,
  235. };
  236. static const struct lpss_device_desc bsw_uart_dev_desc = {
  237. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
  238. | LPSS_NO_D3_DELAY,
  239. .clk_con_id = "baudclk",
  240. .prv_offset = 0x800,
  241. .setup = lpss_uart_setup,
  242. .properties = uart_properties,
  243. };
  244. static const struct property_entry byt_spi_properties[] = {
  245. PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
  246. { }
  247. };
  248. static const struct lpss_device_desc byt_spi_dev_desc = {
  249. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
  250. .prv_offset = 0x400,
  251. .properties = byt_spi_properties,
  252. };
  253. static const struct lpss_device_desc byt_sdio_dev_desc = {
  254. .flags = LPSS_CLK,
  255. };
  256. static const struct lpss_device_desc byt_i2c_dev_desc = {
  257. .flags = LPSS_CLK | LPSS_SAVE_CTX,
  258. .prv_offset = 0x800,
  259. .setup = byt_i2c_setup,
  260. .resume_from_noirq = true,
  261. };
  262. static const struct lpss_device_desc bsw_i2c_dev_desc = {
  263. .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
  264. .prv_offset = 0x800,
  265. .setup = byt_i2c_setup,
  266. .resume_from_noirq = true,
  267. };
  268. static const struct property_entry bsw_spi_properties[] = {
  269. PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
  270. { }
  271. };
  272. static const struct lpss_device_desc bsw_spi_dev_desc = {
  273. .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
  274. | LPSS_NO_D3_DELAY,
  275. .prv_offset = 0x400,
  276. .setup = lpss_deassert_reset,
  277. .properties = bsw_spi_properties,
  278. };
  279. static const struct x86_cpu_id lpss_cpu_ids[] = {
  280. X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
  281. X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
  282. {}
  283. };
  284. #else
  285. #define LPSS_ADDR(desc) (0UL)
  286. #endif /* CONFIG_X86_INTEL_LPSS */
  287. static const struct acpi_device_id acpi_lpss_device_ids[] = {
  288. /* Generic LPSS devices */
  289. { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
  290. /* Lynxpoint LPSS devices */
  291. { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
  292. { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
  293. { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
  294. { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
  295. { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
  296. { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
  297. { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
  298. { "INT33C7", },
  299. /* BayTrail LPSS devices */
  300. { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
  301. { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
  302. { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
  303. { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
  304. { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
  305. { "INT33B2", },
  306. { "INT33FC", },
  307. /* Braswell LPSS devices */
  308. { "80862286", LPSS_ADDR(lpss_dma_desc) },
  309. { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
  310. { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
  311. { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
  312. { "808622C0", LPSS_ADDR(lpss_dma_desc) },
  313. { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
  314. /* Broadwell LPSS devices */
  315. { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
  316. { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
  317. { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
  318. { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
  319. { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
  320. { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
  321. { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
  322. { "INT3437", },
  323. /* Wildcat Point LPSS devices */
  324. { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) },
  325. { }
  326. };
  327. #ifdef CONFIG_X86_INTEL_LPSS
  328. /* LPSS main clock device. */
  329. static struct platform_device *lpss_clk_dev;
  330. static inline void lpt_register_clock_device(void)
  331. {
  332. lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
  333. PLATFORM_DEVID_NONE,
  334. NULL, 0);
  335. }
  336. static int register_device_clock(struct acpi_device *adev,
  337. struct lpss_private_data *pdata)
  338. {
  339. const struct lpss_device_desc *dev_desc = pdata->dev_desc;
  340. const char *devname = dev_name(&adev->dev);
  341. struct clk *clk;
  342. struct lpss_clk_data *clk_data;
  343. const char *parent, *clk_name;
  344. void __iomem *prv_base;
  345. if (!lpss_clk_dev)
  346. lpt_register_clock_device();
  347. if (IS_ERR(lpss_clk_dev))
  348. return PTR_ERR(lpss_clk_dev);
  349. clk_data = platform_get_drvdata(lpss_clk_dev);
  350. if (!clk_data)
  351. return -ENODEV;
  352. clk = clk_data->clk;
  353. if (!pdata->mmio_base
  354. || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
  355. return -ENODATA;
  356. parent = clk_data->name;
  357. prv_base = pdata->mmio_base + dev_desc->prv_offset;
  358. if (pdata->fixed_clk_rate) {
  359. clk = clk_register_fixed_rate(NULL, devname, parent, 0,
  360. pdata->fixed_clk_rate);
  361. goto out;
  362. }
  363. if (dev_desc->flags & LPSS_CLK_GATE) {
  364. clk = clk_register_gate(NULL, devname, parent, 0,
  365. prv_base, 0, 0, NULL);
  366. parent = devname;
  367. }
  368. if (dev_desc->flags & LPSS_CLK_DIVIDER) {
  369. /* Prevent division by zero */
  370. if (!readl(prv_base))
  371. writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
  372. clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
  373. if (!clk_name)
  374. return -ENOMEM;
  375. clk = clk_register_fractional_divider(NULL, clk_name, parent,
  376. CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
  377. prv_base, 1, 15, 16, 15, 0, NULL);
  378. parent = clk_name;
  379. clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
  380. if (!clk_name) {
  381. kfree(parent);
  382. return -ENOMEM;
  383. }
  384. clk = clk_register_gate(NULL, clk_name, parent,
  385. CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
  386. prv_base, 31, 0, NULL);
  387. kfree(parent);
  388. kfree(clk_name);
  389. }
  390. out:
  391. if (IS_ERR(clk))
  392. return PTR_ERR(clk);
  393. pdata->clk = clk;
  394. clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
  395. return 0;
  396. }
  397. struct lpss_device_links {
  398. const char *supplier_hid;
  399. const char *supplier_uid;
  400. const char *consumer_hid;
  401. const char *consumer_uid;
  402. u32 flags;
  403. const struct dmi_system_id *dep_missing_ids;
  404. };
  405. /* Please keep this list sorted alphabetically by vendor and model */
  406. static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
  407. {
  408. .matches = {
  409. DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
  410. DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
  411. },
  412. },
  413. {}
  414. };
  415. /*
  416. * The _DEP method is used to identify dependencies but instead of creating
  417. * device links for every handle in _DEP, only links in the following list are
  418. * created. That is necessary because, in the general case, _DEP can refer to
  419. * devices that might not have drivers, or that are on different buses, or where
  420. * the supplier is not enumerated until after the consumer is probed.
  421. */
  422. static const struct lpss_device_links lpss_device_links[] = {
  423. /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
  424. {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
  425. /* CHT iGPU depends on PMIC I2C controller */
  426. {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
  427. /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
  428. {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
  429. i2c1_dep_missing_dmi_ids},
  430. /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
  431. {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
  432. /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
  433. {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
  434. };
  435. static bool acpi_lpss_is_supplier(struct acpi_device *adev,
  436. const struct lpss_device_links *link)
  437. {
  438. return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
  439. }
  440. static bool acpi_lpss_is_consumer(struct acpi_device *adev,
  441. const struct lpss_device_links *link)
  442. {
  443. return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
  444. }
  445. struct hid_uid {
  446. const char *hid;
  447. const char *uid;
  448. };
  449. static int match_hid_uid(struct device *dev, const void *data)
  450. {
  451. struct acpi_device *adev = ACPI_COMPANION(dev);
  452. const struct hid_uid *id = data;
  453. if (!adev)
  454. return 0;
  455. return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
  456. }
  457. static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
  458. {
  459. struct device *dev;
  460. struct hid_uid data = {
  461. .hid = hid,
  462. .uid = uid,
  463. };
  464. dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
  465. if (dev)
  466. return dev;
  467. return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
  468. }
  469. static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
  470. {
  471. struct acpi_handle_list dep_devices;
  472. acpi_status status;
  473. int i;
  474. if (!acpi_has_method(adev->handle, "_DEP"))
  475. return false;
  476. status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
  477. &dep_devices);
  478. if (ACPI_FAILURE(status)) {
  479. dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
  480. return false;
  481. }
  482. for (i = 0; i < dep_devices.count; i++) {
  483. if (dep_devices.handles[i] == handle)
  484. return true;
  485. }
  486. return false;
  487. }
  488. static void acpi_lpss_link_consumer(struct device *dev1,
  489. const struct lpss_device_links *link)
  490. {
  491. struct device *dev2;
  492. dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
  493. if (!dev2)
  494. return;
  495. if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
  496. || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
  497. device_link_add(dev2, dev1, link->flags);
  498. put_device(dev2);
  499. }
  500. static void acpi_lpss_link_supplier(struct device *dev1,
  501. const struct lpss_device_links *link)
  502. {
  503. struct device *dev2;
  504. dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
  505. if (!dev2)
  506. return;
  507. if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
  508. || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
  509. device_link_add(dev1, dev2, link->flags);
  510. put_device(dev2);
  511. }
  512. static void acpi_lpss_create_device_links(struct acpi_device *adev,
  513. struct platform_device *pdev)
  514. {
  515. int i;
  516. for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
  517. const struct lpss_device_links *link = &lpss_device_links[i];
  518. if (acpi_lpss_is_supplier(adev, link))
  519. acpi_lpss_link_consumer(&pdev->dev, link);
  520. if (acpi_lpss_is_consumer(adev, link))
  521. acpi_lpss_link_supplier(&pdev->dev, link);
  522. }
  523. }
  524. static int acpi_lpss_create_device(struct acpi_device *adev,
  525. const struct acpi_device_id *id)
  526. {
  527. const struct lpss_device_desc *dev_desc;
  528. struct lpss_private_data *pdata;
  529. struct resource_entry *rentry;
  530. struct list_head resource_list;
  531. struct platform_device *pdev;
  532. int ret;
  533. dev_desc = (const struct lpss_device_desc *)id->driver_data;
  534. if (!dev_desc) {
  535. pdev = acpi_create_platform_device(adev, NULL);
  536. return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
  537. }
  538. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  539. if (!pdata)
  540. return -ENOMEM;
  541. INIT_LIST_HEAD(&resource_list);
  542. ret = acpi_dev_get_memory_resources(adev, &resource_list);
  543. if (ret < 0)
  544. goto err_out;
  545. rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node);
  546. if (rentry) {
  547. if (dev_desc->prv_size_override)
  548. pdata->mmio_size = dev_desc->prv_size_override;
  549. else
  550. pdata->mmio_size = resource_size(rentry->res);
  551. pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);
  552. }
  553. acpi_dev_free_resource_list(&resource_list);
  554. if (!pdata->mmio_base) {
  555. /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
  556. adev->pnp.type.platform_id = 0;
  557. goto out_free;
  558. }
  559. pdata->adev = adev;
  560. pdata->dev_desc = dev_desc;
  561. if (dev_desc->setup)
  562. dev_desc->setup(pdata);
  563. if (dev_desc->flags & LPSS_CLK) {
  564. ret = register_device_clock(adev, pdata);
  565. if (ret)
  566. goto out_free;
  567. }
  568. /*
  569. * This works around a known issue in ACPI tables where LPSS devices
  570. * have _PS0 and _PS3 without _PSC (and no power resources), so
  571. * acpi_bus_init_power() will assume that the BIOS has put them into D0.
  572. */
  573. acpi_device_fix_up_power(adev);
  574. adev->driver_data = pdata;
  575. pdev = acpi_create_platform_device(adev, dev_desc->properties);
  576. if (IS_ERR_OR_NULL(pdev)) {
  577. adev->driver_data = NULL;
  578. ret = PTR_ERR(pdev);
  579. goto err_out;
  580. }
  581. acpi_lpss_create_device_links(adev, pdev);
  582. return 1;
  583. out_free:
  584. /* Skip the device, but continue the namespace scan */
  585. ret = 0;
  586. err_out:
  587. kfree(pdata);
  588. return ret;
  589. }
  590. static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
  591. {
  592. return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
  593. }
  594. static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
  595. unsigned int reg)
  596. {
  597. writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
  598. }
  599. static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
  600. {
  601. struct acpi_device *adev = ACPI_COMPANION(dev);
  602. struct lpss_private_data *pdata;
  603. unsigned long flags;
  604. int ret;
  605. if (WARN_ON(!adev))
  606. return -ENODEV;
  607. spin_lock_irqsave(&dev->power.lock, flags);
  608. if (pm_runtime_suspended(dev)) {
  609. ret = -EAGAIN;
  610. goto out;
  611. }
  612. pdata = acpi_driver_data(adev);
  613. if (WARN_ON(!pdata || !pdata->mmio_base)) {
  614. ret = -ENODEV;
  615. goto out;
  616. }
  617. *val = __lpss_reg_read(pdata, reg);
  618. ret = 0;
  619. out:
  620. spin_unlock_irqrestore(&dev->power.lock, flags);
  621. return ret;
  622. }
  623. static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
  624. char *buf)
  625. {
  626. u32 ltr_value = 0;
  627. unsigned int reg;
  628. int ret;
  629. reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
  630. ret = lpss_reg_read(dev, reg, &ltr_value);
  631. if (ret)
  632. return ret;
  633. return sysfs_emit(buf, "%08x\n", ltr_value);
  634. }
  635. static ssize_t lpss_ltr_mode_show(struct device *dev,
  636. struct device_attribute *attr, char *buf)
  637. {
  638. u32 ltr_mode = 0;
  639. char *outstr;
  640. int ret;
  641. ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
  642. if (ret)
  643. return ret;
  644. outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
  645. return sprintf(buf, "%s\n", outstr);
  646. }
  647. static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
  648. static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
  649. static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
  650. static struct attribute *lpss_attrs[] = {
  651. &dev_attr_auto_ltr.attr,
  652. &dev_attr_sw_ltr.attr,
  653. &dev_attr_ltr_mode.attr,
  654. NULL,
  655. };
  656. static const struct attribute_group lpss_attr_group = {
  657. .attrs = lpss_attrs,
  658. .name = "lpss_ltr",
  659. };
  660. static void acpi_lpss_set_ltr(struct device *dev, s32 val)
  661. {
  662. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  663. u32 ltr_mode, ltr_val;
  664. ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
  665. if (val < 0) {
  666. if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
  667. ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
  668. __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
  669. }
  670. return;
  671. }
  672. ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
  673. if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
  674. ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
  675. val = LPSS_LTR_MAX_VAL;
  676. } else if (val > LPSS_LTR_MAX_VAL) {
  677. ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
  678. val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
  679. } else {
  680. ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
  681. }
  682. ltr_val |= val;
  683. __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
  684. if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
  685. ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
  686. __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
  687. }
  688. }
  689. #ifdef CONFIG_PM
  690. /**
  691. * acpi_lpss_save_ctx() - Save the private registers of LPSS device
  692. * @dev: LPSS device
  693. * @pdata: pointer to the private data of the LPSS device
  694. *
  695. * Most LPSS devices have private registers which may loose their context when
  696. * the device is powered down. acpi_lpss_save_ctx() saves those registers into
  697. * prv_reg_ctx array.
  698. */
  699. static void acpi_lpss_save_ctx(struct device *dev,
  700. struct lpss_private_data *pdata)
  701. {
  702. unsigned int i;
  703. for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
  704. unsigned long offset = i * sizeof(u32);
  705. pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
  706. dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
  707. pdata->prv_reg_ctx[i], offset);
  708. }
  709. }
  710. /**
  711. * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
  712. * @dev: LPSS device
  713. * @pdata: pointer to the private data of the LPSS device
  714. *
  715. * Restores the registers that were previously stored with acpi_lpss_save_ctx().
  716. */
  717. static void acpi_lpss_restore_ctx(struct device *dev,
  718. struct lpss_private_data *pdata)
  719. {
  720. unsigned int i;
  721. for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
  722. unsigned long offset = i * sizeof(u32);
  723. __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
  724. dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
  725. pdata->prv_reg_ctx[i], offset);
  726. }
  727. }
  728. static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
  729. {
  730. /*
  731. * The following delay is needed or the subsequent write operations may
  732. * fail. The LPSS devices are actually PCI devices and the PCI spec
  733. * expects 10ms delay before the device can be accessed after D3 to D0
  734. * transition. However some platforms like BSW does not need this delay.
  735. */
  736. unsigned int delay = 10; /* default 10ms delay */
  737. if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
  738. delay = 0;
  739. msleep(delay);
  740. }
  741. static int acpi_lpss_activate(struct device *dev)
  742. {
  743. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  744. int ret;
  745. ret = acpi_dev_resume(dev);
  746. if (ret)
  747. return ret;
  748. acpi_lpss_d3_to_d0_delay(pdata);
  749. /*
  750. * This is called only on ->probe() stage where a device is either in
  751. * known state defined by BIOS or most likely powered off. Due to this
  752. * we have to deassert reset line to be sure that ->probe() will
  753. * recognize the device.
  754. */
  755. if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
  756. lpss_deassert_reset(pdata);
  757. #ifdef CONFIG_PM
  758. if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
  759. acpi_lpss_save_ctx(dev, pdata);
  760. #endif
  761. return 0;
  762. }
  763. static void acpi_lpss_dismiss(struct device *dev)
  764. {
  765. acpi_dev_suspend(dev, false);
  766. }
  767. /* IOSF SB for LPSS island */
  768. #define LPSS_IOSF_UNIT_LPIOEP 0xA0
  769. #define LPSS_IOSF_UNIT_LPIO1 0xAB
  770. #define LPSS_IOSF_UNIT_LPIO2 0xAC
  771. #define LPSS_IOSF_PMCSR 0x84
  772. #define LPSS_PMCSR_D0 0
  773. #define LPSS_PMCSR_D3hot 3
  774. #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
  775. #define LPSS_IOSF_GPIODEF0 0x154
  776. #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
  777. #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
  778. #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
  779. #define LPSS_GPIODEF0_DMA_LLP BIT(13)
  780. static DEFINE_MUTEX(lpss_iosf_mutex);
  781. static bool lpss_iosf_d3_entered = true;
  782. static void lpss_iosf_enter_d3_state(void)
  783. {
  784. u32 value1 = 0;
  785. u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
  786. u32 value2 = LPSS_PMCSR_D3hot;
  787. u32 mask2 = LPSS_PMCSR_Dx_MASK;
  788. /*
  789. * PMC provides an information about actual status of the LPSS devices.
  790. * Here we read the values related to LPSS power island, i.e. LPSS
  791. * devices, excluding both LPSS DMA controllers, along with SCC domain.
  792. */
  793. u32 func_dis, d3_sts_0, pmc_status;
  794. int ret;
  795. ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
  796. if (ret)
  797. return;
  798. mutex_lock(&lpss_iosf_mutex);
  799. ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
  800. if (ret)
  801. goto exit;
  802. /*
  803. * Get the status of entire LPSS power island per device basis.
  804. * Shutdown both LPSS DMA controllers if and only if all other devices
  805. * are already in D3hot.
  806. */
  807. pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
  808. if (pmc_status)
  809. goto exit;
  810. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
  811. LPSS_IOSF_PMCSR, value2, mask2);
  812. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
  813. LPSS_IOSF_PMCSR, value2, mask2);
  814. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
  815. LPSS_IOSF_GPIODEF0, value1, mask1);
  816. lpss_iosf_d3_entered = true;
  817. exit:
  818. mutex_unlock(&lpss_iosf_mutex);
  819. }
  820. static void lpss_iosf_exit_d3_state(void)
  821. {
  822. u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
  823. LPSS_GPIODEF0_DMA_LLP;
  824. u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
  825. u32 value2 = LPSS_PMCSR_D0;
  826. u32 mask2 = LPSS_PMCSR_Dx_MASK;
  827. mutex_lock(&lpss_iosf_mutex);
  828. if (!lpss_iosf_d3_entered)
  829. goto exit;
  830. lpss_iosf_d3_entered = false;
  831. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
  832. LPSS_IOSF_GPIODEF0, value1, mask1);
  833. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
  834. LPSS_IOSF_PMCSR, value2, mask2);
  835. iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
  836. LPSS_IOSF_PMCSR, value2, mask2);
  837. exit:
  838. mutex_unlock(&lpss_iosf_mutex);
  839. }
  840. static int acpi_lpss_suspend(struct device *dev, bool wakeup)
  841. {
  842. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  843. int ret;
  844. if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
  845. acpi_lpss_save_ctx(dev, pdata);
  846. ret = acpi_dev_suspend(dev, wakeup);
  847. /*
  848. * This call must be last in the sequence, otherwise PMC will return
  849. * wrong status for devices being about to be powered off. See
  850. * lpss_iosf_enter_d3_state() for further information.
  851. */
  852. if (acpi_target_system_state() == ACPI_STATE_S0 &&
  853. lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
  854. lpss_iosf_enter_d3_state();
  855. return ret;
  856. }
  857. static int acpi_lpss_resume(struct device *dev)
  858. {
  859. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  860. int ret;
  861. /*
  862. * This call is kept first to be in symmetry with
  863. * acpi_lpss_runtime_suspend() one.
  864. */
  865. if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
  866. lpss_iosf_exit_d3_state();
  867. ret = acpi_dev_resume(dev);
  868. if (ret)
  869. return ret;
  870. acpi_lpss_d3_to_d0_delay(pdata);
  871. if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
  872. acpi_lpss_restore_ctx(dev, pdata);
  873. return 0;
  874. }
  875. #ifdef CONFIG_PM_SLEEP
  876. static int acpi_lpss_do_suspend_late(struct device *dev)
  877. {
  878. int ret;
  879. if (dev_pm_skip_suspend(dev))
  880. return 0;
  881. ret = pm_generic_suspend_late(dev);
  882. return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
  883. }
  884. static int acpi_lpss_suspend_late(struct device *dev)
  885. {
  886. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  887. if (pdata->dev_desc->resume_from_noirq)
  888. return 0;
  889. return acpi_lpss_do_suspend_late(dev);
  890. }
  891. static int acpi_lpss_suspend_noirq(struct device *dev)
  892. {
  893. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  894. int ret;
  895. if (pdata->dev_desc->resume_from_noirq) {
  896. /*
  897. * The driver's ->suspend_late callback will be invoked by
  898. * acpi_lpss_do_suspend_late(), with the assumption that the
  899. * driver really wanted to run that code in ->suspend_noirq, but
  900. * it could not run after acpi_dev_suspend() and the driver
  901. * expected the latter to be called in the "late" phase.
  902. */
  903. ret = acpi_lpss_do_suspend_late(dev);
  904. if (ret)
  905. return ret;
  906. }
  907. return acpi_subsys_suspend_noirq(dev);
  908. }
  909. static int acpi_lpss_do_resume_early(struct device *dev)
  910. {
  911. int ret = acpi_lpss_resume(dev);
  912. return ret ? ret : pm_generic_resume_early(dev);
  913. }
  914. static int acpi_lpss_resume_early(struct device *dev)
  915. {
  916. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  917. if (pdata->dev_desc->resume_from_noirq)
  918. return 0;
  919. if (dev_pm_skip_resume(dev))
  920. return 0;
  921. return acpi_lpss_do_resume_early(dev);
  922. }
  923. static int acpi_lpss_resume_noirq(struct device *dev)
  924. {
  925. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  926. int ret;
  927. /* Follow acpi_subsys_resume_noirq(). */
  928. if (dev_pm_skip_resume(dev))
  929. return 0;
  930. ret = pm_generic_resume_noirq(dev);
  931. if (ret)
  932. return ret;
  933. if (!pdata->dev_desc->resume_from_noirq)
  934. return 0;
  935. /*
  936. * The driver's ->resume_early callback will be invoked by
  937. * acpi_lpss_do_resume_early(), with the assumption that the driver
  938. * really wanted to run that code in ->resume_noirq, but it could not
  939. * run before acpi_dev_resume() and the driver expected the latter to be
  940. * called in the "early" phase.
  941. */
  942. return acpi_lpss_do_resume_early(dev);
  943. }
  944. static int acpi_lpss_do_restore_early(struct device *dev)
  945. {
  946. int ret = acpi_lpss_resume(dev);
  947. return ret ? ret : pm_generic_restore_early(dev);
  948. }
  949. static int acpi_lpss_restore_early(struct device *dev)
  950. {
  951. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  952. if (pdata->dev_desc->resume_from_noirq)
  953. return 0;
  954. return acpi_lpss_do_restore_early(dev);
  955. }
  956. static int acpi_lpss_restore_noirq(struct device *dev)
  957. {
  958. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  959. int ret;
  960. ret = pm_generic_restore_noirq(dev);
  961. if (ret)
  962. return ret;
  963. if (!pdata->dev_desc->resume_from_noirq)
  964. return 0;
  965. /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
  966. return acpi_lpss_do_restore_early(dev);
  967. }
  968. static int acpi_lpss_do_poweroff_late(struct device *dev)
  969. {
  970. int ret = pm_generic_poweroff_late(dev);
  971. return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
  972. }
  973. static int acpi_lpss_poweroff_late(struct device *dev)
  974. {
  975. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  976. if (dev_pm_skip_suspend(dev))
  977. return 0;
  978. if (pdata->dev_desc->resume_from_noirq)
  979. return 0;
  980. return acpi_lpss_do_poweroff_late(dev);
  981. }
  982. static int acpi_lpss_poweroff_noirq(struct device *dev)
  983. {
  984. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  985. if (dev_pm_skip_suspend(dev))
  986. return 0;
  987. if (pdata->dev_desc->resume_from_noirq) {
  988. /* This is analogous to the acpi_lpss_suspend_noirq() case. */
  989. int ret = acpi_lpss_do_poweroff_late(dev);
  990. if (ret)
  991. return ret;
  992. }
  993. return pm_generic_poweroff_noirq(dev);
  994. }
  995. #endif /* CONFIG_PM_SLEEP */
  996. static int acpi_lpss_runtime_suspend(struct device *dev)
  997. {
  998. int ret = pm_generic_runtime_suspend(dev);
  999. return ret ? ret : acpi_lpss_suspend(dev, true);
  1000. }
  1001. static int acpi_lpss_runtime_resume(struct device *dev)
  1002. {
  1003. int ret = acpi_lpss_resume(dev);
  1004. return ret ? ret : pm_generic_runtime_resume(dev);
  1005. }
  1006. #endif /* CONFIG_PM */
  1007. static struct dev_pm_domain acpi_lpss_pm_domain = {
  1008. #ifdef CONFIG_PM
  1009. .activate = acpi_lpss_activate,
  1010. .dismiss = acpi_lpss_dismiss,
  1011. #endif
  1012. .ops = {
  1013. #ifdef CONFIG_PM
  1014. #ifdef CONFIG_PM_SLEEP
  1015. .prepare = acpi_subsys_prepare,
  1016. .complete = acpi_subsys_complete,
  1017. .suspend = acpi_subsys_suspend,
  1018. .suspend_late = acpi_lpss_suspend_late,
  1019. .suspend_noirq = acpi_lpss_suspend_noirq,
  1020. .resume_noirq = acpi_lpss_resume_noirq,
  1021. .resume_early = acpi_lpss_resume_early,
  1022. .freeze = acpi_subsys_freeze,
  1023. .poweroff = acpi_subsys_poweroff,
  1024. .poweroff_late = acpi_lpss_poweroff_late,
  1025. .poweroff_noirq = acpi_lpss_poweroff_noirq,
  1026. .restore_noirq = acpi_lpss_restore_noirq,
  1027. .restore_early = acpi_lpss_restore_early,
  1028. #endif
  1029. .runtime_suspend = acpi_lpss_runtime_suspend,
  1030. .runtime_resume = acpi_lpss_runtime_resume,
  1031. #endif
  1032. },
  1033. };
  1034. static int acpi_lpss_platform_notify(struct notifier_block *nb,
  1035. unsigned long action, void *data)
  1036. {
  1037. struct platform_device *pdev = to_platform_device(data);
  1038. struct lpss_private_data *pdata;
  1039. struct acpi_device *adev;
  1040. const struct acpi_device_id *id;
  1041. id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
  1042. if (!id || !id->driver_data)
  1043. return 0;
  1044. adev = ACPI_COMPANION(&pdev->dev);
  1045. if (!adev)
  1046. return 0;
  1047. pdata = acpi_driver_data(adev);
  1048. if (!pdata)
  1049. return 0;
  1050. if (pdata->mmio_base &&
  1051. pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
  1052. dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
  1053. return 0;
  1054. }
  1055. switch (action) {
  1056. case BUS_NOTIFY_BIND_DRIVER:
  1057. dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
  1058. break;
  1059. case BUS_NOTIFY_DRIVER_NOT_BOUND:
  1060. case BUS_NOTIFY_UNBOUND_DRIVER:
  1061. dev_pm_domain_set(&pdev->dev, NULL);
  1062. break;
  1063. case BUS_NOTIFY_ADD_DEVICE:
  1064. dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
  1065. if (pdata->dev_desc->flags & LPSS_LTR)
  1066. return sysfs_create_group(&pdev->dev.kobj,
  1067. &lpss_attr_group);
  1068. break;
  1069. case BUS_NOTIFY_DEL_DEVICE:
  1070. if (pdata->dev_desc->flags & LPSS_LTR)
  1071. sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
  1072. dev_pm_domain_set(&pdev->dev, NULL);
  1073. break;
  1074. default:
  1075. break;
  1076. }
  1077. return 0;
  1078. }
  1079. static struct notifier_block acpi_lpss_nb = {
  1080. .notifier_call = acpi_lpss_platform_notify,
  1081. };
  1082. static void acpi_lpss_bind(struct device *dev)
  1083. {
  1084. struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
  1085. if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
  1086. return;
  1087. if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
  1088. dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
  1089. else
  1090. dev_err(dev, "MMIO size insufficient to access LTR\n");
  1091. }
  1092. static void acpi_lpss_unbind(struct device *dev)
  1093. {
  1094. dev->power.set_latency_tolerance = NULL;
  1095. }
  1096. static struct acpi_scan_handler lpss_handler = {
  1097. .ids = acpi_lpss_device_ids,
  1098. .attach = acpi_lpss_create_device,
  1099. .bind = acpi_lpss_bind,
  1100. .unbind = acpi_lpss_unbind,
  1101. };
  1102. void __init acpi_lpss_init(void)
  1103. {
  1104. const struct x86_cpu_id *id;
  1105. int ret;
  1106. ret = lpss_atom_clk_init();
  1107. if (ret)
  1108. return;
  1109. id = x86_match_cpu(lpss_cpu_ids);
  1110. if (id)
  1111. lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
  1112. bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
  1113. acpi_scan_add_handler(&lpss_handler);
  1114. }
  1115. #else
  1116. static struct acpi_scan_handler lpss_handler = {
  1117. .ids = acpi_lpss_device_ids,
  1118. };
  1119. void __init acpi_lpss_init(void)
  1120. {
  1121. acpi_scan_add_handler(&lpss_handler);
  1122. }
  1123. #endif /* CONFIG_X86_INTEL_LPSS */