masking.c 8.5 KB

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  1. {
  2. "masking, test out of bounds 1",
  3. .insns = {
  4. BPF_MOV32_IMM(BPF_REG_1, 5),
  5. BPF_MOV32_IMM(BPF_REG_2, 5 - 1),
  6. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  7. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  8. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  9. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  10. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  11. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  12. BPF_EXIT_INSN(),
  13. },
  14. .result = ACCEPT,
  15. .retval = 0,
  16. },
  17. {
  18. "masking, test out of bounds 2",
  19. .insns = {
  20. BPF_MOV32_IMM(BPF_REG_1, 1),
  21. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  22. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  23. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  24. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  25. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  26. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  27. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  28. BPF_EXIT_INSN(),
  29. },
  30. .result = ACCEPT,
  31. .retval = 0,
  32. },
  33. {
  34. "masking, test out of bounds 3",
  35. .insns = {
  36. BPF_MOV32_IMM(BPF_REG_1, 0xffffffff),
  37. BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
  38. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  39. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  40. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  41. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  42. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  43. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  44. BPF_EXIT_INSN(),
  45. },
  46. .result = ACCEPT,
  47. .retval = 0,
  48. },
  49. {
  50. "masking, test out of bounds 4",
  51. .insns = {
  52. BPF_MOV32_IMM(BPF_REG_1, 0xffffffff),
  53. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  54. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  55. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  56. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  57. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  58. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  59. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  60. BPF_EXIT_INSN(),
  61. },
  62. .result = ACCEPT,
  63. .retval = 0,
  64. },
  65. {
  66. "masking, test out of bounds 5",
  67. .insns = {
  68. BPF_MOV32_IMM(BPF_REG_1, -1),
  69. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  70. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  71. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  72. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  73. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  74. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  75. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  76. BPF_EXIT_INSN(),
  77. },
  78. .result = ACCEPT,
  79. .retval = 0,
  80. },
  81. {
  82. "masking, test out of bounds 6",
  83. .insns = {
  84. BPF_MOV32_IMM(BPF_REG_1, -1),
  85. BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
  86. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  87. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  88. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  89. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  90. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  91. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  92. BPF_EXIT_INSN(),
  93. },
  94. .result = ACCEPT,
  95. .retval = 0,
  96. },
  97. {
  98. "masking, test out of bounds 7",
  99. .insns = {
  100. BPF_MOV64_IMM(BPF_REG_1, 5),
  101. BPF_MOV32_IMM(BPF_REG_2, 5 - 1),
  102. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  103. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  104. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  105. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  106. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  107. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  108. BPF_EXIT_INSN(),
  109. },
  110. .result = ACCEPT,
  111. .retval = 0,
  112. },
  113. {
  114. "masking, test out of bounds 8",
  115. .insns = {
  116. BPF_MOV64_IMM(BPF_REG_1, 1),
  117. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  118. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  119. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  120. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  121. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  122. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  123. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  124. BPF_EXIT_INSN(),
  125. },
  126. .result = ACCEPT,
  127. .retval = 0,
  128. },
  129. {
  130. "masking, test out of bounds 9",
  131. .insns = {
  132. BPF_MOV64_IMM(BPF_REG_1, 0xffffffff),
  133. BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
  134. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  135. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  136. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  137. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  138. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  139. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  140. BPF_EXIT_INSN(),
  141. },
  142. .result = ACCEPT,
  143. .retval = 0,
  144. },
  145. {
  146. "masking, test out of bounds 10",
  147. .insns = {
  148. BPF_MOV64_IMM(BPF_REG_1, 0xffffffff),
  149. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  150. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  151. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  152. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  153. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  154. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  155. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  156. BPF_EXIT_INSN(),
  157. },
  158. .result = ACCEPT,
  159. .retval = 0,
  160. },
  161. {
  162. "masking, test out of bounds 11",
  163. .insns = {
  164. BPF_MOV64_IMM(BPF_REG_1, -1),
  165. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  166. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  167. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  168. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  169. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  170. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  171. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  172. BPF_EXIT_INSN(),
  173. },
  174. .result = ACCEPT,
  175. .retval = 0,
  176. },
  177. {
  178. "masking, test out of bounds 12",
  179. .insns = {
  180. BPF_MOV64_IMM(BPF_REG_1, -1),
  181. BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
  182. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  183. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  184. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  185. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  186. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  187. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  188. BPF_EXIT_INSN(),
  189. },
  190. .result = ACCEPT,
  191. .retval = 0,
  192. },
  193. {
  194. "masking, test in bounds 1",
  195. .insns = {
  196. BPF_MOV32_IMM(BPF_REG_1, 4),
  197. BPF_MOV32_IMM(BPF_REG_2, 5 - 1),
  198. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  199. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  200. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  201. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  202. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  203. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  204. BPF_EXIT_INSN(),
  205. },
  206. .result = ACCEPT,
  207. .retval = 4,
  208. },
  209. {
  210. "masking, test in bounds 2",
  211. .insns = {
  212. BPF_MOV32_IMM(BPF_REG_1, 0),
  213. BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
  214. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  215. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  216. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  217. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  218. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  219. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  220. BPF_EXIT_INSN(),
  221. },
  222. .result = ACCEPT,
  223. .retval = 0,
  224. },
  225. {
  226. "masking, test in bounds 3",
  227. .insns = {
  228. BPF_MOV32_IMM(BPF_REG_1, 0xfffffffe),
  229. BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
  230. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  231. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  232. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  233. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  234. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  235. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  236. BPF_EXIT_INSN(),
  237. },
  238. .result = ACCEPT,
  239. .retval = 0xfffffffe,
  240. },
  241. {
  242. "masking, test in bounds 4",
  243. .insns = {
  244. BPF_MOV32_IMM(BPF_REG_1, 0xabcde),
  245. BPF_MOV32_IMM(BPF_REG_2, 0xabcdef - 1),
  246. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  247. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  248. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  249. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  250. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  251. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  252. BPF_EXIT_INSN(),
  253. },
  254. .result = ACCEPT,
  255. .retval = 0xabcde,
  256. },
  257. {
  258. "masking, test in bounds 5",
  259. .insns = {
  260. BPF_MOV32_IMM(BPF_REG_1, 0),
  261. BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
  262. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  263. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  264. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  265. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  266. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  267. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  268. BPF_EXIT_INSN(),
  269. },
  270. .result = ACCEPT,
  271. .retval = 0,
  272. },
  273. {
  274. "masking, test in bounds 6",
  275. .insns = {
  276. BPF_MOV32_IMM(BPF_REG_1, 46),
  277. BPF_MOV32_IMM(BPF_REG_2, 47 - 1),
  278. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
  279. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
  280. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  281. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  282. BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
  283. BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
  284. BPF_EXIT_INSN(),
  285. },
  286. .result = ACCEPT,
  287. .retval = 46,
  288. },
  289. {
  290. "masking, test in bounds 7",
  291. .insns = {
  292. BPF_MOV64_IMM(BPF_REG_3, -46),
  293. BPF_ALU64_IMM(BPF_MUL, BPF_REG_3, -1),
  294. BPF_MOV32_IMM(BPF_REG_2, 47 - 1),
  295. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_3),
  296. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_3),
  297. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  298. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  299. BPF_ALU64_REG(BPF_AND, BPF_REG_3, BPF_REG_2),
  300. BPF_MOV64_REG(BPF_REG_0, BPF_REG_3),
  301. BPF_EXIT_INSN(),
  302. },
  303. .result = ACCEPT,
  304. .retval = 46,
  305. },
  306. {
  307. "masking, test in bounds 8",
  308. .insns = {
  309. BPF_MOV64_IMM(BPF_REG_3, -47),
  310. BPF_ALU64_IMM(BPF_MUL, BPF_REG_3, -1),
  311. BPF_MOV32_IMM(BPF_REG_2, 47 - 1),
  312. BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_3),
  313. BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_3),
  314. BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
  315. BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
  316. BPF_ALU64_REG(BPF_AND, BPF_REG_3, BPF_REG_2),
  317. BPF_MOV64_REG(BPF_REG_0, BPF_REG_3),
  318. BPF_EXIT_INSN(),
  319. },
  320. .result = ACCEPT,
  321. .retval = 0,
  322. },