aio.h 9.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Socionext UniPhier AIO ALSA driver.
  4. *
  5. * Copyright (c) 2016-2018 Socionext Inc.
  6. */
  7. #ifndef SND_UNIPHIER_AIO_H__
  8. #define SND_UNIPHIER_AIO_H__
  9. #include <linux/spinlock.h>
  10. #include <linux/types.h>
  11. #include <sound/pcm.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dai.h>
  14. struct platform_device;
  15. enum ID_PORT_TYPE {
  16. PORT_TYPE_UNKNOWN,
  17. PORT_TYPE_I2S,
  18. PORT_TYPE_SPDIF,
  19. PORT_TYPE_EVE,
  20. PORT_TYPE_CONV,
  21. };
  22. enum ID_PORT_DIR {
  23. PORT_DIR_OUTPUT,
  24. PORT_DIR_INPUT,
  25. };
  26. enum IEC61937_PC {
  27. IEC61937_PC_AC3 = 0x0001,
  28. IEC61937_PC_PAUSE = 0x0003,
  29. IEC61937_PC_MPA = 0x0004,
  30. IEC61937_PC_MP3 = 0x0005,
  31. IEC61937_PC_DTS1 = 0x000b,
  32. IEC61937_PC_DTS2 = 0x000c,
  33. IEC61937_PC_DTS3 = 0x000d,
  34. IEC61937_PC_AAC = 0x0007,
  35. };
  36. /* IEC61937 Repetition period of data-burst in IEC60958 frames */
  37. #define IEC61937_FRM_STR_AC3 1536
  38. #define IEC61937_FRM_STR_MPA 1152
  39. #define IEC61937_FRM_STR_MP3 1152
  40. #define IEC61937_FRM_STR_DTS1 512
  41. #define IEC61937_FRM_STR_DTS2 1024
  42. #define IEC61937_FRM_STR_DTS3 2048
  43. #define IEC61937_FRM_STR_AAC 1024
  44. /* IEC61937 Repetition period of Pause data-burst in IEC60958 frames */
  45. #define IEC61937_FRM_PAU_AC3 3
  46. #define IEC61937_FRM_PAU_MPA 32
  47. #define IEC61937_FRM_PAU_MP3 32
  48. #define IEC61937_FRM_PAU_DTS1 3
  49. #define IEC61937_FRM_PAU_DTS2 3
  50. #define IEC61937_FRM_PAU_DTS3 3
  51. #define IEC61937_FRM_PAU_AAC 32
  52. /* IEC61937 Pa and Pb */
  53. #define IEC61937_HEADER_SIGN 0x1f4e72f8
  54. #define AUD_HW_PCMIN1 0
  55. #define AUD_HW_PCMIN2 1
  56. #define AUD_HW_PCMIN3 2
  57. #define AUD_HW_IECIN1 3
  58. #define AUD_HW_DIECIN1 4
  59. #define AUD_NAME_PCMIN1 "aio-pcmin1"
  60. #define AUD_NAME_PCMIN2 "aio-pcmin2"
  61. #define AUD_NAME_PCMIN3 "aio-pcmin3"
  62. #define AUD_NAME_IECIN1 "aio-iecin1"
  63. #define AUD_NAME_DIECIN1 "aio-diecin1"
  64. #define AUD_HW_HPCMOUT1 0
  65. #define AUD_HW_PCMOUT1 1
  66. #define AUD_HW_PCMOUT2 2
  67. #define AUD_HW_PCMOUT3 3
  68. #define AUD_HW_EPCMOUT1 4
  69. #define AUD_HW_EPCMOUT2 5
  70. #define AUD_HW_EPCMOUT3 6
  71. #define AUD_HW_EPCMOUT6 9
  72. #define AUD_HW_HIECOUT1 10
  73. #define AUD_HW_IECOUT1 11
  74. #define AUD_HW_CMASTER 31
  75. #define AUD_NAME_HPCMOUT1 "aio-hpcmout1"
  76. #define AUD_NAME_PCMOUT1 "aio-pcmout1"
  77. #define AUD_NAME_PCMOUT2 "aio-pcmout2"
  78. #define AUD_NAME_PCMOUT3 "aio-pcmout3"
  79. #define AUD_NAME_EPCMOUT1 "aio-epcmout1"
  80. #define AUD_NAME_EPCMOUT2 "aio-epcmout2"
  81. #define AUD_NAME_EPCMOUT3 "aio-epcmout3"
  82. #define AUD_NAME_EPCMOUT6 "aio-epcmout6"
  83. #define AUD_NAME_HIECOUT1 "aio-hiecout1"
  84. #define AUD_NAME_IECOUT1 "aio-iecout1"
  85. #define AUD_NAME_CMASTER "aio-cmaster"
  86. #define AUD_NAME_HIECCOMPOUT1 "aio-hieccompout1"
  87. #define AUD_NAME_IECCOMPOUT1 "aio-ieccompout1"
  88. #define AUD_GNAME_HDMI "aio-hdmi"
  89. #define AUD_GNAME_LINE "aio-line"
  90. #define AUD_GNAME_AUX "aio-aux"
  91. #define AUD_GNAME_IEC "aio-iec"
  92. #define AUD_CLK_IO 0
  93. #define AUD_CLK_A1 1
  94. #define AUD_CLK_F1 2
  95. #define AUD_CLK_A2 3
  96. #define AUD_CLK_F2 4
  97. #define AUD_CLK_A 5
  98. #define AUD_CLK_F 6
  99. #define AUD_CLK_APLL 7
  100. #define AUD_CLK_RX0 8
  101. #define AUD_CLK_USB0 9
  102. #define AUD_CLK_HSC0 10
  103. #define AUD_PLL_A1 0
  104. #define AUD_PLL_F1 1
  105. #define AUD_PLL_A2 2
  106. #define AUD_PLL_F2 3
  107. #define AUD_PLL_APLL 4
  108. #define AUD_PLL_RX0 5
  109. #define AUD_PLL_USB0 6
  110. #define AUD_PLL_HSC0 7
  111. #define AUD_PLLDIV_1_2 0
  112. #define AUD_PLLDIV_1_3 1
  113. #define AUD_PLLDIV_1_1 2
  114. #define AUD_PLLDIV_2_3 3
  115. #define AUD_VOL_INIT 0x4000 /* +0dB */
  116. #define AUD_VOL_MAX 0xffff /* +6dB */
  117. #define AUD_VOL_FADE_TIME 20 /* 20ms */
  118. #define AUD_RING_SIZE (128 * 1024)
  119. #define AUD_MIN_FRAGMENT 4
  120. #define AUD_MAX_FRAGMENT 8
  121. #define AUD_MIN_FRAGMENT_SIZE (4 * 1024)
  122. #define AUD_MAX_FRAGMENT_SIZE (16 * 1024)
  123. /* max 5 slots, 10 channels, 2 channel in 1 slot */
  124. #define AUD_MAX_SLOTSEL 5
  125. /*
  126. * This is a selector for virtual register map of AIO.
  127. *
  128. * map: Specify the index of virtual register map.
  129. * hw : Specify the ID of real register map, selector uses this value.
  130. * A meaning of this value depends specification of SoC.
  131. */
  132. struct uniphier_aio_selector {
  133. int map;
  134. int hw;
  135. };
  136. /**
  137. * 'SoftWare MAPping' setting of UniPhier AIO registers.
  138. *
  139. * We have to setup 'virtual' register maps to access 'real' registers of AIO.
  140. * This feature is legacy and meaningless but AIO needs this to work.
  141. *
  142. * Each hardware blocks have own virtual register maps as following:
  143. *
  144. * Address Virtual Real
  145. * ------- --------- ---------------
  146. * 0x12000 DMAC map0 --> [selector] --> DMAC hardware 3
  147. * 0x12080 DMAC map1 --> [selector] --> DMAC hardware 1
  148. * ...
  149. * 0x42000 Port map0 --> [selector] --> Port hardware 1
  150. * 0x42400 Port map1 --> [selector] --> Port hardware 2
  151. * ...
  152. *
  153. * ch : Input or output channel of DMAC
  154. * rb : Ring buffer
  155. * iport: PCM input port
  156. * iif : Input interface
  157. * oport: PCM output port
  158. * oif : Output interface
  159. * och : Output channel of DMAC for sampling rate converter
  160. *
  161. * These are examples for sound data paths:
  162. *
  163. * For caputure device:
  164. * (outer of AIO) -> iport -> iif -> ch -> rb -> (CPU)
  165. * For playback device:
  166. * (CPU) -> rb -> ch -> oif -> oport -> (outer of AIO)
  167. * For sampling rate converter device:
  168. * (CPU) -> rb -> ch -> oif -> (HW SRC) -> iif -> och -> orb -> (CPU)
  169. */
  170. struct uniphier_aio_swmap {
  171. int type;
  172. int dir;
  173. struct uniphier_aio_selector ch;
  174. struct uniphier_aio_selector rb;
  175. struct uniphier_aio_selector iport;
  176. struct uniphier_aio_selector iif;
  177. struct uniphier_aio_selector oport;
  178. struct uniphier_aio_selector oif;
  179. struct uniphier_aio_selector och;
  180. };
  181. struct uniphier_aio_spec {
  182. const char *name;
  183. const char *gname;
  184. struct uniphier_aio_swmap swm;
  185. };
  186. struct uniphier_aio_pll {
  187. bool enable;
  188. unsigned int freq;
  189. };
  190. struct uniphier_aio_chip_spec {
  191. const struct uniphier_aio_spec *specs;
  192. int num_specs;
  193. const struct uniphier_aio_pll *plls;
  194. int num_plls;
  195. struct snd_soc_dai_driver *dais;
  196. int num_dais;
  197. /* DMA access mode, this is workaround for DMA hungup */
  198. int addr_ext;
  199. };
  200. struct uniphier_aio_sub {
  201. struct uniphier_aio *aio;
  202. /* Guard sub->rd_offs and wr_offs from IRQ handler. */
  203. spinlock_t lock;
  204. const struct uniphier_aio_swmap *swm;
  205. const struct uniphier_aio_spec *spec;
  206. /* For PCM audio */
  207. struct snd_pcm_substream *substream;
  208. struct snd_pcm_hw_params params;
  209. int vol;
  210. /* For compress audio */
  211. struct snd_compr_stream *cstream;
  212. struct snd_compr_params cparams;
  213. unsigned char *compr_area;
  214. dma_addr_t compr_addr;
  215. size_t compr_bytes;
  216. int pass_through;
  217. enum IEC61937_PC iec_pc;
  218. bool iec_header;
  219. /* Both PCM and compress audio */
  220. bool use_mmap;
  221. int setting;
  222. int running;
  223. u64 rd_offs;
  224. u64 wr_offs;
  225. u32 threshold;
  226. u64 rd_org;
  227. u64 wr_org;
  228. u64 rd_total;
  229. u64 wr_total;
  230. };
  231. struct uniphier_aio {
  232. struct uniphier_aio_chip *chip;
  233. struct uniphier_aio_sub sub[2];
  234. unsigned int fmt;
  235. /* Set one of AUD_CLK_X */
  236. int clk_in;
  237. int clk_out;
  238. /* Set one of AUD_PLL_X */
  239. int pll_in;
  240. int pll_out;
  241. /* Set one of AUD_PLLDIV_X */
  242. int plldiv;
  243. };
  244. struct uniphier_aio_chip {
  245. struct platform_device *pdev;
  246. const struct uniphier_aio_chip_spec *chip_spec;
  247. struct uniphier_aio *aios;
  248. int num_aios;
  249. int num_wup_aios;
  250. struct uniphier_aio_pll *plls;
  251. int num_plls;
  252. struct clk *clk;
  253. struct reset_control *rst;
  254. struct regmap *regmap;
  255. struct regmap *regmap_sg;
  256. int active;
  257. };
  258. static inline struct uniphier_aio *uniphier_priv(struct snd_soc_dai *dai)
  259. {
  260. struct uniphier_aio_chip *chip = snd_soc_dai_get_drvdata(dai);
  261. return &chip->aios[dai->id];
  262. }
  263. int uniphier_aiodma_soc_register_platform(struct platform_device *pdev);
  264. extern const struct snd_compress_ops uniphier_aio_compress_ops;
  265. int uniphier_aio_dai_probe(struct snd_soc_dai *dai);
  266. int uniphier_aio_dai_remove(struct snd_soc_dai *dai);
  267. int uniphier_aio_probe(struct platform_device *pdev);
  268. int uniphier_aio_remove(struct platform_device *pdev);
  269. extern const struct snd_soc_dai_ops uniphier_aio_i2s_ops;
  270. extern const struct snd_soc_dai_ops uniphier_aio_spdif_ops;
  271. u64 aio_rb_cnt(struct uniphier_aio_sub *sub);
  272. u64 aio_rbt_cnt_to_end(struct uniphier_aio_sub *sub);
  273. u64 aio_rb_space(struct uniphier_aio_sub *sub);
  274. u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub);
  275. void aio_iecout_set_enable(struct uniphier_aio_chip *chip, bool enable);
  276. int aio_chip_set_pll(struct uniphier_aio_chip *chip, int pll_id,
  277. unsigned int freq);
  278. void aio_chip_init(struct uniphier_aio_chip *chip);
  279. int aio_init(struct uniphier_aio_sub *sub);
  280. void aio_port_reset(struct uniphier_aio_sub *sub);
  281. int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through,
  282. const struct snd_pcm_hw_params *params);
  283. void aio_port_set_enable(struct uniphier_aio_sub *sub, int enable);
  284. int aio_port_get_volume(struct uniphier_aio_sub *sub);
  285. void aio_port_set_volume(struct uniphier_aio_sub *sub, int vol);
  286. int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through);
  287. int aio_oport_set_stream_type(struct uniphier_aio_sub *sub,
  288. enum IEC61937_PC pc);
  289. void aio_src_reset(struct uniphier_aio_sub *sub);
  290. int aio_src_set_param(struct uniphier_aio_sub *sub,
  291. const struct snd_pcm_hw_params *params);
  292. int aio_srcif_set_param(struct uniphier_aio_sub *sub);
  293. int aio_srcch_set_param(struct uniphier_aio_sub *sub);
  294. void aio_srcch_set_enable(struct uniphier_aio_sub *sub, int enable);
  295. int aiodma_ch_set_param(struct uniphier_aio_sub *sub);
  296. void aiodma_ch_set_enable(struct uniphier_aio_sub *sub, int enable);
  297. int aiodma_rb_set_threshold(struct uniphier_aio_sub *sub, u64 size, u32 th);
  298. int aiodma_rb_set_buffer(struct uniphier_aio_sub *sub, u64 start, u64 end,
  299. int period);
  300. void aiodma_rb_sync(struct uniphier_aio_sub *sub, u64 start, u64 size,
  301. int period);
  302. bool aiodma_rb_is_irq(struct uniphier_aio_sub *sub);
  303. void aiodma_rb_clear_irq(struct uniphier_aio_sub *sub);
  304. #endif /* SND_UNIPHIER_AIO_H__ */