omap-mcbsp.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
  4. *
  5. * Copyright (C) 2008 Nokia Corporation
  6. *
  7. * Contact: Jarkko Nikula <[email protected]>
  8. * Peter Ujfalusi <[email protected]>
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/initval.h>
  20. #include <sound/soc.h>
  21. #include <sound/dmaengine_pcm.h>
  22. #include "omap-mcbsp-priv.h"
  23. #include "omap-mcbsp.h"
  24. #include "sdma-pcm.h"
  25. #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
  26. enum {
  27. OMAP_MCBSP_WORD_8 = 0,
  28. OMAP_MCBSP_WORD_12,
  29. OMAP_MCBSP_WORD_16,
  30. OMAP_MCBSP_WORD_20,
  31. OMAP_MCBSP_WORD_24,
  32. OMAP_MCBSP_WORD_32,
  33. };
  34. static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  35. {
  36. dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  37. dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
  38. dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
  39. dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
  40. dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
  41. dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
  42. dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
  43. dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
  44. dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
  45. dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
  46. dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
  47. dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
  48. dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
  49. dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
  50. dev_dbg(mcbsp->dev, "***********************\n");
  51. }
  52. static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
  53. {
  54. struct clk *fck_src;
  55. const char *src;
  56. int r;
  57. if (fck_src_id == MCBSP_CLKS_PAD_SRC)
  58. src = "pad_fck";
  59. else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
  60. src = "prcm_fck";
  61. else
  62. return -EINVAL;
  63. fck_src = clk_get(mcbsp->dev, src);
  64. if (IS_ERR(fck_src)) {
  65. dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
  66. return -EINVAL;
  67. }
  68. if (mcbsp->active)
  69. pm_runtime_put_sync(mcbsp->dev);
  70. r = clk_set_parent(mcbsp->fclk, fck_src);
  71. if (r)
  72. dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
  73. src);
  74. if (mcbsp->active)
  75. pm_runtime_get_sync(mcbsp->dev);
  76. clk_put(fck_src);
  77. return r;
  78. }
  79. static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
  80. {
  81. struct omap_mcbsp *mcbsp = data;
  82. u16 irqst;
  83. irqst = MCBSP_READ(mcbsp, IRQST);
  84. dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
  85. if (irqst & RSYNCERREN)
  86. dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
  87. if (irqst & RFSREN)
  88. dev_dbg(mcbsp->dev, "RX Frame Sync\n");
  89. if (irqst & REOFEN)
  90. dev_dbg(mcbsp->dev, "RX End Of Frame\n");
  91. if (irqst & RRDYEN)
  92. dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
  93. if (irqst & RUNDFLEN)
  94. dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
  95. if (irqst & ROVFLEN)
  96. dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
  97. if (irqst & XSYNCERREN)
  98. dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
  99. if (irqst & XFSXEN)
  100. dev_dbg(mcbsp->dev, "TX Frame Sync\n");
  101. if (irqst & XEOFEN)
  102. dev_dbg(mcbsp->dev, "TX End Of Frame\n");
  103. if (irqst & XRDYEN)
  104. dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
  105. if (irqst & XUNDFLEN)
  106. dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
  107. if (irqst & XOVFLEN)
  108. dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
  109. if (irqst & XEMPTYEOFEN)
  110. dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
  111. MCBSP_WRITE(mcbsp, IRQST, irqst);
  112. return IRQ_HANDLED;
  113. }
  114. static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
  115. {
  116. struct omap_mcbsp *mcbsp = data;
  117. u16 irqst_spcr2;
  118. irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
  119. dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  120. if (irqst_spcr2 & XSYNC_ERR) {
  121. dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
  122. irqst_spcr2);
  123. /* Writing zero to XSYNC_ERR clears the IRQ */
  124. MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
  125. }
  126. return IRQ_HANDLED;
  127. }
  128. static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
  129. {
  130. struct omap_mcbsp *mcbsp = data;
  131. u16 irqst_spcr1;
  132. irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
  133. dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
  134. if (irqst_spcr1 & RSYNC_ERR) {
  135. dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
  136. irqst_spcr1);
  137. /* Writing zero to RSYNC_ERR clears the IRQ */
  138. MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
  139. }
  140. return IRQ_HANDLED;
  141. }
  142. /*
  143. * omap_mcbsp_config simply write a config to the
  144. * appropriate McBSP.
  145. * You either call this function or set the McBSP registers
  146. * by yourself before calling omap_mcbsp_start().
  147. */
  148. static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
  149. const struct omap_mcbsp_reg_cfg *config)
  150. {
  151. dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
  152. mcbsp->id, mcbsp->phys_base);
  153. /* We write the given config */
  154. MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
  155. MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
  156. MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
  157. MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
  158. MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
  159. MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
  160. MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
  161. MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
  162. MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
  163. MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
  164. MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
  165. if (mcbsp->pdata->has_ccr) {
  166. MCBSP_WRITE(mcbsp, XCCR, config->xccr);
  167. MCBSP_WRITE(mcbsp, RCCR, config->rccr);
  168. }
  169. /* Enable wakeup behavior */
  170. if (mcbsp->pdata->has_wakeup)
  171. MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
  172. /* Enable TX/RX sync error interrupts by default */
  173. if (mcbsp->irq)
  174. MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
  175. RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
  176. }
  177. /**
  178. * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
  179. * @mcbsp: omap_mcbsp struct for the McBSP instance
  180. * @stream: Stream direction (playback/capture)
  181. *
  182. * Returns the address of mcbsp data transmit register or data receive register
  183. * to be used by DMA for transferring/receiving data
  184. */
  185. static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
  186. unsigned int stream)
  187. {
  188. int data_reg;
  189. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  190. if (mcbsp->pdata->reg_size == 2)
  191. data_reg = OMAP_MCBSP_REG_DXR1;
  192. else
  193. data_reg = OMAP_MCBSP_REG_DXR;
  194. } else {
  195. if (mcbsp->pdata->reg_size == 2)
  196. data_reg = OMAP_MCBSP_REG_DRR1;
  197. else
  198. data_reg = OMAP_MCBSP_REG_DRR;
  199. }
  200. return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
  201. }
  202. /*
  203. * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
  204. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  205. * for the THRSH2 register.
  206. */
  207. static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
  208. {
  209. if (threshold && threshold <= mcbsp->max_tx_thres)
  210. MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
  211. }
  212. /*
  213. * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
  214. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  215. * for the THRSH1 register.
  216. */
  217. static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
  218. {
  219. if (threshold && threshold <= mcbsp->max_rx_thres)
  220. MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
  221. }
  222. /*
  223. * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
  224. */
  225. static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
  226. {
  227. u16 buffstat;
  228. /* Returns the number of free locations in the buffer */
  229. buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
  230. /* Number of slots are different in McBSP ports */
  231. return mcbsp->pdata->buffer_size - buffstat;
  232. }
  233. /*
  234. * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
  235. * to reach the threshold value (when the DMA will be triggered to read it)
  236. */
  237. static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
  238. {
  239. u16 buffstat, threshold;
  240. /* Returns the number of used locations in the buffer */
  241. buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
  242. /* RX threshold */
  243. threshold = MCBSP_READ(mcbsp, THRSH1);
  244. /* Return the number of location till we reach the threshold limit */
  245. if (threshold <= buffstat)
  246. return 0;
  247. else
  248. return threshold - buffstat;
  249. }
  250. static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
  251. {
  252. void *reg_cache;
  253. int err;
  254. reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
  255. if (!reg_cache)
  256. return -ENOMEM;
  257. spin_lock(&mcbsp->lock);
  258. if (!mcbsp->free) {
  259. dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
  260. err = -EBUSY;
  261. goto err_kfree;
  262. }
  263. mcbsp->free = false;
  264. mcbsp->reg_cache = reg_cache;
  265. spin_unlock(&mcbsp->lock);
  266. if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
  267. mcbsp->pdata->ops->request(mcbsp->id - 1);
  268. /*
  269. * Make sure that transmitter, receiver and sample-rate generator are
  270. * not running before activating IRQs.
  271. */
  272. MCBSP_WRITE(mcbsp, SPCR1, 0);
  273. MCBSP_WRITE(mcbsp, SPCR2, 0);
  274. if (mcbsp->irq) {
  275. err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
  276. "McBSP", (void *)mcbsp);
  277. if (err != 0) {
  278. dev_err(mcbsp->dev, "Unable to request IRQ\n");
  279. goto err_clk_disable;
  280. }
  281. } else {
  282. err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
  283. "McBSP TX", (void *)mcbsp);
  284. if (err != 0) {
  285. dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
  286. goto err_clk_disable;
  287. }
  288. err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
  289. "McBSP RX", (void *)mcbsp);
  290. if (err != 0) {
  291. dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
  292. goto err_free_irq;
  293. }
  294. }
  295. return 0;
  296. err_free_irq:
  297. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  298. err_clk_disable:
  299. if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  300. mcbsp->pdata->ops->free(mcbsp->id - 1);
  301. /* Disable wakeup behavior */
  302. if (mcbsp->pdata->has_wakeup)
  303. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  304. spin_lock(&mcbsp->lock);
  305. mcbsp->free = true;
  306. mcbsp->reg_cache = NULL;
  307. err_kfree:
  308. spin_unlock(&mcbsp->lock);
  309. kfree(reg_cache);
  310. return err;
  311. }
  312. static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
  313. {
  314. void *reg_cache;
  315. if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  316. mcbsp->pdata->ops->free(mcbsp->id - 1);
  317. /* Disable wakeup behavior */
  318. if (mcbsp->pdata->has_wakeup)
  319. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  320. /* Disable interrupt requests */
  321. if (mcbsp->irq) {
  322. MCBSP_WRITE(mcbsp, IRQEN, 0);
  323. free_irq(mcbsp->irq, (void *)mcbsp);
  324. } else {
  325. free_irq(mcbsp->rx_irq, (void *)mcbsp);
  326. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  327. }
  328. reg_cache = mcbsp->reg_cache;
  329. /*
  330. * Select CLKS source from internal source unconditionally before
  331. * marking the McBSP port as free.
  332. * If the external clock source via MCBSP_CLKS pin has been selected the
  333. * system will refuse to enter idle if the CLKS pin source is not reset
  334. * back to internal source.
  335. */
  336. if (!mcbsp_omap1())
  337. omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
  338. spin_lock(&mcbsp->lock);
  339. if (mcbsp->free)
  340. dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
  341. else
  342. mcbsp->free = true;
  343. mcbsp->reg_cache = NULL;
  344. spin_unlock(&mcbsp->lock);
  345. kfree(reg_cache);
  346. }
  347. /*
  348. * Here we start the McBSP, by enabling transmitter, receiver or both.
  349. * If no transmitter or receiver is active prior calling, then sample-rate
  350. * generator and frame sync are started.
  351. */
  352. static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
  353. {
  354. int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
  355. int rx = !tx;
  356. int enable_srg = 0;
  357. u16 w;
  358. if (mcbsp->st_data)
  359. omap_mcbsp_st_start(mcbsp);
  360. /* Only enable SRG, if McBSP is master */
  361. w = MCBSP_READ_CACHE(mcbsp, PCR0);
  362. if (w & (FSXM | FSRM | CLKXM | CLKRM))
  363. enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  364. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  365. if (enable_srg) {
  366. /* Start the sample generator */
  367. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  368. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
  369. }
  370. /* Enable transmitter and receiver */
  371. tx &= 1;
  372. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  373. MCBSP_WRITE(mcbsp, SPCR2, w | tx);
  374. rx &= 1;
  375. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  376. MCBSP_WRITE(mcbsp, SPCR1, w | rx);
  377. /*
  378. * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
  379. * REVISIT: 100us may give enough time for two CLKSRG, however
  380. * due to some unknown PM related, clock gating etc. reason it
  381. * is now at 500us.
  382. */
  383. udelay(500);
  384. if (enable_srg) {
  385. /* Start frame sync */
  386. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  387. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
  388. }
  389. if (mcbsp->pdata->has_ccr) {
  390. /* Release the transmitter and receiver */
  391. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  392. w &= ~(tx ? XDISABLE : 0);
  393. MCBSP_WRITE(mcbsp, XCCR, w);
  394. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  395. w &= ~(rx ? RDISABLE : 0);
  396. MCBSP_WRITE(mcbsp, RCCR, w);
  397. }
  398. /* Dump McBSP Regs */
  399. omap_mcbsp_dump_reg(mcbsp);
  400. }
  401. static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
  402. {
  403. int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
  404. int rx = !tx;
  405. int idle;
  406. u16 w;
  407. /* Reset transmitter */
  408. tx &= 1;
  409. if (mcbsp->pdata->has_ccr) {
  410. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  411. w |= (tx ? XDISABLE : 0);
  412. MCBSP_WRITE(mcbsp, XCCR, w);
  413. }
  414. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  415. MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
  416. /* Reset receiver */
  417. rx &= 1;
  418. if (mcbsp->pdata->has_ccr) {
  419. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  420. w |= (rx ? RDISABLE : 0);
  421. MCBSP_WRITE(mcbsp, RCCR, w);
  422. }
  423. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  424. MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
  425. idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  426. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  427. if (idle) {
  428. /* Reset the sample rate generator */
  429. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  430. MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
  431. }
  432. if (mcbsp->st_data)
  433. omap_mcbsp_st_stop(mcbsp);
  434. }
  435. #define max_thres(m) (mcbsp->pdata->buffer_size)
  436. #define valid_threshold(m, val) ((val) <= max_thres(m))
  437. #define THRESHOLD_PROP_BUILDER(prop) \
  438. static ssize_t prop##_show(struct device *dev, \
  439. struct device_attribute *attr, char *buf) \
  440. { \
  441. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  442. \
  443. return sysfs_emit(buf, "%u\n", mcbsp->prop); \
  444. } \
  445. \
  446. static ssize_t prop##_store(struct device *dev, \
  447. struct device_attribute *attr, \
  448. const char *buf, size_t size) \
  449. { \
  450. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  451. unsigned long val; \
  452. int status; \
  453. \
  454. status = kstrtoul(buf, 0, &val); \
  455. if (status) \
  456. return status; \
  457. \
  458. if (!valid_threshold(mcbsp, val)) \
  459. return -EDOM; \
  460. \
  461. mcbsp->prop = val; \
  462. return size; \
  463. } \
  464. \
  465. static DEVICE_ATTR_RW(prop)
  466. THRESHOLD_PROP_BUILDER(max_tx_thres);
  467. THRESHOLD_PROP_BUILDER(max_rx_thres);
  468. static const char * const dma_op_modes[] = {
  469. "element", "threshold",
  470. };
  471. static ssize_t dma_op_mode_show(struct device *dev,
  472. struct device_attribute *attr, char *buf)
  473. {
  474. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  475. int dma_op_mode, i = 0;
  476. ssize_t len = 0;
  477. const char * const *s;
  478. dma_op_mode = mcbsp->dma_op_mode;
  479. for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
  480. if (dma_op_mode == i)
  481. len += sysfs_emit_at(buf, len, "[%s] ", *s);
  482. else
  483. len += sysfs_emit_at(buf, len, "%s ", *s);
  484. }
  485. len += sysfs_emit_at(buf, len, "\n");
  486. return len;
  487. }
  488. static ssize_t dma_op_mode_store(struct device *dev,
  489. struct device_attribute *attr, const char *buf,
  490. size_t size)
  491. {
  492. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  493. int i;
  494. i = sysfs_match_string(dma_op_modes, buf);
  495. if (i < 0)
  496. return i;
  497. spin_lock_irq(&mcbsp->lock);
  498. if (!mcbsp->free) {
  499. size = -EBUSY;
  500. goto unlock;
  501. }
  502. mcbsp->dma_op_mode = i;
  503. unlock:
  504. spin_unlock_irq(&mcbsp->lock);
  505. return size;
  506. }
  507. static DEVICE_ATTR_RW(dma_op_mode);
  508. static const struct attribute *additional_attrs[] = {
  509. &dev_attr_max_tx_thres.attr,
  510. &dev_attr_max_rx_thres.attr,
  511. &dev_attr_dma_op_mode.attr,
  512. NULL,
  513. };
  514. static const struct attribute_group additional_attr_group = {
  515. .attrs = (struct attribute **)additional_attrs,
  516. };
  517. /*
  518. * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  519. * 730 has only 2 McBSP, and both of them are MPU peripherals.
  520. */
  521. static int omap_mcbsp_init(struct platform_device *pdev)
  522. {
  523. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  524. struct resource *res;
  525. int ret;
  526. spin_lock_init(&mcbsp->lock);
  527. mcbsp->free = true;
  528. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  529. if (!res)
  530. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  531. mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
  532. if (IS_ERR(mcbsp->io_base))
  533. return PTR_ERR(mcbsp->io_base);
  534. mcbsp->phys_base = res->start;
  535. mcbsp->reg_cache_size = resource_size(res);
  536. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  537. if (!res)
  538. mcbsp->phys_dma_base = mcbsp->phys_base;
  539. else
  540. mcbsp->phys_dma_base = res->start;
  541. /*
  542. * OMAP1, 2 uses two interrupt lines: TX, RX
  543. * OMAP2430, OMAP3 SoC have combined IRQ line as well.
  544. * OMAP4 and newer SoC only have the combined IRQ line.
  545. * Use the combined IRQ if available since it gives better debugging
  546. * possibilities.
  547. */
  548. mcbsp->irq = platform_get_irq_byname(pdev, "common");
  549. if (mcbsp->irq == -ENXIO) {
  550. mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
  551. if (mcbsp->tx_irq == -ENXIO) {
  552. mcbsp->irq = platform_get_irq(pdev, 0);
  553. mcbsp->tx_irq = 0;
  554. } else {
  555. mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
  556. mcbsp->irq = 0;
  557. }
  558. }
  559. if (!pdev->dev.of_node) {
  560. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  561. if (!res) {
  562. dev_err(&pdev->dev, "invalid tx DMA channel\n");
  563. return -ENODEV;
  564. }
  565. mcbsp->dma_req[0] = res->start;
  566. mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
  567. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  568. if (!res) {
  569. dev_err(&pdev->dev, "invalid rx DMA channel\n");
  570. return -ENODEV;
  571. }
  572. mcbsp->dma_req[1] = res->start;
  573. mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
  574. } else {
  575. mcbsp->dma_data[0].filter_data = "tx";
  576. mcbsp->dma_data[1].filter_data = "rx";
  577. }
  578. mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
  579. SNDRV_PCM_STREAM_PLAYBACK);
  580. mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
  581. SNDRV_PCM_STREAM_CAPTURE);
  582. mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
  583. if (IS_ERR(mcbsp->fclk)) {
  584. ret = PTR_ERR(mcbsp->fclk);
  585. dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
  586. return ret;
  587. }
  588. mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
  589. if (mcbsp->pdata->buffer_size) {
  590. /*
  591. * Initially configure the maximum thresholds to a safe value.
  592. * The McBSP FIFO usage with these values should not go under
  593. * 16 locations.
  594. * If the whole FIFO without safety buffer is used, than there
  595. * is a possibility that the DMA will be not able to push the
  596. * new data on time, causing channel shifts in runtime.
  597. */
  598. mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
  599. mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
  600. ret = devm_device_add_group(mcbsp->dev, &additional_attr_group);
  601. if (ret) {
  602. dev_err(mcbsp->dev,
  603. "Unable to create additional controls\n");
  604. return ret;
  605. }
  606. }
  607. return omap_mcbsp_st_init(pdev);
  608. }
  609. /*
  610. * Stream DMA parameters. DMA request line and port address are set runtime
  611. * since they are different between OMAP1 and later OMAPs
  612. */
  613. static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
  614. unsigned int packet_size)
  615. {
  616. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  617. struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
  618. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  619. int words;
  620. /* No need to proceed further if McBSP does not have FIFO */
  621. if (mcbsp->pdata->buffer_size == 0)
  622. return;
  623. /*
  624. * Configure McBSP threshold based on either:
  625. * packet_size, when the sDMA is in packet mode, or based on the
  626. * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  627. * for mono streams.
  628. */
  629. if (packet_size)
  630. words = packet_size;
  631. else
  632. words = 1;
  633. /* Configure McBSP internal buffer usage */
  634. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  635. omap_mcbsp_set_tx_threshold(mcbsp, words);
  636. else
  637. omap_mcbsp_set_rx_threshold(mcbsp, words);
  638. }
  639. static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  640. struct snd_pcm_hw_rule *rule)
  641. {
  642. struct snd_interval *buffer_size = hw_param_interval(params,
  643. SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
  644. struct snd_interval *channels = hw_param_interval(params,
  645. SNDRV_PCM_HW_PARAM_CHANNELS);
  646. struct omap_mcbsp *mcbsp = rule->private;
  647. struct snd_interval frames;
  648. int size;
  649. snd_interval_any(&frames);
  650. size = mcbsp->pdata->buffer_size;
  651. frames.min = size / channels->min;
  652. frames.integer = 1;
  653. return snd_interval_refine(buffer_size, &frames);
  654. }
  655. static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
  656. struct snd_soc_dai *cpu_dai)
  657. {
  658. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  659. int err = 0;
  660. if (!snd_soc_dai_active(cpu_dai))
  661. err = omap_mcbsp_request(mcbsp);
  662. /*
  663. * OMAP3 McBSP FIFO is word structured.
  664. * McBSP2 has 1024 + 256 = 1280 word long buffer,
  665. * McBSP1,3,4,5 has 128 word long buffer
  666. * This means that the size of the FIFO depends on the sample format.
  667. * For example on McBSP3:
  668. * 16bit samples: size is 128 * 2 = 256 bytes
  669. * 32bit samples: size is 128 * 4 = 512 bytes
  670. * It is simpler to place constraint for buffer and period based on
  671. * channels.
  672. * McBSP3 as example again (16 or 32 bit samples):
  673. * 1 channel (mono): size is 128 frames (128 words)
  674. * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
  675. * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
  676. */
  677. if (mcbsp->pdata->buffer_size) {
  678. /*
  679. * Rule for the buffer size. We should not allow
  680. * smaller buffer than the FIFO size to avoid underruns.
  681. * This applies only for the playback stream.
  682. */
  683. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  684. snd_pcm_hw_rule_add(substream->runtime, 0,
  685. SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
  686. omap_mcbsp_hwrule_min_buffersize,
  687. mcbsp,
  688. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  689. /* Make sure, that the period size is always even */
  690. snd_pcm_hw_constraint_step(substream->runtime, 0,
  691. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
  692. }
  693. return err;
  694. }
  695. static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
  696. struct snd_soc_dai *cpu_dai)
  697. {
  698. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  699. int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  700. int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
  701. int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
  702. if (mcbsp->latency[stream2])
  703. cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
  704. mcbsp->latency[stream2]);
  705. else if (mcbsp->latency[stream1])
  706. cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
  707. mcbsp->latency[stream1] = 0;
  708. if (!snd_soc_dai_active(cpu_dai)) {
  709. omap_mcbsp_free(mcbsp);
  710. mcbsp->configured = 0;
  711. }
  712. }
  713. static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
  714. struct snd_soc_dai *cpu_dai)
  715. {
  716. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  717. struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
  718. int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  719. int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
  720. int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
  721. int latency = mcbsp->latency[stream2];
  722. /* Prevent omap hardware from hitting off between FIFO fills */
  723. if (!latency || mcbsp->latency[stream1] < latency)
  724. latency = mcbsp->latency[stream1];
  725. if (cpu_latency_qos_request_active(pm_qos_req))
  726. cpu_latency_qos_update_request(pm_qos_req, latency);
  727. else if (latency)
  728. cpu_latency_qos_add_request(pm_qos_req, latency);
  729. return 0;
  730. }
  731. static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  732. struct snd_soc_dai *cpu_dai)
  733. {
  734. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  735. switch (cmd) {
  736. case SNDRV_PCM_TRIGGER_START:
  737. case SNDRV_PCM_TRIGGER_RESUME:
  738. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  739. mcbsp->active++;
  740. omap_mcbsp_start(mcbsp, substream->stream);
  741. break;
  742. case SNDRV_PCM_TRIGGER_STOP:
  743. case SNDRV_PCM_TRIGGER_SUSPEND:
  744. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  745. omap_mcbsp_stop(mcbsp, substream->stream);
  746. mcbsp->active--;
  747. break;
  748. default:
  749. return -EINVAL;
  750. }
  751. return 0;
  752. }
  753. static snd_pcm_sframes_t omap_mcbsp_dai_delay(
  754. struct snd_pcm_substream *substream,
  755. struct snd_soc_dai *dai)
  756. {
  757. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  758. struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
  759. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  760. u16 fifo_use;
  761. snd_pcm_sframes_t delay;
  762. /* No need to proceed further if McBSP does not have FIFO */
  763. if (mcbsp->pdata->buffer_size == 0)
  764. return 0;
  765. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  766. fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
  767. else
  768. fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
  769. /*
  770. * Divide the used locations with the channel count to get the
  771. * FIFO usage in samples (don't care about partial samples in the
  772. * buffer).
  773. */
  774. delay = fifo_use / substream->runtime->channels;
  775. return delay;
  776. }
  777. static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
  778. struct snd_pcm_hw_params *params,
  779. struct snd_soc_dai *cpu_dai)
  780. {
  781. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  782. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  783. struct snd_dmaengine_dai_dma_data *dma_data;
  784. int wlen, channels, wpf;
  785. int pkt_size = 0;
  786. unsigned int format, div, framesize, master;
  787. unsigned int buffer_size = mcbsp->pdata->buffer_size;
  788. dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
  789. channels = params_channels(params);
  790. switch (params_format(params)) {
  791. case SNDRV_PCM_FORMAT_S16_LE:
  792. wlen = 16;
  793. break;
  794. case SNDRV_PCM_FORMAT_S32_LE:
  795. wlen = 32;
  796. break;
  797. default:
  798. return -EINVAL;
  799. }
  800. if (buffer_size) {
  801. int latency;
  802. if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
  803. int period_words, max_thrsh;
  804. int divider = 0;
  805. period_words = params_period_bytes(params) / (wlen / 8);
  806. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  807. max_thrsh = mcbsp->max_tx_thres;
  808. else
  809. max_thrsh = mcbsp->max_rx_thres;
  810. /*
  811. * Use sDMA packet mode if McBSP is in threshold mode:
  812. * If period words less than the FIFO size the packet
  813. * size is set to the number of period words, otherwise
  814. * Look for the biggest threshold value which divides
  815. * the period size evenly.
  816. */
  817. divider = period_words / max_thrsh;
  818. if (period_words % max_thrsh)
  819. divider++;
  820. while (period_words % divider &&
  821. divider < period_words)
  822. divider++;
  823. if (divider == period_words)
  824. return -EINVAL;
  825. pkt_size = period_words / divider;
  826. } else if (channels > 1) {
  827. /* Use packet mode for non mono streams */
  828. pkt_size = channels;
  829. }
  830. latency = (buffer_size - pkt_size) / channels;
  831. latency = latency * USEC_PER_SEC /
  832. (params->rate_num / params->rate_den);
  833. mcbsp->latency[substream->stream] = latency;
  834. omap_mcbsp_set_threshold(substream, pkt_size);
  835. }
  836. dma_data->maxburst = pkt_size;
  837. if (mcbsp->configured) {
  838. /* McBSP already configured by another stream */
  839. return 0;
  840. }
  841. regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
  842. regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
  843. regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
  844. regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
  845. format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  846. wpf = channels;
  847. if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
  848. format == SND_SOC_DAIFMT_LEFT_J)) {
  849. /* Use dual-phase frames */
  850. regs->rcr2 |= RPHASE;
  851. regs->xcr2 |= XPHASE;
  852. /* Set 1 word per (McBSP) frame for phase1 and phase2 */
  853. wpf--;
  854. regs->rcr2 |= RFRLEN2(wpf - 1);
  855. regs->xcr2 |= XFRLEN2(wpf - 1);
  856. }
  857. regs->rcr1 |= RFRLEN1(wpf - 1);
  858. regs->xcr1 |= XFRLEN1(wpf - 1);
  859. switch (params_format(params)) {
  860. case SNDRV_PCM_FORMAT_S16_LE:
  861. /* Set word lengths */
  862. regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
  863. regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
  864. regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
  865. regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
  866. break;
  867. case SNDRV_PCM_FORMAT_S32_LE:
  868. /* Set word lengths */
  869. regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
  870. regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
  871. regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
  872. regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
  873. break;
  874. default:
  875. /* Unsupported PCM format */
  876. return -EINVAL;
  877. }
  878. /* In McBSP master modes, FRAME (i.e. sample rate) is generated
  879. * by _counting_ BCLKs. Calculate frame size in BCLKs */
  880. master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
  881. if (master == SND_SOC_DAIFMT_BP_FP) {
  882. div = mcbsp->clk_div ? mcbsp->clk_div : 1;
  883. framesize = (mcbsp->in_freq / div) / params_rate(params);
  884. if (framesize < wlen * channels) {
  885. printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
  886. "channels\n", __func__);
  887. return -EINVAL;
  888. }
  889. } else
  890. framesize = wlen * channels;
  891. /* Set FS period and length in terms of bit clock periods */
  892. regs->srgr2 &= ~FPER(0xfff);
  893. regs->srgr1 &= ~FWID(0xff);
  894. switch (format) {
  895. case SND_SOC_DAIFMT_I2S:
  896. case SND_SOC_DAIFMT_LEFT_J:
  897. regs->srgr2 |= FPER(framesize - 1);
  898. regs->srgr1 |= FWID((framesize >> 1) - 1);
  899. break;
  900. case SND_SOC_DAIFMT_DSP_A:
  901. case SND_SOC_DAIFMT_DSP_B:
  902. regs->srgr2 |= FPER(framesize - 1);
  903. regs->srgr1 |= FWID(0);
  904. break;
  905. }
  906. omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
  907. mcbsp->wlen = wlen;
  908. mcbsp->configured = 1;
  909. return 0;
  910. }
  911. /*
  912. * This must be called before _set_clkdiv and _set_sysclk since McBSP register
  913. * cache is initialized here
  914. */
  915. static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  916. unsigned int fmt)
  917. {
  918. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  919. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  920. bool inv_fs = false;
  921. if (mcbsp->configured)
  922. return 0;
  923. mcbsp->fmt = fmt;
  924. memset(regs, 0, sizeof(*regs));
  925. /* Generic McBSP register settings */
  926. regs->spcr2 |= XINTM(3) | FREE;
  927. regs->spcr1 |= RINTM(3);
  928. /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
  929. if (!mcbsp->pdata->has_ccr) {
  930. regs->rcr2 |= RFIG;
  931. regs->xcr2 |= XFIG;
  932. }
  933. /* Configure XCCR/RCCR only for revisions which have ccr registers */
  934. if (mcbsp->pdata->has_ccr) {
  935. regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
  936. regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
  937. }
  938. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  939. case SND_SOC_DAIFMT_I2S:
  940. /* 1-bit data delay */
  941. regs->rcr2 |= RDATDLY(1);
  942. regs->xcr2 |= XDATDLY(1);
  943. break;
  944. case SND_SOC_DAIFMT_LEFT_J:
  945. /* 0-bit data delay */
  946. regs->rcr2 |= RDATDLY(0);
  947. regs->xcr2 |= XDATDLY(0);
  948. regs->spcr1 |= RJUST(2);
  949. /* Invert FS polarity configuration */
  950. inv_fs = true;
  951. break;
  952. case SND_SOC_DAIFMT_DSP_A:
  953. /* 1-bit data delay */
  954. regs->rcr2 |= RDATDLY(1);
  955. regs->xcr2 |= XDATDLY(1);
  956. /* Invert FS polarity configuration */
  957. inv_fs = true;
  958. break;
  959. case SND_SOC_DAIFMT_DSP_B:
  960. /* 0-bit data delay */
  961. regs->rcr2 |= RDATDLY(0);
  962. regs->xcr2 |= XDATDLY(0);
  963. /* Invert FS polarity configuration */
  964. inv_fs = true;
  965. break;
  966. default:
  967. /* Unsupported data format */
  968. return -EINVAL;
  969. }
  970. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  971. case SND_SOC_DAIFMT_BP_FP:
  972. /* McBSP master. Set FS and bit clocks as outputs */
  973. regs->pcr0 |= FSXM | FSRM |
  974. CLKXM | CLKRM;
  975. /* Sample rate generator drives the FS */
  976. regs->srgr2 |= FSGM;
  977. break;
  978. case SND_SOC_DAIFMT_BC_FP:
  979. /* McBSP slave. FS clock as output */
  980. regs->srgr2 |= FSGM;
  981. regs->pcr0 |= FSXM | FSRM;
  982. break;
  983. case SND_SOC_DAIFMT_BC_FC:
  984. /* McBSP slave */
  985. break;
  986. default:
  987. /* Unsupported master/slave configuration */
  988. return -EINVAL;
  989. }
  990. /* Set bit clock (CLKX/CLKR) and FS polarities */
  991. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  992. case SND_SOC_DAIFMT_NB_NF:
  993. /*
  994. * Normal BCLK + FS.
  995. * FS active low. TX data driven on falling edge of bit clock
  996. * and RX data sampled on rising edge of bit clock.
  997. */
  998. regs->pcr0 |= FSXP | FSRP |
  999. CLKXP | CLKRP;
  1000. break;
  1001. case SND_SOC_DAIFMT_NB_IF:
  1002. regs->pcr0 |= CLKXP | CLKRP;
  1003. break;
  1004. case SND_SOC_DAIFMT_IB_NF:
  1005. regs->pcr0 |= FSXP | FSRP;
  1006. break;
  1007. case SND_SOC_DAIFMT_IB_IF:
  1008. break;
  1009. default:
  1010. return -EINVAL;
  1011. }
  1012. if (inv_fs)
  1013. regs->pcr0 ^= FSXP | FSRP;
  1014. return 0;
  1015. }
  1016. static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
  1017. int div_id, int div)
  1018. {
  1019. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  1020. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  1021. if (div_id != OMAP_MCBSP_CLKGDV)
  1022. return -ENODEV;
  1023. mcbsp->clk_div = div;
  1024. regs->srgr1 &= ~CLKGDV(0xff);
  1025. regs->srgr1 |= CLKGDV(div - 1);
  1026. return 0;
  1027. }
  1028. static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  1029. int clk_id, unsigned int freq,
  1030. int dir)
  1031. {
  1032. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  1033. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  1034. int err = 0;
  1035. if (mcbsp->active) {
  1036. if (freq == mcbsp->in_freq)
  1037. return 0;
  1038. else
  1039. return -EBUSY;
  1040. }
  1041. mcbsp->in_freq = freq;
  1042. regs->srgr2 &= ~CLKSM;
  1043. regs->pcr0 &= ~SCLKME;
  1044. switch (clk_id) {
  1045. case OMAP_MCBSP_SYSCLK_CLK:
  1046. regs->srgr2 |= CLKSM;
  1047. break;
  1048. case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
  1049. if (mcbsp_omap1()) {
  1050. err = -EINVAL;
  1051. break;
  1052. }
  1053. err = omap2_mcbsp_set_clks_src(mcbsp,
  1054. MCBSP_CLKS_PRCM_SRC);
  1055. break;
  1056. case OMAP_MCBSP_SYSCLK_CLKS_EXT:
  1057. if (mcbsp_omap1()) {
  1058. err = 0;
  1059. break;
  1060. }
  1061. err = omap2_mcbsp_set_clks_src(mcbsp,
  1062. MCBSP_CLKS_PAD_SRC);
  1063. break;
  1064. case OMAP_MCBSP_SYSCLK_CLKX_EXT:
  1065. regs->srgr2 |= CLKSM;
  1066. regs->pcr0 |= SCLKME;
  1067. /*
  1068. * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
  1069. * disable output on those pins. This enables to inject the
  1070. * reference clock through CLKX/CLKR. For this to work
  1071. * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
  1072. */
  1073. regs->pcr0 &= ~CLKXM;
  1074. break;
  1075. case OMAP_MCBSP_SYSCLK_CLKR_EXT:
  1076. regs->pcr0 |= SCLKME;
  1077. /* Disable ouput on CLKR pin in master mode */
  1078. regs->pcr0 &= ~CLKRM;
  1079. break;
  1080. default:
  1081. err = -ENODEV;
  1082. }
  1083. return err;
  1084. }
  1085. static const struct snd_soc_dai_ops mcbsp_dai_ops = {
  1086. .startup = omap_mcbsp_dai_startup,
  1087. .shutdown = omap_mcbsp_dai_shutdown,
  1088. .prepare = omap_mcbsp_dai_prepare,
  1089. .trigger = omap_mcbsp_dai_trigger,
  1090. .delay = omap_mcbsp_dai_delay,
  1091. .hw_params = omap_mcbsp_dai_hw_params,
  1092. .set_fmt = omap_mcbsp_dai_set_dai_fmt,
  1093. .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
  1094. .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
  1095. };
  1096. static int omap_mcbsp_probe(struct snd_soc_dai *dai)
  1097. {
  1098. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
  1099. pm_runtime_enable(mcbsp->dev);
  1100. snd_soc_dai_init_dma_data(dai,
  1101. &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
  1102. &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
  1103. return 0;
  1104. }
  1105. static int omap_mcbsp_remove(struct snd_soc_dai *dai)
  1106. {
  1107. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
  1108. pm_runtime_disable(mcbsp->dev);
  1109. return 0;
  1110. }
  1111. static struct snd_soc_dai_driver omap_mcbsp_dai = {
  1112. .probe = omap_mcbsp_probe,
  1113. .remove = omap_mcbsp_remove,
  1114. .playback = {
  1115. .channels_min = 1,
  1116. .channels_max = 16,
  1117. .rates = OMAP_MCBSP_RATES,
  1118. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
  1119. },
  1120. .capture = {
  1121. .channels_min = 1,
  1122. .channels_max = 16,
  1123. .rates = OMAP_MCBSP_RATES,
  1124. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
  1125. },
  1126. .ops = &mcbsp_dai_ops,
  1127. };
  1128. static const struct snd_soc_component_driver omap_mcbsp_component = {
  1129. .name = "omap-mcbsp",
  1130. .legacy_dai_naming = 1,
  1131. };
  1132. static struct omap_mcbsp_platform_data omap2420_pdata = {
  1133. .reg_step = 4,
  1134. .reg_size = 2,
  1135. };
  1136. static struct omap_mcbsp_platform_data omap2430_pdata = {
  1137. .reg_step = 4,
  1138. .reg_size = 4,
  1139. .has_ccr = true,
  1140. };
  1141. static struct omap_mcbsp_platform_data omap3_pdata = {
  1142. .reg_step = 4,
  1143. .reg_size = 4,
  1144. .has_ccr = true,
  1145. .has_wakeup = true,
  1146. };
  1147. static struct omap_mcbsp_platform_data omap4_pdata = {
  1148. .reg_step = 4,
  1149. .reg_size = 4,
  1150. .has_ccr = true,
  1151. .has_wakeup = true,
  1152. };
  1153. static const struct of_device_id omap_mcbsp_of_match[] = {
  1154. {
  1155. .compatible = "ti,omap2420-mcbsp",
  1156. .data = &omap2420_pdata,
  1157. },
  1158. {
  1159. .compatible = "ti,omap2430-mcbsp",
  1160. .data = &omap2430_pdata,
  1161. },
  1162. {
  1163. .compatible = "ti,omap3-mcbsp",
  1164. .data = &omap3_pdata,
  1165. },
  1166. {
  1167. .compatible = "ti,omap4-mcbsp",
  1168. .data = &omap4_pdata,
  1169. },
  1170. { },
  1171. };
  1172. MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
  1173. static int asoc_mcbsp_probe(struct platform_device *pdev)
  1174. {
  1175. struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1176. struct omap_mcbsp *mcbsp;
  1177. const struct of_device_id *match;
  1178. int ret;
  1179. match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
  1180. if (match) {
  1181. struct device_node *node = pdev->dev.of_node;
  1182. struct omap_mcbsp_platform_data *pdata_quirk = pdata;
  1183. int buffer_size;
  1184. pdata = devm_kzalloc(&pdev->dev,
  1185. sizeof(struct omap_mcbsp_platform_data),
  1186. GFP_KERNEL);
  1187. if (!pdata)
  1188. return -ENOMEM;
  1189. memcpy(pdata, match->data, sizeof(*pdata));
  1190. if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
  1191. pdata->buffer_size = buffer_size;
  1192. if (pdata_quirk)
  1193. pdata->force_ick_on = pdata_quirk->force_ick_on;
  1194. } else if (!pdata) {
  1195. dev_err(&pdev->dev, "missing platform data.\n");
  1196. return -EINVAL;
  1197. }
  1198. mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
  1199. if (!mcbsp)
  1200. return -ENOMEM;
  1201. mcbsp->id = pdev->id;
  1202. mcbsp->pdata = pdata;
  1203. mcbsp->dev = &pdev->dev;
  1204. platform_set_drvdata(pdev, mcbsp);
  1205. ret = omap_mcbsp_init(pdev);
  1206. if (ret)
  1207. return ret;
  1208. if (mcbsp->pdata->reg_size == 2) {
  1209. omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
  1210. omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
  1211. }
  1212. ret = devm_snd_soc_register_component(&pdev->dev,
  1213. &omap_mcbsp_component,
  1214. &omap_mcbsp_dai, 1);
  1215. if (ret)
  1216. return ret;
  1217. return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
  1218. }
  1219. static int asoc_mcbsp_remove(struct platform_device *pdev)
  1220. {
  1221. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  1222. if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  1223. mcbsp->pdata->ops->free(mcbsp->id);
  1224. if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
  1225. cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
  1226. return 0;
  1227. }
  1228. static struct platform_driver asoc_mcbsp_driver = {
  1229. .driver = {
  1230. .name = "omap-mcbsp",
  1231. .of_match_table = omap_mcbsp_of_match,
  1232. },
  1233. .probe = asoc_mcbsp_probe,
  1234. .remove = asoc_mcbsp_remove,
  1235. };
  1236. module_platform_driver(asoc_mcbsp_driver);
  1237. MODULE_AUTHOR("Jarkko Nikula <[email protected]>");
  1238. MODULE_DESCRIPTION("OMAP I2S SoC Interface");
  1239. MODULE_LICENSE("GPL");
  1240. MODULE_ALIAS("platform:omap-mcbsp");