tegra210_sfc.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * tegra210_sfc.h - Definitions for Tegra210 SFC driver
  4. *
  5. * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
  6. *
  7. */
  8. #ifndef __TEGRA210_SFC_H__
  9. #define __TEGRA210_SFC_H__
  10. /*
  11. * SFC_RX registers are with respect to XBAR.
  12. * The data comes from XBAR to SFC.
  13. */
  14. #define TEGRA210_SFC_RX_STATUS 0x0c
  15. #define TEGRA210_SFC_RX_INT_STATUS 0x10
  16. #define TEGRA210_SFC_RX_INT_MASK 0x14
  17. #define TEGRA210_SFC_RX_INT_SET 0x18
  18. #define TEGRA210_SFC_RX_INT_CLEAR 0x1c
  19. #define TEGRA210_SFC_RX_CIF_CTRL 0x20
  20. #define TEGRA210_SFC_RX_FREQ 0x24
  21. /*
  22. * SFC_TX registers are with respect to XBAR.
  23. * The data goes out of SFC.
  24. */
  25. #define TEGRA210_SFC_TX_STATUS 0x4c
  26. #define TEGRA210_SFC_TX_INT_STATUS 0x50
  27. #define TEGRA210_SFC_TX_INT_MASK 0x54
  28. #define TEGRA210_SFC_TX_INT_SET 0x58
  29. #define TEGRA210_SFC_TX_INT_CLEAR 0x5c
  30. #define TEGRA210_SFC_TX_CIF_CTRL 0x60
  31. #define TEGRA210_SFC_TX_FREQ 0x64
  32. /* Register offsets from TEGRA210_SFC*_BASE */
  33. #define TEGRA210_SFC_ENABLE 0x80
  34. #define TEGRA210_SFC_SOFT_RESET 0x84
  35. #define TEGRA210_SFC_CG 0x88
  36. #define TEGRA210_SFC_STATUS 0x8c
  37. #define TEGRA210_SFC_INT_STATUS 0x90
  38. #define TEGRA210_SFC_COEF_RAM 0xbc
  39. #define TEGRA210_SFC_CFG_RAM_CTRL 0xc0
  40. #define TEGRA210_SFC_CFG_RAM_DATA 0xc4
  41. /* Fields in TEGRA210_SFC_ENABLE */
  42. #define TEGRA210_SFC_EN_SHIFT 0
  43. #define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
  44. #define TEGRA210_SFC_NUM_RATES 13
  45. /* Fields in TEGRA210_SFC_COEF_RAM */
  46. #define TEGRA210_SFC_COEF_RAM_EN BIT(0)
  47. #define TEGRA210_SFC_SOFT_RESET_EN BIT(0)
  48. /* Coefficients */
  49. #define TEGRA210_SFC_COEF_RAM_DEPTH 64
  50. #define TEGRA210_SFC_RAM_CTRL_RW_WRITE (1 << 14)
  51. #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN (1 << 13)
  52. #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12)
  53. enum tegra210_sfc_path {
  54. SFC_RX_PATH,
  55. SFC_TX_PATH,
  56. SFC_PATHS,
  57. };
  58. struct tegra210_sfc {
  59. unsigned int mono_to_stereo[SFC_PATHS];
  60. unsigned int stereo_to_mono[SFC_PATHS];
  61. unsigned int srate_out;
  62. unsigned int srate_in;
  63. struct regmap *regmap;
  64. };
  65. #endif