tegra210_ope.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // tegra210_ope.c - Tegra210 OPE driver
  4. //
  5. // Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
  6. #include <linux/clk.h>
  7. #include <linux/device.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/regmap.h>
  15. #include <sound/core.h>
  16. #include <sound/pcm.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/soc.h>
  19. #include "tegra210_mbdrc.h"
  20. #include "tegra210_ope.h"
  21. #include "tegra210_peq.h"
  22. #include "tegra_cif.h"
  23. static const struct reg_default tegra210_ope_reg_defaults[] = {
  24. { TEGRA210_OPE_RX_INT_MASK, 0x00000001},
  25. { TEGRA210_OPE_RX_CIF_CTRL, 0x00007700},
  26. { TEGRA210_OPE_TX_INT_MASK, 0x00000001},
  27. { TEGRA210_OPE_TX_CIF_CTRL, 0x00007700},
  28. { TEGRA210_OPE_CG, 0x1},
  29. };
  30. static int tegra210_ope_set_audio_cif(struct tegra210_ope *ope,
  31. struct snd_pcm_hw_params *params,
  32. unsigned int reg)
  33. {
  34. int channels, audio_bits;
  35. struct tegra_cif_conf cif_conf;
  36. memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
  37. channels = params_channels(params);
  38. if (channels < 2)
  39. return -EINVAL;
  40. switch (params_format(params)) {
  41. case SNDRV_PCM_FORMAT_S16_LE:
  42. audio_bits = TEGRA_ACIF_BITS_16;
  43. break;
  44. case SNDRV_PCM_FORMAT_S32_LE:
  45. audio_bits = TEGRA_ACIF_BITS_32;
  46. break;
  47. default:
  48. return -EINVAL;
  49. }
  50. cif_conf.audio_ch = channels;
  51. cif_conf.client_ch = channels;
  52. cif_conf.audio_bits = audio_bits;
  53. cif_conf.client_bits = audio_bits;
  54. tegra_set_cif(ope->regmap, reg, &cif_conf);
  55. return 0;
  56. }
  57. static int tegra210_ope_hw_params(struct snd_pcm_substream *substream,
  58. struct snd_pcm_hw_params *params,
  59. struct snd_soc_dai *dai)
  60. {
  61. struct device *dev = dai->dev;
  62. struct tegra210_ope *ope = snd_soc_dai_get_drvdata(dai);
  63. int err;
  64. /* Set RX and TX CIF */
  65. err = tegra210_ope_set_audio_cif(ope, params,
  66. TEGRA210_OPE_RX_CIF_CTRL);
  67. if (err) {
  68. dev_err(dev, "Can't set OPE RX CIF: %d\n", err);
  69. return err;
  70. }
  71. err = tegra210_ope_set_audio_cif(ope, params,
  72. TEGRA210_OPE_TX_CIF_CTRL);
  73. if (err) {
  74. dev_err(dev, "Can't set OPE TX CIF: %d\n", err);
  75. return err;
  76. }
  77. tegra210_mbdrc_hw_params(dai->component);
  78. return err;
  79. }
  80. static int tegra210_ope_component_probe(struct snd_soc_component *cmpnt)
  81. {
  82. struct tegra210_ope *ope = dev_get_drvdata(cmpnt->dev);
  83. tegra210_peq_component_init(cmpnt);
  84. tegra210_mbdrc_component_init(cmpnt);
  85. /*
  86. * The OPE, PEQ and MBDRC functionalities are combined under one
  87. * device registered by OPE driver. In fact OPE HW block includes
  88. * sub blocks PEQ and MBDRC. However driver registers separate
  89. * regmap interfaces for each of these. ASoC core depends on
  90. * dev_get_regmap() to populate the regmap field for a given ASoC
  91. * component. A component can have one regmap reference and since
  92. * the DAPM routes depend on OPE regmap only, below explicit
  93. * assignment is done to highlight this. This is needed for ASoC
  94. * core to access correct regmap during DAPM path setup.
  95. */
  96. snd_soc_component_init_regmap(cmpnt, ope->regmap);
  97. return 0;
  98. }
  99. static const struct snd_soc_dai_ops tegra210_ope_dai_ops = {
  100. .hw_params = tegra210_ope_hw_params,
  101. };
  102. static struct snd_soc_dai_driver tegra210_ope_dais[] = {
  103. {
  104. .name = "OPE-RX-CIF",
  105. .playback = {
  106. .stream_name = "RX-CIF-Playback",
  107. .channels_min = 1,
  108. .channels_max = 8,
  109. .rates = SNDRV_PCM_RATE_8000_192000,
  110. .formats = SNDRV_PCM_FMTBIT_S8 |
  111. SNDRV_PCM_FMTBIT_S16_LE |
  112. SNDRV_PCM_FMTBIT_S32_LE,
  113. },
  114. .capture = {
  115. .stream_name = "RX-CIF-Capture",
  116. .channels_min = 1,
  117. .channels_max = 8,
  118. .rates = SNDRV_PCM_RATE_8000_192000,
  119. .formats = SNDRV_PCM_FMTBIT_S8 |
  120. SNDRV_PCM_FMTBIT_S16_LE |
  121. SNDRV_PCM_FMTBIT_S32_LE,
  122. },
  123. },
  124. {
  125. .name = "OPE-TX-CIF",
  126. .playback = {
  127. .stream_name = "TX-CIF-Playback",
  128. .channels_min = 1,
  129. .channels_max = 8,
  130. .rates = SNDRV_PCM_RATE_8000_192000,
  131. .formats = SNDRV_PCM_FMTBIT_S8 |
  132. SNDRV_PCM_FMTBIT_S16_LE |
  133. SNDRV_PCM_FMTBIT_S32_LE,
  134. },
  135. .capture = {
  136. .stream_name = "TX-CIF-Capture",
  137. .channels_min = 1,
  138. .channels_max = 8,
  139. .rates = SNDRV_PCM_RATE_8000_192000,
  140. .formats = SNDRV_PCM_FMTBIT_S8 |
  141. SNDRV_PCM_FMTBIT_S16_LE |
  142. SNDRV_PCM_FMTBIT_S32_LE,
  143. },
  144. .ops = &tegra210_ope_dai_ops,
  145. }
  146. };
  147. static const struct snd_soc_dapm_widget tegra210_ope_widgets[] = {
  148. SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
  149. SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_OPE_ENABLE,
  150. TEGRA210_OPE_EN_SHIFT, 0),
  151. };
  152. #define OPE_ROUTES(sname) \
  153. { "RX XBAR-" sname, NULL, "XBAR-TX" }, \
  154. { "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \
  155. { "RX", NULL, "RX-CIF-" sname }, \
  156. { "TX-CIF-" sname, NULL, "TX" }, \
  157. { "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \
  158. { "XBAR-RX", NULL, "TX XBAR-" sname }
  159. static const struct snd_soc_dapm_route tegra210_ope_routes[] = {
  160. { "TX", NULL, "RX" },
  161. OPE_ROUTES("Playback"),
  162. OPE_ROUTES("Capture"),
  163. };
  164. static const char * const tegra210_ope_data_dir_text[] = {
  165. "MBDRC to PEQ",
  166. "PEQ to MBDRC"
  167. };
  168. static const struct soc_enum tegra210_ope_data_dir_enum =
  169. SOC_ENUM_SINGLE(TEGRA210_OPE_DIR, TEGRA210_OPE_DIR_SHIFT,
  170. 2, tegra210_ope_data_dir_text);
  171. static int tegra210_ope_get_data_dir(struct snd_kcontrol *kcontrol,
  172. struct snd_ctl_elem_value *ucontrol)
  173. {
  174. struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
  175. struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
  176. ucontrol->value.enumerated.item[0] = ope->data_dir;
  177. return 0;
  178. }
  179. static int tegra210_ope_put_data_dir(struct snd_kcontrol *kcontrol,
  180. struct snd_ctl_elem_value *ucontrol)
  181. {
  182. struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
  183. struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
  184. unsigned int value = ucontrol->value.enumerated.item[0];
  185. if (value == ope->data_dir)
  186. return 0;
  187. ope->data_dir = value;
  188. return 1;
  189. }
  190. static const struct snd_kcontrol_new tegra210_ope_controls[] = {
  191. SOC_ENUM_EXT("Data Flow Direction", tegra210_ope_data_dir_enum,
  192. tegra210_ope_get_data_dir, tegra210_ope_put_data_dir),
  193. };
  194. static const struct snd_soc_component_driver tegra210_ope_cmpnt = {
  195. .probe = tegra210_ope_component_probe,
  196. .dapm_widgets = tegra210_ope_widgets,
  197. .num_dapm_widgets = ARRAY_SIZE(tegra210_ope_widgets),
  198. .dapm_routes = tegra210_ope_routes,
  199. .num_dapm_routes = ARRAY_SIZE(tegra210_ope_routes),
  200. .controls = tegra210_ope_controls,
  201. .num_controls = ARRAY_SIZE(tegra210_ope_controls),
  202. };
  203. static bool tegra210_ope_wr_reg(struct device *dev, unsigned int reg)
  204. {
  205. switch (reg) {
  206. case TEGRA210_OPE_RX_INT_MASK ... TEGRA210_OPE_RX_CIF_CTRL:
  207. case TEGRA210_OPE_TX_INT_MASK ... TEGRA210_OPE_TX_CIF_CTRL:
  208. case TEGRA210_OPE_ENABLE ... TEGRA210_OPE_CG:
  209. case TEGRA210_OPE_DIR:
  210. return true;
  211. default:
  212. return false;
  213. }
  214. }
  215. static bool tegra210_ope_rd_reg(struct device *dev, unsigned int reg)
  216. {
  217. if (tegra210_ope_wr_reg(dev, reg))
  218. return true;
  219. switch (reg) {
  220. case TEGRA210_OPE_RX_STATUS:
  221. case TEGRA210_OPE_RX_INT_STATUS:
  222. case TEGRA210_OPE_TX_STATUS:
  223. case TEGRA210_OPE_TX_INT_STATUS:
  224. case TEGRA210_OPE_STATUS:
  225. case TEGRA210_OPE_INT_STATUS:
  226. return true;
  227. default:
  228. return false;
  229. }
  230. }
  231. static bool tegra210_ope_volatile_reg(struct device *dev, unsigned int reg)
  232. {
  233. switch (reg) {
  234. case TEGRA210_OPE_RX_STATUS:
  235. case TEGRA210_OPE_RX_INT_STATUS:
  236. case TEGRA210_OPE_TX_STATUS:
  237. case TEGRA210_OPE_TX_INT_STATUS:
  238. case TEGRA210_OPE_SOFT_RESET:
  239. case TEGRA210_OPE_STATUS:
  240. case TEGRA210_OPE_INT_STATUS:
  241. return true;
  242. default:
  243. return false;
  244. }
  245. }
  246. static const struct regmap_config tegra210_ope_regmap_config = {
  247. .reg_bits = 32,
  248. .reg_stride = 4,
  249. .val_bits = 32,
  250. .max_register = TEGRA210_OPE_DIR,
  251. .writeable_reg = tegra210_ope_wr_reg,
  252. .readable_reg = tegra210_ope_rd_reg,
  253. .volatile_reg = tegra210_ope_volatile_reg,
  254. .reg_defaults = tegra210_ope_reg_defaults,
  255. .num_reg_defaults = ARRAY_SIZE(tegra210_ope_reg_defaults),
  256. .cache_type = REGCACHE_FLAT,
  257. };
  258. static int tegra210_ope_probe(struct platform_device *pdev)
  259. {
  260. struct device *dev = &pdev->dev;
  261. struct tegra210_ope *ope;
  262. void __iomem *regs;
  263. int err;
  264. ope = devm_kzalloc(dev, sizeof(*ope), GFP_KERNEL);
  265. if (!ope)
  266. return -ENOMEM;
  267. regs = devm_platform_ioremap_resource(pdev, 0);
  268. if (IS_ERR(regs))
  269. return PTR_ERR(regs);
  270. ope->regmap = devm_regmap_init_mmio(dev, regs,
  271. &tegra210_ope_regmap_config);
  272. if (IS_ERR(ope->regmap)) {
  273. dev_err(dev, "regmap init failed\n");
  274. return PTR_ERR(ope->regmap);
  275. }
  276. regcache_cache_only(ope->regmap, true);
  277. dev_set_drvdata(dev, ope);
  278. err = tegra210_peq_regmap_init(pdev);
  279. if (err < 0) {
  280. dev_err(dev, "PEQ init failed\n");
  281. return err;
  282. }
  283. err = tegra210_mbdrc_regmap_init(pdev);
  284. if (err < 0) {
  285. dev_err(dev, "MBDRC init failed\n");
  286. return err;
  287. }
  288. err = devm_snd_soc_register_component(dev, &tegra210_ope_cmpnt,
  289. tegra210_ope_dais,
  290. ARRAY_SIZE(tegra210_ope_dais));
  291. if (err) {
  292. dev_err(dev, "can't register OPE component, err: %d\n", err);
  293. return err;
  294. }
  295. pm_runtime_enable(dev);
  296. return 0;
  297. }
  298. static int tegra210_ope_remove(struct platform_device *pdev)
  299. {
  300. pm_runtime_disable(&pdev->dev);
  301. return 0;
  302. }
  303. static int __maybe_unused tegra210_ope_runtime_suspend(struct device *dev)
  304. {
  305. struct tegra210_ope *ope = dev_get_drvdata(dev);
  306. tegra210_peq_save(ope->peq_regmap, ope->peq_biquad_gains,
  307. ope->peq_biquad_shifts);
  308. regcache_cache_only(ope->mbdrc_regmap, true);
  309. regcache_cache_only(ope->peq_regmap, true);
  310. regcache_cache_only(ope->regmap, true);
  311. regcache_mark_dirty(ope->regmap);
  312. regcache_mark_dirty(ope->peq_regmap);
  313. regcache_mark_dirty(ope->mbdrc_regmap);
  314. return 0;
  315. }
  316. static int __maybe_unused tegra210_ope_runtime_resume(struct device *dev)
  317. {
  318. struct tegra210_ope *ope = dev_get_drvdata(dev);
  319. regcache_cache_only(ope->regmap, false);
  320. regcache_cache_only(ope->peq_regmap, false);
  321. regcache_cache_only(ope->mbdrc_regmap, false);
  322. regcache_sync(ope->regmap);
  323. regcache_sync(ope->peq_regmap);
  324. regcache_sync(ope->mbdrc_regmap);
  325. tegra210_peq_restore(ope->peq_regmap, ope->peq_biquad_gains,
  326. ope->peq_biquad_shifts);
  327. return 0;
  328. }
  329. static const struct dev_pm_ops tegra210_ope_pm_ops = {
  330. SET_RUNTIME_PM_OPS(tegra210_ope_runtime_suspend,
  331. tegra210_ope_runtime_resume, NULL)
  332. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  333. pm_runtime_force_resume)
  334. };
  335. static const struct of_device_id tegra210_ope_of_match[] = {
  336. { .compatible = "nvidia,tegra210-ope" },
  337. {},
  338. };
  339. MODULE_DEVICE_TABLE(of, tegra210_ope_of_match);
  340. static struct platform_driver tegra210_ope_driver = {
  341. .driver = {
  342. .name = "tegra210-ope",
  343. .of_match_table = tegra210_ope_of_match,
  344. .pm = &tegra210_ope_pm_ops,
  345. },
  346. .probe = tegra210_ope_probe,
  347. .remove = tegra210_ope_remove,
  348. };
  349. module_platform_driver(tegra210_ope_driver)
  350. MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
  351. MODULE_DESCRIPTION("Tegra210 OPE ASoC driver");
  352. MODULE_LICENSE("GPL");