tegra210_ahub.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * tegra210_ahub.h - TEGRA210 AHUB
  4. *
  5. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. */
  8. #ifndef __TEGRA210_AHUB__H__
  9. #define __TEGRA210_AHUB__H__
  10. /* Tegra210 specific */
  11. #define TEGRA210_XBAR_PART1_RX 0x200
  12. #define TEGRA210_XBAR_PART2_RX 0x400
  13. #define TEGRA210_XBAR_RX_STRIDE 0x4
  14. #define TEGRA210_XBAR_AUDIO_RX_COUNT 90
  15. #define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff
  16. #define TEGRA210_XBAR_REG_MASK_1 0x3f30031f
  17. #define TEGRA210_XBAR_REG_MASK_2 0xff1cf313
  18. #define TEGRA210_XBAR_REG_MASK_3 0x0
  19. #define TEGRA210_XBAR_UPDATE_MAX_REG 3
  20. /* Tegra186 specific */
  21. #define TEGRA186_XBAR_PART3_RX 0x600
  22. #define TEGRA186_XBAR_AUDIO_RX_COUNT 115
  23. #define TEGRA186_XBAR_REG_MASK_0 0xf3fffff
  24. #define TEGRA186_XBAR_REG_MASK_1 0x3f310f1f
  25. #define TEGRA186_XBAR_REG_MASK_2 0xff3cf311
  26. #define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff
  27. #define TEGRA186_XBAR_UPDATE_MAX_REG 4
  28. #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
  29. #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \
  30. (TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
  31. #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
  32. (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
  33. #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
  34. #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
  35. #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
  36. { \
  37. .reg = xreg, \
  38. .shift_l = shift, \
  39. .shift_r = shift, \
  40. .items = xmax, \
  41. .texts = xtexts, \
  42. .values = xvalues, \
  43. .mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0 \
  44. }
  45. #define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues) \
  46. static struct soc_enum name = \
  47. SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts), \
  48. xtexts, xvalues)
  49. #define MUX_ENUM_CTRL_DECL(ename, id) \
  50. SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
  51. tegra210_ahub_mux_texts, \
  52. tegra210_ahub_mux_values); \
  53. static const struct snd_kcontrol_new ename##_control = \
  54. SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
  55. tegra_ahub_get_value_enum, \
  56. tegra_ahub_put_value_enum)
  57. #define MUX_ENUM_CTRL_DECL_186(ename, id) \
  58. SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
  59. tegra186_ahub_mux_texts, \
  60. tegra186_ahub_mux_values); \
  61. static const struct snd_kcontrol_new ename##_control = \
  62. SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
  63. tegra_ahub_get_value_enum, \
  64. tegra_ahub_put_value_enum)
  65. #define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id)
  66. #define WIDGETS(sname, ename) \
  67. SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
  68. SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
  69. SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \
  70. &ename##_control)
  71. #define TX_WIDGETS(sname) \
  72. SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
  73. SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0)
  74. #define DAI(sname) \
  75. { \
  76. .name = "XBAR-" #sname, \
  77. .playback = { \
  78. .stream_name = #sname " XBAR-Playback", \
  79. .channels_min = 1, \
  80. .channels_max = 16, \
  81. .rates = SNDRV_PCM_RATE_8000_192000, \
  82. .formats = SNDRV_PCM_FMTBIT_S8 | \
  83. SNDRV_PCM_FMTBIT_S16_LE | \
  84. SNDRV_PCM_FMTBIT_S24_LE | \
  85. SNDRV_PCM_FMTBIT_S32_LE, \
  86. }, \
  87. .capture = { \
  88. .stream_name = #sname " XBAR-Capture", \
  89. .channels_min = 1, \
  90. .channels_max = 16, \
  91. .rates = SNDRV_PCM_RATE_8000_192000, \
  92. .formats = SNDRV_PCM_FMTBIT_S8 | \
  93. SNDRV_PCM_FMTBIT_S16_LE | \
  94. SNDRV_PCM_FMTBIT_S24_LE | \
  95. SNDRV_PCM_FMTBIT_S32_LE, \
  96. }, \
  97. }
  98. struct tegra_ahub_soc_data {
  99. const struct regmap_config *regmap_config;
  100. const struct snd_soc_component_driver *cmpnt_drv;
  101. struct snd_soc_dai_driver *dai_drv;
  102. unsigned int mask[4];
  103. unsigned int reg_count;
  104. unsigned int num_dais;
  105. };
  106. struct tegra_ahub {
  107. const struct tegra_ahub_soc_data *soc_data;
  108. struct regmap *regmap;
  109. struct clk *clk;
  110. };
  111. #endif