stm32_sai.h 10.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
  4. *
  5. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6. * Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
  7. */
  8. #include <linux/bitfield.h>
  9. /******************** SAI Register Map **************************************/
  10. /* Global configuration register */
  11. #define STM_SAI_GCR 0x00
  12. /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */
  13. #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */
  14. #define STM_SAI_CR2_REGX 0x04
  15. #define STM_SAI_FRCR_REGX 0x08
  16. #define STM_SAI_SLOTR_REGX 0x0C
  17. #define STM_SAI_IMR_REGX 0x10
  18. #define STM_SAI_SR_REGX 0x14
  19. #define STM_SAI_CLRFR_REGX 0x18
  20. #define STM_SAI_DR_REGX 0x1C
  21. /* Sub-block A registers, relative to sub-block A address */
  22. #define STM_SAI_PDMCR_REGX 0x40
  23. #define STM_SAI_PDMLY_REGX 0x44
  24. /* Hardware configuration registers */
  25. #define STM_SAI_HWCFGR 0x3F0
  26. #define STM_SAI_VERR 0x3F4
  27. #define STM_SAI_IDR 0x3F8
  28. #define STM_SAI_SIDR 0x3FC
  29. /******************** Bit definition for SAI_GCR register *******************/
  30. #define SAI_GCR_SYNCIN_SHIFT 0
  31. #define SAI_GCR_SYNCIN_WDTH 2
  32. #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
  33. #define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\
  34. SAI_GCR_SYNCIN_MASK)
  35. #define SAI_GCR_SYNCOUT_SHIFT 4
  36. #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
  37. /******************* Bit definition for SAI_XCR1 register *******************/
  38. #define SAI_XCR1_RX_TX_SHIFT 0
  39. #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT)
  40. #define SAI_XCR1_SLAVE_SHIFT 1
  41. #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT)
  42. #define SAI_XCR1_PRTCFG_SHIFT 2
  43. #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)
  44. #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT)
  45. #define SAI_XCR1_DS_SHIFT 5
  46. #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT)
  47. #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT)
  48. #define SAI_XCR1_LSBFIRST_SHIFT 8
  49. #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT)
  50. #define SAI_XCR1_CKSTR_SHIFT 9
  51. #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT)
  52. #define SAI_XCR1_SYNCEN_SHIFT 10
  53. #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)
  54. #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT)
  55. #define SAI_XCR1_MONO_SHIFT 12
  56. #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT)
  57. #define SAI_XCR1_OUTDRIV_SHIFT 13
  58. #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT)
  59. #define SAI_XCR1_SAIEN_SHIFT 16
  60. #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT)
  61. #define SAI_XCR1_DMAEN_SHIFT 17
  62. #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT)
  63. #define SAI_XCR1_NODIV_SHIFT 19
  64. #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT)
  65. #define SAI_XCR1_MCKDIV_SHIFT 20
  66. #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == STM_SAI_STM32F4) ? 4 : 6)
  67. #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
  68. SAI_XCR1_MCKDIV_SHIFT)
  69. #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT)
  70. #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1)
  71. #define SAI_XCR1_OSR_SHIFT 26
  72. #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT)
  73. #define SAI_XCR1_MCKEN_SHIFT 27
  74. #define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT)
  75. /******************* Bit definition for SAI_XCR2 register *******************/
  76. #define SAI_XCR2_FTH_SHIFT 0
  77. #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT)
  78. #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT)
  79. #define SAI_XCR2_FFLUSH_SHIFT 3
  80. #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT)
  81. #define SAI_XCR2_TRIS_SHIFT 4
  82. #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT)
  83. #define SAI_XCR2_MUTE_SHIFT 5
  84. #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT)
  85. #define SAI_XCR2_MUTEVAL_SHIFT 6
  86. #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT)
  87. #define SAI_XCR2_MUTECNT_SHIFT 7
  88. #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)
  89. #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT)
  90. #define SAI_XCR2_CPL_SHIFT 13
  91. #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT)
  92. #define SAI_XCR2_COMP_SHIFT 14
  93. #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT)
  94. #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT)
  95. /****************** Bit definition for SAI_XFRCR register *******************/
  96. #define SAI_XFRCR_FRL_SHIFT 0
  97. #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT)
  98. #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT)
  99. #define SAI_XFRCR_FSALL_SHIFT 8
  100. #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT)
  101. #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT)
  102. #define SAI_XFRCR_FSDEF_SHIFT 16
  103. #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT)
  104. #define SAI_XFRCR_FSPOL_SHIFT 17
  105. #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT)
  106. #define SAI_XFRCR_FSOFF_SHIFT 18
  107. #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT)
  108. /****************** Bit definition for SAI_XSLOTR register ******************/
  109. #define SAI_XSLOTR_FBOFF_SHIFT 0
  110. #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT)
  111. #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT)
  112. #define SAI_XSLOTR_SLOTSZ_SHIFT 6
  113. #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT)
  114. #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT)
  115. #define SAI_XSLOTR_NBSLOT_SHIFT 8
  116. #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT)
  117. #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT)
  118. #define SAI_XSLOTR_SLOTEN_SHIFT 16
  119. #define SAI_XSLOTR_SLOTEN_WIDTH 16
  120. #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT)
  121. #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT)
  122. /******************* Bit definition for SAI_XIMR register *******************/
  123. #define SAI_XIMR_OVRUDRIE BIT(0)
  124. #define SAI_XIMR_MUTEDETIE BIT(1)
  125. #define SAI_XIMR_WCKCFGIE BIT(2)
  126. #define SAI_XIMR_FREQIE BIT(3)
  127. #define SAI_XIMR_CNRDYIE BIT(4)
  128. #define SAI_XIMR_AFSDETIE BIT(5)
  129. #define SAI_XIMR_LFSDETIE BIT(6)
  130. #define SAI_XIMR_SHIFT 0
  131. #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT)
  132. /******************** Bit definition for SAI_XSR register *******************/
  133. #define SAI_XSR_OVRUDR BIT(0)
  134. #define SAI_XSR_MUTEDET BIT(1)
  135. #define SAI_XSR_WCKCFG BIT(2)
  136. #define SAI_XSR_FREQ BIT(3)
  137. #define SAI_XSR_CNRDY BIT(4)
  138. #define SAI_XSR_AFSDET BIT(5)
  139. #define SAI_XSR_LFSDET BIT(6)
  140. #define SAI_XSR_SHIFT 0
  141. #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT)
  142. /****************** Bit definition for SAI_XCLRFR register ******************/
  143. #define SAI_XCLRFR_COVRUDR BIT(0)
  144. #define SAI_XCLRFR_CMUTEDET BIT(1)
  145. #define SAI_XCLRFR_CWCKCFG BIT(2)
  146. #define SAI_XCLRFR_CFREQ BIT(3)
  147. #define SAI_XCLRFR_CCNRDY BIT(4)
  148. #define SAI_XCLRFR_CAFSDET BIT(5)
  149. #define SAI_XCLRFR_CLFSDET BIT(6)
  150. #define SAI_XCLRFR_SHIFT 0
  151. #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT)
  152. /****************** Bit definition for SAI_PDMCR register ******************/
  153. #define SAI_PDMCR_PDMEN BIT(0)
  154. #define SAI_PDMCR_MICNBR_SHIFT 4
  155. #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)
  156. #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT)
  157. #define SAI_PDMCR_CKEN1 BIT(8)
  158. #define SAI_PDMCR_CKEN2 BIT(9)
  159. #define SAI_PDMCR_CKEN3 BIT(10)
  160. #define SAI_PDMCR_CKEN4 BIT(11)
  161. /****************** Bit definition for (SAI_PDMDLY register ****************/
  162. #define SAI_PDMDLY_1L_SHIFT 0
  163. #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT)
  164. #define SAI_PDMDLY_1L_WIDTH 3
  165. #define SAI_PDMDLY_1R_SHIFT 4
  166. #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT)
  167. #define SAI_PDMDLY_1R_WIDTH 3
  168. #define SAI_PDMDLY_2L_SHIFT 8
  169. #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT)
  170. #define SAI_PDMDLY_2L_WIDTH 3
  171. #define SAI_PDMDLY_2R_SHIFT 12
  172. #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT)
  173. #define SAI_PDMDLY_2R_WIDTH 3
  174. #define SAI_PDMDLY_3L_SHIFT 16
  175. #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT)
  176. #define SAI_PDMDLY_3L_WIDTH 3
  177. #define SAI_PDMDLY_3R_SHIFT 20
  178. #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT)
  179. #define SAI_PDMDLY_3R_WIDTH 3
  180. #define SAI_PDMDLY_4L_SHIFT 24
  181. #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT)
  182. #define SAI_PDMDLY_4L_WIDTH 3
  183. #define SAI_PDMDLY_4R_SHIFT 28
  184. #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT)
  185. #define SAI_PDMDLY_4R_WIDTH 3
  186. /* Registers below apply to SAI version 2.1 and more */
  187. /* Bit definition for SAI_HWCFGR register */
  188. #define SAI_HWCFGR_FIFO_SIZE GENMASK(7, 0)
  189. #define SAI_HWCFGR_SPDIF_PDM GENMASK(11, 8)
  190. #define SAI_HWCFGR_REGOUT GENMASK(19, 12)
  191. /* Bit definition for SAI_VERR register */
  192. #define SAI_VERR_MIN_MASK GENMASK(3, 0)
  193. #define SAI_VERR_MAJ_MASK GENMASK(7, 4)
  194. /* Bit definition for SAI_IDR register */
  195. #define SAI_IDR_ID_MASK GENMASK(31, 0)
  196. /* Bit definition for SAI_SIDR register */
  197. #define SAI_SIDR_ID_MASK GENMASK(31, 0)
  198. #define SAI_IPIDR_NUMBER 0x00130031
  199. /* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */
  200. #define STM_SAI_STM32F4 BIT(4)
  201. /* Dummy version number for H7 socs and next */
  202. #define STM_SAI_STM32H7 0x0
  203. #define STM_SAI_IS_F4(ip) ((ip)->conf.version == STM_SAI_STM32F4)
  204. #define STM_SAI_HAS_SPDIF_PDM(ip)\
  205. ((ip)->pdata->conf.has_spdif_pdm)
  206. enum stm32_sai_syncout {
  207. STM_SAI_SYNC_OUT_NONE,
  208. STM_SAI_SYNC_OUT_A,
  209. STM_SAI_SYNC_OUT_B,
  210. };
  211. /**
  212. * struct stm32_sai_conf - SAI configuration
  213. * @version: SAI version
  214. * @fifo_size: SAI fifo size as words number
  215. * @has_spdif_pdm: SAI S/PDIF and PDM features support flag
  216. */
  217. struct stm32_sai_conf {
  218. u32 version;
  219. u32 fifo_size;
  220. bool has_spdif_pdm;
  221. };
  222. /**
  223. * struct stm32_sai_data - private data of SAI instance driver
  224. * @pdev: device data pointer
  225. * @base: common register bank virtual base address
  226. * @pclk: SAI bus clock
  227. * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
  228. * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
  229. * @conf: SAI hardware capabitilites
  230. * @irq: SAI interrupt line
  231. * @set_sync: pointer to synchro mode configuration callback
  232. * @gcr: SAI Global Configuration Register
  233. */
  234. struct stm32_sai_data {
  235. struct platform_device *pdev;
  236. void __iomem *base;
  237. struct clk *pclk;
  238. struct clk *clk_x8k;
  239. struct clk *clk_x11k;
  240. struct stm32_sai_conf conf;
  241. int irq;
  242. int (*set_sync)(struct stm32_sai_data *sai,
  243. struct device_node *np_provider, int synco, int synci);
  244. u32 gcr;
  245. };