stm32_sai.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
  4. *
  5. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6. * Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
  7. */
  8. #include <linux/bitfield.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/module.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/pinctrl/consumer.h>
  14. #include <linux/reset.h>
  15. #include <sound/dmaengine_pcm.h>
  16. #include <sound/core.h>
  17. #include "stm32_sai.h"
  18. static const struct stm32_sai_conf stm32_sai_conf_f4 = {
  19. .version = STM_SAI_STM32F4,
  20. .fifo_size = 8,
  21. .has_spdif_pdm = false,
  22. };
  23. /*
  24. * Default settings for stm32 H7 socs and next.
  25. * These default settings will be overridden if the soc provides
  26. * support of hardware configuration registers.
  27. */
  28. static const struct stm32_sai_conf stm32_sai_conf_h7 = {
  29. .version = STM_SAI_STM32H7,
  30. .fifo_size = 8,
  31. .has_spdif_pdm = true,
  32. };
  33. static const struct of_device_id stm32_sai_ids[] = {
  34. { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
  35. { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
  36. {}
  37. };
  38. static int stm32_sai_pclk_disable(struct device *dev)
  39. {
  40. struct stm32_sai_data *sai = dev_get_drvdata(dev);
  41. clk_disable_unprepare(sai->pclk);
  42. return 0;
  43. }
  44. static int stm32_sai_pclk_enable(struct device *dev)
  45. {
  46. struct stm32_sai_data *sai = dev_get_drvdata(dev);
  47. int ret;
  48. ret = clk_prepare_enable(sai->pclk);
  49. if (ret) {
  50. dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
  51. return ret;
  52. }
  53. return 0;
  54. }
  55. static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
  56. {
  57. int ret;
  58. /* Enable peripheral clock to allow GCR register access */
  59. ret = stm32_sai_pclk_enable(&sai->pdev->dev);
  60. if (ret)
  61. return ret;
  62. writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
  63. stm32_sai_pclk_disable(&sai->pdev->dev);
  64. return 0;
  65. }
  66. static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
  67. {
  68. u32 prev_synco;
  69. int ret;
  70. /* Enable peripheral clock to allow GCR register access */
  71. ret = stm32_sai_pclk_enable(&sai->pdev->dev);
  72. if (ret)
  73. return ret;
  74. dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
  75. sai->pdev->dev.of_node,
  76. synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
  77. prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
  78. if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
  79. dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
  80. sai->pdev->dev.of_node,
  81. prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
  82. stm32_sai_pclk_disable(&sai->pdev->dev);
  83. return -EINVAL;
  84. }
  85. writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
  86. stm32_sai_pclk_disable(&sai->pdev->dev);
  87. return 0;
  88. }
  89. static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
  90. struct device_node *np_provider,
  91. int synco, int synci)
  92. {
  93. struct platform_device *pdev = of_find_device_by_node(np_provider);
  94. struct stm32_sai_data *sai_provider;
  95. int ret;
  96. if (!pdev) {
  97. dev_err(&sai_client->pdev->dev,
  98. "Device not found for node %pOFn\n", np_provider);
  99. of_node_put(np_provider);
  100. return -ENODEV;
  101. }
  102. sai_provider = platform_get_drvdata(pdev);
  103. if (!sai_provider) {
  104. dev_err(&sai_client->pdev->dev,
  105. "SAI sync provider data not found\n");
  106. ret = -EINVAL;
  107. goto error;
  108. }
  109. /* Configure sync client */
  110. ret = stm32_sai_sync_conf_client(sai_client, synci);
  111. if (ret < 0)
  112. goto error;
  113. /* Configure sync provider */
  114. ret = stm32_sai_sync_conf_provider(sai_provider, synco);
  115. error:
  116. put_device(&pdev->dev);
  117. of_node_put(np_provider);
  118. return ret;
  119. }
  120. static int stm32_sai_probe(struct platform_device *pdev)
  121. {
  122. struct stm32_sai_data *sai;
  123. struct reset_control *rst;
  124. const struct of_device_id *of_id;
  125. u32 val;
  126. int ret;
  127. sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
  128. if (!sai)
  129. return -ENOMEM;
  130. sai->base = devm_platform_ioremap_resource(pdev, 0);
  131. if (IS_ERR(sai->base))
  132. return PTR_ERR(sai->base);
  133. of_id = of_match_device(stm32_sai_ids, &pdev->dev);
  134. if (of_id)
  135. memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
  136. sizeof(struct stm32_sai_conf));
  137. else
  138. return -EINVAL;
  139. if (!STM_SAI_IS_F4(sai)) {
  140. sai->pclk = devm_clk_get(&pdev->dev, "pclk");
  141. if (IS_ERR(sai->pclk))
  142. return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
  143. "missing bus clock pclk\n");
  144. }
  145. sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
  146. if (IS_ERR(sai->clk_x8k))
  147. return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x8k),
  148. "missing x8k parent clock\n");
  149. sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
  150. if (IS_ERR(sai->clk_x11k))
  151. return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x11k),
  152. "missing x11k parent clock\n");
  153. /* init irqs */
  154. sai->irq = platform_get_irq(pdev, 0);
  155. if (sai->irq < 0)
  156. return sai->irq;
  157. /* reset */
  158. rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
  159. if (IS_ERR(rst))
  160. return dev_err_probe(&pdev->dev, PTR_ERR(rst),
  161. "Reset controller error\n");
  162. reset_control_assert(rst);
  163. udelay(2);
  164. reset_control_deassert(rst);
  165. /* Enable peripheral clock to allow register access */
  166. ret = clk_prepare_enable(sai->pclk);
  167. if (ret) {
  168. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  169. return ret;
  170. }
  171. val = FIELD_GET(SAI_IDR_ID_MASK,
  172. readl_relaxed(sai->base + STM_SAI_IDR));
  173. if (val == SAI_IPIDR_NUMBER) {
  174. val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
  175. sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
  176. sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
  177. val);
  178. val = readl_relaxed(sai->base + STM_SAI_VERR);
  179. sai->conf.version = val;
  180. dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
  181. FIELD_GET(SAI_VERR_MAJ_MASK, val),
  182. FIELD_GET(SAI_VERR_MIN_MASK, val));
  183. }
  184. clk_disable_unprepare(sai->pclk);
  185. sai->pdev = pdev;
  186. sai->set_sync = &stm32_sai_set_sync;
  187. platform_set_drvdata(pdev, sai);
  188. return devm_of_platform_populate(&pdev->dev);
  189. }
  190. #ifdef CONFIG_PM_SLEEP
  191. /*
  192. * When pins are shared by two sai sub instances, pins have to be defined
  193. * in sai parent node. In this case, pins state is not managed by alsa fw.
  194. * These pins are managed in suspend/resume callbacks.
  195. */
  196. static int stm32_sai_suspend(struct device *dev)
  197. {
  198. struct stm32_sai_data *sai = dev_get_drvdata(dev);
  199. int ret;
  200. ret = stm32_sai_pclk_enable(dev);
  201. if (ret)
  202. return ret;
  203. sai->gcr = readl_relaxed(sai->base);
  204. stm32_sai_pclk_disable(dev);
  205. return pinctrl_pm_select_sleep_state(dev);
  206. }
  207. static int stm32_sai_resume(struct device *dev)
  208. {
  209. struct stm32_sai_data *sai = dev_get_drvdata(dev);
  210. int ret;
  211. ret = stm32_sai_pclk_enable(dev);
  212. if (ret)
  213. return ret;
  214. writel_relaxed(sai->gcr, sai->base);
  215. stm32_sai_pclk_disable(dev);
  216. return pinctrl_pm_select_default_state(dev);
  217. }
  218. #endif /* CONFIG_PM_SLEEP */
  219. static const struct dev_pm_ops stm32_sai_pm_ops = {
  220. SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
  221. };
  222. MODULE_DEVICE_TABLE(of, stm32_sai_ids);
  223. static struct platform_driver stm32_sai_driver = {
  224. .driver = {
  225. .name = "st,stm32-sai",
  226. .of_match_table = stm32_sai_ids,
  227. .pm = &stm32_sai_pm_ops,
  228. },
  229. .probe = stm32_sai_probe,
  230. };
  231. module_platform_driver(stm32_sai_driver);
  232. MODULE_DESCRIPTION("STM32 Soc SAI Interface");
  233. MODULE_AUTHOR("Olivier Moysan <[email protected]>");
  234. MODULE_ALIAS("platform:st,stm32-sai");
  235. MODULE_LICENSE("GPL v2");