stm32_i2s.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
  4. *
  5. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. * Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
  7. */
  8. #include <linux/bitfield.h>
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regmap.h>
  17. #include <linux/reset.h>
  18. #include <linux/spinlock.h>
  19. #include <sound/dmaengine_pcm.h>
  20. #include <sound/pcm_params.h>
  21. #define STM32_I2S_CR1_REG 0x0
  22. #define STM32_I2S_CFG1_REG 0x08
  23. #define STM32_I2S_CFG2_REG 0x0C
  24. #define STM32_I2S_IER_REG 0x10
  25. #define STM32_I2S_SR_REG 0x14
  26. #define STM32_I2S_IFCR_REG 0x18
  27. #define STM32_I2S_TXDR_REG 0X20
  28. #define STM32_I2S_RXDR_REG 0x30
  29. #define STM32_I2S_CGFR_REG 0X50
  30. #define STM32_I2S_HWCFGR_REG 0x3F0
  31. #define STM32_I2S_VERR_REG 0x3F4
  32. #define STM32_I2S_IPIDR_REG 0x3F8
  33. #define STM32_I2S_SIDR_REG 0x3FC
  34. /* Bit definition for SPI2S_CR1 register */
  35. #define I2S_CR1_SPE BIT(0)
  36. #define I2S_CR1_CSTART BIT(9)
  37. #define I2S_CR1_CSUSP BIT(10)
  38. #define I2S_CR1_HDDIR BIT(11)
  39. #define I2S_CR1_SSI BIT(12)
  40. #define I2S_CR1_CRC33_17 BIT(13)
  41. #define I2S_CR1_RCRCI BIT(14)
  42. #define I2S_CR1_TCRCI BIT(15)
  43. /* Bit definition for SPI_CFG2 register */
  44. #define I2S_CFG2_IOSWP_SHIFT 15
  45. #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
  46. #define I2S_CFG2_LSBFRST BIT(23)
  47. #define I2S_CFG2_AFCNTR BIT(31)
  48. /* Bit definition for SPI_CFG1 register */
  49. #define I2S_CFG1_FTHVL_SHIFT 5
  50. #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  51. #define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
  52. #define I2S_CFG1_TXDMAEN BIT(15)
  53. #define I2S_CFG1_RXDMAEN BIT(14)
  54. /* Bit definition for SPI2S_IER register */
  55. #define I2S_IER_RXPIE BIT(0)
  56. #define I2S_IER_TXPIE BIT(1)
  57. #define I2S_IER_DPXPIE BIT(2)
  58. #define I2S_IER_EOTIE BIT(3)
  59. #define I2S_IER_TXTFIE BIT(4)
  60. #define I2S_IER_UDRIE BIT(5)
  61. #define I2S_IER_OVRIE BIT(6)
  62. #define I2S_IER_CRCEIE BIT(7)
  63. #define I2S_IER_TIFREIE BIT(8)
  64. #define I2S_IER_MODFIE BIT(9)
  65. #define I2S_IER_TSERFIE BIT(10)
  66. /* Bit definition for SPI2S_SR register */
  67. #define I2S_SR_RXP BIT(0)
  68. #define I2S_SR_TXP BIT(1)
  69. #define I2S_SR_DPXP BIT(2)
  70. #define I2S_SR_EOT BIT(3)
  71. #define I2S_SR_TXTF BIT(4)
  72. #define I2S_SR_UDR BIT(5)
  73. #define I2S_SR_OVR BIT(6)
  74. #define I2S_SR_CRCERR BIT(7)
  75. #define I2S_SR_TIFRE BIT(8)
  76. #define I2S_SR_MODF BIT(9)
  77. #define I2S_SR_TSERF BIT(10)
  78. #define I2S_SR_SUSP BIT(11)
  79. #define I2S_SR_TXC BIT(12)
  80. #define I2S_SR_RXPLVL GENMASK(14, 13)
  81. #define I2S_SR_RXWNE BIT(15)
  82. #define I2S_SR_MASK GENMASK(15, 0)
  83. /* Bit definition for SPI_IFCR register */
  84. #define I2S_IFCR_EOTC BIT(3)
  85. #define I2S_IFCR_TXTFC BIT(4)
  86. #define I2S_IFCR_UDRC BIT(5)
  87. #define I2S_IFCR_OVRC BIT(6)
  88. #define I2S_IFCR_CRCEC BIT(7)
  89. #define I2S_IFCR_TIFREC BIT(8)
  90. #define I2S_IFCR_MODFC BIT(9)
  91. #define I2S_IFCR_TSERFC BIT(10)
  92. #define I2S_IFCR_SUSPC BIT(11)
  93. #define I2S_IFCR_MASK GENMASK(11, 3)
  94. /* Bit definition for SPI_I2SCGFR register */
  95. #define I2S_CGFR_I2SMOD BIT(0)
  96. #define I2S_CGFR_I2SCFG_SHIFT 1
  97. #define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
  98. #define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
  99. #define I2S_CGFR_I2SSTD_SHIFT 4
  100. #define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
  101. #define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
  102. #define I2S_CGFR_PCMSYNC BIT(7)
  103. #define I2S_CGFR_DATLEN_SHIFT 8
  104. #define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
  105. #define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
  106. #define I2S_CGFR_CHLEN_SHIFT 10
  107. #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
  108. #define I2S_CGFR_CKPOL BIT(11)
  109. #define I2S_CGFR_FIXCH BIT(12)
  110. #define I2S_CGFR_WSINV BIT(13)
  111. #define I2S_CGFR_DATFMT BIT(14)
  112. #define I2S_CGFR_I2SDIV_SHIFT 16
  113. #define I2S_CGFR_I2SDIV_BIT_H 23
  114. #define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
  115. I2S_CGFR_I2SDIV_SHIFT)
  116. #define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
  117. #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
  118. I2S_CGFR_I2SDIV_SHIFT)) - 1)
  119. #define I2S_CGFR_ODD_SHIFT 24
  120. #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
  121. #define I2S_CGFR_MCKOE BIT(25)
  122. /* Registers below apply to I2S version 1.1 and more */
  123. /* Bit definition for SPI_HWCFGR register */
  124. #define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
  125. /* Bit definition for SPI_VERR register */
  126. #define I2S_VERR_MIN_MASK GENMASK(3, 0)
  127. #define I2S_VERR_MAJ_MASK GENMASK(7, 4)
  128. /* Bit definition for SPI_IPIDR register */
  129. #define I2S_IPIDR_ID_MASK GENMASK(31, 0)
  130. /* Bit definition for SPI_SIDR register */
  131. #define I2S_SIDR_ID_MASK GENMASK(31, 0)
  132. #define I2S_IPIDR_NUMBER 0x00130022
  133. enum i2s_master_mode {
  134. I2S_MS_NOT_SET,
  135. I2S_MS_MASTER,
  136. I2S_MS_SLAVE,
  137. };
  138. enum i2s_mode {
  139. I2S_I2SMOD_TX_SLAVE,
  140. I2S_I2SMOD_RX_SLAVE,
  141. I2S_I2SMOD_TX_MASTER,
  142. I2S_I2SMOD_RX_MASTER,
  143. I2S_I2SMOD_FD_SLAVE,
  144. I2S_I2SMOD_FD_MASTER,
  145. };
  146. enum i2s_fifo_th {
  147. I2S_FIFO_TH_NONE,
  148. I2S_FIFO_TH_ONE_QUARTER,
  149. I2S_FIFO_TH_HALF,
  150. I2S_FIFO_TH_THREE_QUARTER,
  151. I2S_FIFO_TH_FULL,
  152. };
  153. enum i2s_std {
  154. I2S_STD_I2S,
  155. I2S_STD_LEFT_J,
  156. I2S_STD_RIGHT_J,
  157. I2S_STD_DSP,
  158. };
  159. enum i2s_datlen {
  160. I2S_I2SMOD_DATLEN_16,
  161. I2S_I2SMOD_DATLEN_24,
  162. I2S_I2SMOD_DATLEN_32,
  163. };
  164. #define STM32_I2S_FIFO_SIZE 16
  165. #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
  166. #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
  167. #define STM32_I2S_NAME_LEN 32
  168. #define STM32_I2S_RATE_11K 11025
  169. /**
  170. * struct stm32_i2s_data - private data of I2S
  171. * @regmap_conf: I2S register map configuration pointer
  172. * @regmap: I2S register map pointer
  173. * @pdev: device data pointer
  174. * @dai_drv: DAI driver pointer
  175. * @dma_data_tx: dma configuration data for tx channel
  176. * @dma_data_rx: dma configuration data for tx channel
  177. * @substream: PCM substream data pointer
  178. * @i2sclk: kernel clock feeding the I2S clock generator
  179. * @i2smclk: master clock from I2S mclk provider
  180. * @pclk: peripheral clock driving bus interface
  181. * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
  182. * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
  183. * @base: mmio register base virtual address
  184. * @phys_addr: I2S registers physical base address
  185. * @lock_fd: lock to manage race conditions in full duplex mode
  186. * @irq_lock: prevent race condition with IRQ
  187. * @mclk_rate: master clock frequency (Hz)
  188. * @fmt: DAI protocol
  189. * @divider: prescaler division ratio
  190. * @div: prescaler div field
  191. * @odd: prescaler odd field
  192. * @refcount: keep count of opened streams on I2S
  193. * @ms_flg: master mode flag.
  194. */
  195. struct stm32_i2s_data {
  196. const struct regmap_config *regmap_conf;
  197. struct regmap *regmap;
  198. struct platform_device *pdev;
  199. struct snd_soc_dai_driver *dai_drv;
  200. struct snd_dmaengine_dai_dma_data dma_data_tx;
  201. struct snd_dmaengine_dai_dma_data dma_data_rx;
  202. struct snd_pcm_substream *substream;
  203. struct clk *i2sclk;
  204. struct clk *i2smclk;
  205. struct clk *pclk;
  206. struct clk *x8kclk;
  207. struct clk *x11kclk;
  208. void __iomem *base;
  209. dma_addr_t phys_addr;
  210. spinlock_t lock_fd; /* Manage race conditions for full duplex */
  211. spinlock_t irq_lock; /* used to prevent race condition with IRQ */
  212. unsigned int mclk_rate;
  213. unsigned int fmt;
  214. unsigned int divider;
  215. unsigned int div;
  216. bool odd;
  217. int refcount;
  218. int ms_flg;
  219. };
  220. struct stm32_i2smclk_data {
  221. struct clk_hw hw;
  222. unsigned long freq;
  223. struct stm32_i2s_data *i2s_data;
  224. };
  225. #define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
  226. static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
  227. unsigned long input_rate,
  228. unsigned long output_rate)
  229. {
  230. unsigned int ratio, div, divider = 1;
  231. bool odd;
  232. ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
  233. /* Check the parity of the divider */
  234. odd = ratio & 0x1;
  235. /* Compute the div prescaler */
  236. div = ratio >> 1;
  237. /* If div is 0 actual divider is 1 */
  238. if (div) {
  239. divider = ((2 * div) + odd);
  240. dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
  241. div, odd, divider);
  242. }
  243. /* Division by three is not allowed by I2S prescaler */
  244. if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
  245. dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
  246. return -EINVAL;
  247. }
  248. if (input_rate % divider)
  249. dev_dbg(&i2s->pdev->dev,
  250. "Rate not accurate. requested (%ld), actual (%ld)\n",
  251. output_rate, input_rate / divider);
  252. i2s->div = div;
  253. i2s->odd = odd;
  254. i2s->divider = divider;
  255. return 0;
  256. }
  257. static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
  258. {
  259. u32 cgfr, cgfr_mask;
  260. cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
  261. cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
  262. return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
  263. cgfr_mask, cgfr);
  264. }
  265. static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
  266. unsigned int rate)
  267. {
  268. struct platform_device *pdev = i2s->pdev;
  269. struct clk *parent_clk;
  270. int ret;
  271. if (!(rate % STM32_I2S_RATE_11K))
  272. parent_clk = i2s->x11kclk;
  273. else
  274. parent_clk = i2s->x8kclk;
  275. ret = clk_set_parent(i2s->i2sclk, parent_clk);
  276. if (ret)
  277. dev_err(&pdev->dev,
  278. "Error %d setting i2sclk parent clock\n", ret);
  279. return ret;
  280. }
  281. static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
  282. unsigned long *prate)
  283. {
  284. struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
  285. struct stm32_i2s_data *i2s = mclk->i2s_data;
  286. int ret;
  287. ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
  288. if (ret)
  289. return ret;
  290. mclk->freq = *prate / i2s->divider;
  291. return mclk->freq;
  292. }
  293. static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
  294. unsigned long parent_rate)
  295. {
  296. struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
  297. return mclk->freq;
  298. }
  299. static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
  300. unsigned long parent_rate)
  301. {
  302. struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
  303. struct stm32_i2s_data *i2s = mclk->i2s_data;
  304. int ret;
  305. ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
  306. if (ret)
  307. return ret;
  308. ret = stm32_i2s_set_clk_div(i2s);
  309. if (ret)
  310. return ret;
  311. mclk->freq = rate;
  312. return 0;
  313. }
  314. static int stm32_i2smclk_enable(struct clk_hw *hw)
  315. {
  316. struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
  317. struct stm32_i2s_data *i2s = mclk->i2s_data;
  318. dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
  319. return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
  320. I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
  321. }
  322. static void stm32_i2smclk_disable(struct clk_hw *hw)
  323. {
  324. struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
  325. struct stm32_i2s_data *i2s = mclk->i2s_data;
  326. dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
  327. regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
  328. }
  329. static const struct clk_ops mclk_ops = {
  330. .enable = stm32_i2smclk_enable,
  331. .disable = stm32_i2smclk_disable,
  332. .recalc_rate = stm32_i2smclk_recalc_rate,
  333. .round_rate = stm32_i2smclk_round_rate,
  334. .set_rate = stm32_i2smclk_set_rate,
  335. };
  336. static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
  337. {
  338. struct clk_hw *hw;
  339. struct stm32_i2smclk_data *mclk;
  340. struct device *dev = &i2s->pdev->dev;
  341. const char *pname = __clk_get_name(i2s->i2sclk);
  342. char *mclk_name, *p, *s = (char *)pname;
  343. int ret, i = 0;
  344. mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
  345. if (!mclk)
  346. return -ENOMEM;
  347. mclk_name = devm_kcalloc(dev, sizeof(char),
  348. STM32_I2S_NAME_LEN, GFP_KERNEL);
  349. if (!mclk_name)
  350. return -ENOMEM;
  351. /*
  352. * Forge mclk clock name from parent clock name and suffix.
  353. * String after "_" char is stripped in parent name.
  354. */
  355. p = mclk_name;
  356. while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
  357. *p++ = *s++;
  358. i++;
  359. }
  360. strcat(p, "_mclk");
  361. mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
  362. mclk->i2s_data = i2s;
  363. hw = &mclk->hw;
  364. dev_dbg(dev, "Register master clock %s\n", mclk_name);
  365. ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
  366. if (ret) {
  367. dev_err(dev, "mclk register fails with error %d\n", ret);
  368. return ret;
  369. }
  370. i2s->i2smclk = hw->clk;
  371. /* register mclk provider */
  372. return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
  373. }
  374. static irqreturn_t stm32_i2s_isr(int irq, void *devid)
  375. {
  376. struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
  377. struct platform_device *pdev = i2s->pdev;
  378. u32 sr, ier;
  379. unsigned long flags;
  380. int err = 0;
  381. regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
  382. regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
  383. flags = sr & ier;
  384. if (!flags) {
  385. dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
  386. sr, ier);
  387. return IRQ_NONE;
  388. }
  389. regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
  390. I2S_IFCR_MASK, flags);
  391. if (flags & I2S_SR_OVR) {
  392. dev_dbg(&pdev->dev, "Overrun\n");
  393. err = 1;
  394. }
  395. if (flags & I2S_SR_UDR) {
  396. dev_dbg(&pdev->dev, "Underrun\n");
  397. err = 1;
  398. }
  399. if (flags & I2S_SR_TIFRE)
  400. dev_dbg(&pdev->dev, "Frame error\n");
  401. spin_lock(&i2s->irq_lock);
  402. if (err && i2s->substream)
  403. snd_pcm_stop_xrun(i2s->substream);
  404. spin_unlock(&i2s->irq_lock);
  405. return IRQ_HANDLED;
  406. }
  407. static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
  408. {
  409. switch (reg) {
  410. case STM32_I2S_CR1_REG:
  411. case STM32_I2S_CFG1_REG:
  412. case STM32_I2S_CFG2_REG:
  413. case STM32_I2S_IER_REG:
  414. case STM32_I2S_SR_REG:
  415. case STM32_I2S_RXDR_REG:
  416. case STM32_I2S_CGFR_REG:
  417. case STM32_I2S_HWCFGR_REG:
  418. case STM32_I2S_VERR_REG:
  419. case STM32_I2S_IPIDR_REG:
  420. case STM32_I2S_SIDR_REG:
  421. return true;
  422. default:
  423. return false;
  424. }
  425. }
  426. static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
  427. {
  428. switch (reg) {
  429. case STM32_I2S_SR_REG:
  430. case STM32_I2S_RXDR_REG:
  431. return true;
  432. default:
  433. return false;
  434. }
  435. }
  436. static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
  437. {
  438. switch (reg) {
  439. case STM32_I2S_CR1_REG:
  440. case STM32_I2S_CFG1_REG:
  441. case STM32_I2S_CFG2_REG:
  442. case STM32_I2S_IER_REG:
  443. case STM32_I2S_IFCR_REG:
  444. case STM32_I2S_TXDR_REG:
  445. case STM32_I2S_CGFR_REG:
  446. return true;
  447. default:
  448. return false;
  449. }
  450. }
  451. static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  452. {
  453. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  454. u32 cgfr;
  455. u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
  456. I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
  457. dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
  458. /*
  459. * winv = 0 : default behavior (high/low) for all standards
  460. * ckpol = 0 for all standards.
  461. */
  462. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  463. case SND_SOC_DAIFMT_I2S:
  464. cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
  465. break;
  466. case SND_SOC_DAIFMT_MSB:
  467. cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
  468. break;
  469. case SND_SOC_DAIFMT_LSB:
  470. cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
  471. break;
  472. case SND_SOC_DAIFMT_DSP_A:
  473. cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
  474. break;
  475. /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
  476. default:
  477. dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
  478. fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  479. return -EINVAL;
  480. }
  481. /* DAI clock strobing */
  482. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  483. case SND_SOC_DAIFMT_NB_NF:
  484. break;
  485. case SND_SOC_DAIFMT_IB_NF:
  486. cgfr |= I2S_CGFR_CKPOL;
  487. break;
  488. case SND_SOC_DAIFMT_NB_IF:
  489. cgfr |= I2S_CGFR_WSINV;
  490. break;
  491. case SND_SOC_DAIFMT_IB_IF:
  492. cgfr |= I2S_CGFR_CKPOL;
  493. cgfr |= I2S_CGFR_WSINV;
  494. break;
  495. default:
  496. dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
  497. fmt & SND_SOC_DAIFMT_INV_MASK);
  498. return -EINVAL;
  499. }
  500. /* DAI clock master masks */
  501. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  502. case SND_SOC_DAIFMT_BC_FC:
  503. i2s->ms_flg = I2S_MS_SLAVE;
  504. break;
  505. case SND_SOC_DAIFMT_BP_FP:
  506. i2s->ms_flg = I2S_MS_MASTER;
  507. break;
  508. default:
  509. dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
  510. fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
  511. return -EINVAL;
  512. }
  513. i2s->fmt = fmt;
  514. return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
  515. cgfr_mask, cgfr);
  516. }
  517. static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
  518. int clk_id, unsigned int freq, int dir)
  519. {
  520. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  521. int ret = 0;
  522. dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
  523. freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
  524. dir ? "output" : "input");
  525. /* MCLK generation is available only in master mode */
  526. if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
  527. if (!i2s->i2smclk) {
  528. dev_dbg(cpu_dai->dev, "No MCLK registered\n");
  529. return 0;
  530. }
  531. /* Assume shutdown if requested frequency is 0Hz */
  532. if (!freq) {
  533. /* Release mclk rate only if rate was actually set */
  534. if (i2s->mclk_rate) {
  535. clk_rate_exclusive_put(i2s->i2smclk);
  536. i2s->mclk_rate = 0;
  537. }
  538. return regmap_update_bits(i2s->regmap,
  539. STM32_I2S_CGFR_REG,
  540. I2S_CGFR_MCKOE, 0);
  541. }
  542. /* If master clock is used, set parent clock now */
  543. ret = stm32_i2s_set_parent_clock(i2s, freq);
  544. if (ret)
  545. return ret;
  546. ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
  547. if (ret) {
  548. dev_err(cpu_dai->dev, "Could not set mclk rate\n");
  549. return ret;
  550. }
  551. ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
  552. I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
  553. if (!ret)
  554. i2s->mclk_rate = freq;
  555. }
  556. return ret;
  557. }
  558. static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
  559. struct snd_pcm_hw_params *params)
  560. {
  561. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  562. unsigned long i2s_clock_rate;
  563. unsigned int nb_bits, frame_len;
  564. unsigned int rate = params_rate(params);
  565. u32 cgfr;
  566. int ret;
  567. if (!(rate % 11025))
  568. clk_set_parent(i2s->i2sclk, i2s->x11kclk);
  569. else
  570. clk_set_parent(i2s->i2sclk, i2s->x8kclk);
  571. i2s_clock_rate = clk_get_rate(i2s->i2sclk);
  572. /*
  573. * mckl = mclk_ratio x ws
  574. * i2s mode : mclk_ratio = 256
  575. * dsp mode : mclk_ratio = 128
  576. *
  577. * mclk on
  578. * i2s mode : div = i2s_clk / (mclk_ratio * ws)
  579. * dsp mode : div = i2s_clk / (mclk_ratio * ws)
  580. * mclk off
  581. * i2s mode : div = i2s_clk / (nb_bits x ws)
  582. * dsp mode : div = i2s_clk / (nb_bits x ws)
  583. */
  584. if (i2s->mclk_rate) {
  585. ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
  586. i2s->mclk_rate);
  587. if (ret)
  588. return ret;
  589. } else {
  590. frame_len = 32;
  591. if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
  592. SND_SOC_DAIFMT_DSP_A)
  593. frame_len = 16;
  594. /* master clock not enabled */
  595. ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
  596. if (ret < 0)
  597. return ret;
  598. nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
  599. ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
  600. (nb_bits * rate));
  601. if (ret)
  602. return ret;
  603. }
  604. ret = stm32_i2s_set_clk_div(i2s);
  605. if (ret < 0)
  606. return ret;
  607. /* Set bitclock and frameclock to their inactive state */
  608. return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
  609. I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
  610. }
  611. static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
  612. struct snd_pcm_hw_params *params,
  613. struct snd_pcm_substream *substream)
  614. {
  615. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  616. int format = params_width(params);
  617. u32 cfgr, cfgr_mask, cfg1;
  618. unsigned int fthlv;
  619. int ret;
  620. switch (format) {
  621. case 16:
  622. cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
  623. cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
  624. break;
  625. case 32:
  626. cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
  627. I2S_CGFR_CHLEN;
  628. cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
  629. break;
  630. default:
  631. dev_err(cpu_dai->dev, "Unexpected format %d", format);
  632. return -EINVAL;
  633. }
  634. if (STM32_I2S_IS_SLAVE(i2s)) {
  635. cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
  636. /* As data length is either 16 or 32 bits, fixch always set */
  637. cfgr |= I2S_CGFR_FIXCH;
  638. cfgr_mask |= I2S_CGFR_FIXCH;
  639. } else {
  640. cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
  641. }
  642. cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
  643. ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
  644. cfgr_mask, cfgr);
  645. if (ret < 0)
  646. return ret;
  647. fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
  648. cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
  649. return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
  650. I2S_CFG1_FTHVL_MASK, cfg1);
  651. }
  652. static int stm32_i2s_startup(struct snd_pcm_substream *substream,
  653. struct snd_soc_dai *cpu_dai)
  654. {
  655. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  656. unsigned long flags;
  657. int ret;
  658. spin_lock_irqsave(&i2s->irq_lock, flags);
  659. i2s->substream = substream;
  660. spin_unlock_irqrestore(&i2s->irq_lock, flags);
  661. if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
  662. snd_pcm_hw_constraint_single(substream->runtime,
  663. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  664. ret = clk_prepare_enable(i2s->i2sclk);
  665. if (ret < 0) {
  666. dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
  667. return ret;
  668. }
  669. return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
  670. I2S_IFCR_MASK, I2S_IFCR_MASK);
  671. }
  672. static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
  673. struct snd_pcm_hw_params *params,
  674. struct snd_soc_dai *cpu_dai)
  675. {
  676. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  677. int ret;
  678. ret = stm32_i2s_configure(cpu_dai, params, substream);
  679. if (ret < 0) {
  680. dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
  681. return ret;
  682. }
  683. if (STM32_I2S_IS_MASTER(i2s))
  684. ret = stm32_i2s_configure_clock(cpu_dai, params);
  685. return ret;
  686. }
  687. static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  688. struct snd_soc_dai *cpu_dai)
  689. {
  690. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  691. bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  692. u32 cfg1_mask, ier;
  693. int ret;
  694. switch (cmd) {
  695. case SNDRV_PCM_TRIGGER_START:
  696. case SNDRV_PCM_TRIGGER_RESUME:
  697. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  698. /* Enable i2s */
  699. dev_dbg(cpu_dai->dev, "start I2S %s\n",
  700. playback_flg ? "playback" : "capture");
  701. cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
  702. regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
  703. cfg1_mask, cfg1_mask);
  704. ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
  705. I2S_CR1_SPE, I2S_CR1_SPE);
  706. if (ret < 0) {
  707. dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
  708. return ret;
  709. }
  710. ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
  711. I2S_CR1_CSTART, I2S_CR1_CSTART);
  712. if (ret < 0) {
  713. dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
  714. return ret;
  715. }
  716. regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
  717. I2S_IFCR_MASK, I2S_IFCR_MASK);
  718. spin_lock(&i2s->lock_fd);
  719. i2s->refcount++;
  720. if (playback_flg) {
  721. ier = I2S_IER_UDRIE;
  722. } else {
  723. ier = I2S_IER_OVRIE;
  724. if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
  725. /* dummy write to gate bus clocks */
  726. regmap_write(i2s->regmap,
  727. STM32_I2S_TXDR_REG, 0);
  728. }
  729. spin_unlock(&i2s->lock_fd);
  730. if (STM32_I2S_IS_SLAVE(i2s))
  731. ier |= I2S_IER_TIFREIE;
  732. regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
  733. break;
  734. case SNDRV_PCM_TRIGGER_STOP:
  735. case SNDRV_PCM_TRIGGER_SUSPEND:
  736. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  737. dev_dbg(cpu_dai->dev, "stop I2S %s\n",
  738. playback_flg ? "playback" : "capture");
  739. if (playback_flg)
  740. regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
  741. I2S_IER_UDRIE,
  742. (unsigned int)~I2S_IER_UDRIE);
  743. else
  744. regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
  745. I2S_IER_OVRIE,
  746. (unsigned int)~I2S_IER_OVRIE);
  747. spin_lock(&i2s->lock_fd);
  748. i2s->refcount--;
  749. if (i2s->refcount) {
  750. spin_unlock(&i2s->lock_fd);
  751. break;
  752. }
  753. ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
  754. I2S_CR1_SPE, 0);
  755. if (ret < 0) {
  756. dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
  757. spin_unlock(&i2s->lock_fd);
  758. return ret;
  759. }
  760. spin_unlock(&i2s->lock_fd);
  761. cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
  762. regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
  763. cfg1_mask, 0);
  764. break;
  765. default:
  766. return -EINVAL;
  767. }
  768. return 0;
  769. }
  770. static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
  771. struct snd_soc_dai *cpu_dai)
  772. {
  773. struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  774. unsigned long flags;
  775. clk_disable_unprepare(i2s->i2sclk);
  776. spin_lock_irqsave(&i2s->irq_lock, flags);
  777. i2s->substream = NULL;
  778. spin_unlock_irqrestore(&i2s->irq_lock, flags);
  779. }
  780. static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
  781. {
  782. struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
  783. struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
  784. struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
  785. /* Buswidth will be set by framework */
  786. dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  787. dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
  788. dma_data_tx->maxburst = 1;
  789. dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  790. dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
  791. dma_data_rx->maxburst = 1;
  792. snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
  793. return 0;
  794. }
  795. static const struct regmap_config stm32_h7_i2s_regmap_conf = {
  796. .reg_bits = 32,
  797. .reg_stride = 4,
  798. .val_bits = 32,
  799. .max_register = STM32_I2S_SIDR_REG,
  800. .readable_reg = stm32_i2s_readable_reg,
  801. .volatile_reg = stm32_i2s_volatile_reg,
  802. .writeable_reg = stm32_i2s_writeable_reg,
  803. .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
  804. .fast_io = true,
  805. .cache_type = REGCACHE_FLAT,
  806. };
  807. static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
  808. .set_sysclk = stm32_i2s_set_sysclk,
  809. .set_fmt = stm32_i2s_set_dai_fmt,
  810. .startup = stm32_i2s_startup,
  811. .hw_params = stm32_i2s_hw_params,
  812. .trigger = stm32_i2s_trigger,
  813. .shutdown = stm32_i2s_shutdown,
  814. };
  815. static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
  816. .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
  817. .buffer_bytes_max = 8 * PAGE_SIZE,
  818. .period_bytes_min = 1024,
  819. .period_bytes_max = 4 * PAGE_SIZE,
  820. .periods_min = 2,
  821. .periods_max = 8,
  822. };
  823. static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
  824. .pcm_hardware = &stm32_i2s_pcm_hw,
  825. .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  826. .prealloc_buffer_size = PAGE_SIZE * 8,
  827. };
  828. static const struct snd_soc_component_driver stm32_i2s_component = {
  829. .name = "stm32-i2s",
  830. .legacy_dai_naming = 1,
  831. };
  832. static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
  833. char *stream_name)
  834. {
  835. stream->stream_name = stream_name;
  836. stream->channels_min = 1;
  837. stream->channels_max = 2;
  838. stream->rates = SNDRV_PCM_RATE_8000_192000;
  839. stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
  840. SNDRV_PCM_FMTBIT_S32_LE;
  841. }
  842. static int stm32_i2s_dais_init(struct platform_device *pdev,
  843. struct stm32_i2s_data *i2s)
  844. {
  845. struct snd_soc_dai_driver *dai_ptr;
  846. dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
  847. GFP_KERNEL);
  848. if (!dai_ptr)
  849. return -ENOMEM;
  850. dai_ptr->probe = stm32_i2s_dai_probe;
  851. dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
  852. dai_ptr->id = 1;
  853. stm32_i2s_dai_init(&dai_ptr->playback, "playback");
  854. stm32_i2s_dai_init(&dai_ptr->capture, "capture");
  855. i2s->dai_drv = dai_ptr;
  856. return 0;
  857. }
  858. static const struct of_device_id stm32_i2s_ids[] = {
  859. {
  860. .compatible = "st,stm32h7-i2s",
  861. .data = &stm32_h7_i2s_regmap_conf
  862. },
  863. {},
  864. };
  865. static int stm32_i2s_parse_dt(struct platform_device *pdev,
  866. struct stm32_i2s_data *i2s)
  867. {
  868. struct device_node *np = pdev->dev.of_node;
  869. const struct of_device_id *of_id;
  870. struct reset_control *rst;
  871. struct resource *res;
  872. int irq, ret;
  873. if (!np)
  874. return -ENODEV;
  875. of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
  876. if (of_id)
  877. i2s->regmap_conf = (const struct regmap_config *)of_id->data;
  878. else
  879. return -EINVAL;
  880. i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  881. if (IS_ERR(i2s->base))
  882. return PTR_ERR(i2s->base);
  883. i2s->phys_addr = res->start;
  884. /* Get clocks */
  885. i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
  886. if (IS_ERR(i2s->pclk))
  887. return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
  888. "Could not get pclk\n");
  889. i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
  890. if (IS_ERR(i2s->i2sclk))
  891. return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
  892. "Could not get i2sclk\n");
  893. i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
  894. if (IS_ERR(i2s->x8kclk))
  895. return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
  896. "Could not get x8k parent clock\n");
  897. i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
  898. if (IS_ERR(i2s->x11kclk))
  899. return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
  900. "Could not get x11k parent clock\n");
  901. /* Register mclk provider if requested */
  902. if (of_find_property(np, "#clock-cells", NULL)) {
  903. ret = stm32_i2s_add_mclk_provider(i2s);
  904. if (ret < 0)
  905. return ret;
  906. }
  907. /* Get irqs */
  908. irq = platform_get_irq(pdev, 0);
  909. if (irq < 0)
  910. return irq;
  911. ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0,
  912. dev_name(&pdev->dev), i2s);
  913. if (ret) {
  914. dev_err(&pdev->dev, "irq request returned %d\n", ret);
  915. return ret;
  916. }
  917. /* Reset */
  918. rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
  919. if (IS_ERR(rst))
  920. return dev_err_probe(&pdev->dev, PTR_ERR(rst),
  921. "Reset controller error\n");
  922. reset_control_assert(rst);
  923. udelay(2);
  924. reset_control_deassert(rst);
  925. return 0;
  926. }
  927. static int stm32_i2s_remove(struct platform_device *pdev)
  928. {
  929. snd_dmaengine_pcm_unregister(&pdev->dev);
  930. snd_soc_unregister_component(&pdev->dev);
  931. pm_runtime_disable(&pdev->dev);
  932. return 0;
  933. }
  934. static int stm32_i2s_probe(struct platform_device *pdev)
  935. {
  936. struct stm32_i2s_data *i2s;
  937. u32 val;
  938. int ret;
  939. i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
  940. if (!i2s)
  941. return -ENOMEM;
  942. i2s->pdev = pdev;
  943. i2s->ms_flg = I2S_MS_NOT_SET;
  944. spin_lock_init(&i2s->lock_fd);
  945. spin_lock_init(&i2s->irq_lock);
  946. platform_set_drvdata(pdev, i2s);
  947. ret = stm32_i2s_parse_dt(pdev, i2s);
  948. if (ret)
  949. return ret;
  950. ret = stm32_i2s_dais_init(pdev, i2s);
  951. if (ret)
  952. return ret;
  953. i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
  954. i2s->base, i2s->regmap_conf);
  955. if (IS_ERR(i2s->regmap))
  956. return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
  957. "Regmap init error\n");
  958. ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
  959. if (ret)
  960. return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
  961. ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
  962. i2s->dai_drv, 1);
  963. if (ret) {
  964. snd_dmaengine_pcm_unregister(&pdev->dev);
  965. return ret;
  966. }
  967. /* Set SPI/I2S in i2s mode */
  968. ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
  969. I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
  970. if (ret)
  971. goto error;
  972. ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
  973. if (ret)
  974. goto error;
  975. if (val == I2S_IPIDR_NUMBER) {
  976. ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
  977. if (ret)
  978. goto error;
  979. if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
  980. dev_err(&pdev->dev,
  981. "Device does not support i2s mode\n");
  982. ret = -EPERM;
  983. goto error;
  984. }
  985. ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
  986. if (ret)
  987. goto error;
  988. dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
  989. FIELD_GET(I2S_VERR_MAJ_MASK, val),
  990. FIELD_GET(I2S_VERR_MIN_MASK, val));
  991. }
  992. pm_runtime_enable(&pdev->dev);
  993. return ret;
  994. error:
  995. stm32_i2s_remove(pdev);
  996. return ret;
  997. }
  998. MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
  999. #ifdef CONFIG_PM_SLEEP
  1000. static int stm32_i2s_suspend(struct device *dev)
  1001. {
  1002. struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
  1003. regcache_cache_only(i2s->regmap, true);
  1004. regcache_mark_dirty(i2s->regmap);
  1005. return 0;
  1006. }
  1007. static int stm32_i2s_resume(struct device *dev)
  1008. {
  1009. struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
  1010. regcache_cache_only(i2s->regmap, false);
  1011. return regcache_sync(i2s->regmap);
  1012. }
  1013. #endif /* CONFIG_PM_SLEEP */
  1014. static const struct dev_pm_ops stm32_i2s_pm_ops = {
  1015. SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
  1016. };
  1017. static struct platform_driver stm32_i2s_driver = {
  1018. .driver = {
  1019. .name = "st,stm32-i2s",
  1020. .of_match_table = stm32_i2s_ids,
  1021. .pm = &stm32_i2s_pm_ops,
  1022. },
  1023. .probe = stm32_i2s_probe,
  1024. .remove = stm32_i2s_remove,
  1025. };
  1026. module_platform_driver(stm32_i2s_driver);
  1027. MODULE_DESCRIPTION("STM32 Soc i2s Interface");
  1028. MODULE_AUTHOR("Olivier Moysan, <[email protected]>");
  1029. MODULE_ALIAS("platform:stm32-i2s");
  1030. MODULE_LICENSE("GPL v2");