sprd-mcdt.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2019 Spreadtrum Communications Inc.
  3. #include <linux/errno.h>
  4. #include <linux/interrupt.h>
  5. #include <linux/io.h>
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/mutex.h>
  9. #include <linux/of.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/spinlock.h>
  12. #include "sprd-mcdt.h"
  13. /* MCDT registers definition */
  14. #define MCDT_CH0_TXD 0x0
  15. #define MCDT_CH0_RXD 0x28
  16. #define MCDT_DAC0_WTMK 0x60
  17. #define MCDT_ADC0_WTMK 0x88
  18. #define MCDT_DMA_EN 0xb0
  19. #define MCDT_INT_EN0 0xb4
  20. #define MCDT_INT_EN1 0xb8
  21. #define MCDT_INT_EN2 0xbc
  22. #define MCDT_INT_CLR0 0xc0
  23. #define MCDT_INT_CLR1 0xc4
  24. #define MCDT_INT_CLR2 0xc8
  25. #define MCDT_INT_RAW1 0xcc
  26. #define MCDT_INT_RAW2 0xd0
  27. #define MCDT_INT_RAW3 0xd4
  28. #define MCDT_INT_MSK1 0xd8
  29. #define MCDT_INT_MSK2 0xdc
  30. #define MCDT_INT_MSK3 0xe0
  31. #define MCDT_DAC0_FIFO_ADDR_ST 0xe4
  32. #define MCDT_ADC0_FIFO_ADDR_ST 0xe8
  33. #define MCDT_CH_FIFO_ST0 0x134
  34. #define MCDT_CH_FIFO_ST1 0x138
  35. #define MCDT_CH_FIFO_ST2 0x13c
  36. #define MCDT_INT_MSK_CFG0 0x140
  37. #define MCDT_INT_MSK_CFG1 0x144
  38. #define MCDT_DMA_CFG0 0x148
  39. #define MCDT_FIFO_CLR 0x14c
  40. #define MCDT_DMA_CFG1 0x150
  41. #define MCDT_DMA_CFG2 0x154
  42. #define MCDT_DMA_CFG3 0x158
  43. #define MCDT_DMA_CFG4 0x15c
  44. #define MCDT_DMA_CFG5 0x160
  45. /* Channel water mark definition */
  46. #define MCDT_CH_FIFO_AE_SHIFT 16
  47. #define MCDT_CH_FIFO_AE_MASK GENMASK(24, 16)
  48. #define MCDT_CH_FIFO_AF_MASK GENMASK(8, 0)
  49. /* DMA channel select definition */
  50. #define MCDT_DMA_CH0_SEL_MASK GENMASK(3, 0)
  51. #define MCDT_DMA_CH0_SEL_SHIFT 0
  52. #define MCDT_DMA_CH1_SEL_MASK GENMASK(7, 4)
  53. #define MCDT_DMA_CH1_SEL_SHIFT 4
  54. #define MCDT_DMA_CH2_SEL_MASK GENMASK(11, 8)
  55. #define MCDT_DMA_CH2_SEL_SHIFT 8
  56. #define MCDT_DMA_CH3_SEL_MASK GENMASK(15, 12)
  57. #define MCDT_DMA_CH3_SEL_SHIFT 12
  58. #define MCDT_DMA_CH4_SEL_MASK GENMASK(19, 16)
  59. #define MCDT_DMA_CH4_SEL_SHIFT 16
  60. #define MCDT_DAC_DMA_SHIFT 16
  61. /* DMA channel ACK select definition */
  62. #define MCDT_DMA_ACK_SEL_MASK GENMASK(3, 0)
  63. /* Channel FIFO definition */
  64. #define MCDT_CH_FIFO_ADDR_SHIFT 16
  65. #define MCDT_CH_FIFO_ADDR_MASK GENMASK(9, 0)
  66. #define MCDT_ADC_FIFO_SHIFT 16
  67. #define MCDT_FIFO_LENGTH 512
  68. #define MCDT_ADC_CHANNEL_NUM 10
  69. #define MCDT_DAC_CHANNEL_NUM 10
  70. #define MCDT_CHANNEL_NUM (MCDT_ADC_CHANNEL_NUM + MCDT_DAC_CHANNEL_NUM)
  71. enum sprd_mcdt_fifo_int {
  72. MCDT_ADC_FIFO_AE_INT,
  73. MCDT_ADC_FIFO_AF_INT,
  74. MCDT_DAC_FIFO_AE_INT,
  75. MCDT_DAC_FIFO_AF_INT,
  76. MCDT_ADC_FIFO_OV_INT,
  77. MCDT_DAC_FIFO_OV_INT
  78. };
  79. enum sprd_mcdt_fifo_sts {
  80. MCDT_ADC_FIFO_REAL_FULL,
  81. MCDT_ADC_FIFO_REAL_EMPTY,
  82. MCDT_ADC_FIFO_AF,
  83. MCDT_ADC_FIFO_AE,
  84. MCDT_DAC_FIFO_REAL_FULL,
  85. MCDT_DAC_FIFO_REAL_EMPTY,
  86. MCDT_DAC_FIFO_AF,
  87. MCDT_DAC_FIFO_AE
  88. };
  89. struct sprd_mcdt_dev {
  90. struct device *dev;
  91. void __iomem *base;
  92. spinlock_t lock;
  93. struct sprd_mcdt_chan chan[MCDT_CHANNEL_NUM];
  94. };
  95. static LIST_HEAD(sprd_mcdt_chan_list);
  96. static DEFINE_MUTEX(sprd_mcdt_list_mutex);
  97. static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val,
  98. u32 mask)
  99. {
  100. u32 orig = readl_relaxed(mcdt->base + reg);
  101. u32 tmp;
  102. tmp = (orig & ~mask) | val;
  103. writel_relaxed(tmp, mcdt->base + reg);
  104. }
  105. static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,
  106. u32 full, u32 empty)
  107. {
  108. u32 reg = MCDT_DAC0_WTMK + channel * 4;
  109. u32 water_mark =
  110. (empty << MCDT_CH_FIFO_AE_SHIFT) & MCDT_CH_FIFO_AE_MASK;
  111. water_mark |= full & MCDT_CH_FIFO_AF_MASK;
  112. sprd_mcdt_update(mcdt, reg, water_mark,
  113. MCDT_CH_FIFO_AE_MASK | MCDT_CH_FIFO_AF_MASK);
  114. }
  115. static void sprd_mcdt_adc_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,
  116. u32 full, u32 empty)
  117. {
  118. u32 reg = MCDT_ADC0_WTMK + channel * 4;
  119. u32 water_mark =
  120. (empty << MCDT_CH_FIFO_AE_SHIFT) & MCDT_CH_FIFO_AE_MASK;
  121. water_mark |= full & MCDT_CH_FIFO_AF_MASK;
  122. sprd_mcdt_update(mcdt, reg, water_mark,
  123. MCDT_CH_FIFO_AE_MASK | MCDT_CH_FIFO_AF_MASK);
  124. }
  125. static void sprd_mcdt_dac_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,
  126. bool enable)
  127. {
  128. u32 shift = MCDT_DAC_DMA_SHIFT + channel;
  129. if (enable)
  130. sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift));
  131. else
  132. sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift));
  133. }
  134. static void sprd_mcdt_adc_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,
  135. bool enable)
  136. {
  137. if (enable)
  138. sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(channel), BIT(channel));
  139. else
  140. sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(channel));
  141. }
  142. static void sprd_mcdt_ap_int_enable(struct sprd_mcdt_dev *mcdt, u8 channel,
  143. bool enable)
  144. {
  145. if (enable)
  146. sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, BIT(channel),
  147. BIT(channel));
  148. else
  149. sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, 0, BIT(channel));
  150. }
  151. static void sprd_mcdt_dac_write_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,
  152. u32 val)
  153. {
  154. u32 reg = MCDT_CH0_TXD + channel * 4;
  155. writel_relaxed(val, mcdt->base + reg);
  156. }
  157. static void sprd_mcdt_adc_read_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,
  158. u32 *val)
  159. {
  160. u32 reg = MCDT_CH0_RXD + channel * 4;
  161. *val = readl_relaxed(mcdt->base + reg);
  162. }
  163. static void sprd_mcdt_dac_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,
  164. enum sprd_mcdt_dma_chan dma_chan)
  165. {
  166. switch (dma_chan) {
  167. case SPRD_MCDT_DMA_CH0:
  168. sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
  169. channel << MCDT_DMA_CH0_SEL_SHIFT,
  170. MCDT_DMA_CH0_SEL_MASK);
  171. break;
  172. case SPRD_MCDT_DMA_CH1:
  173. sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
  174. channel << MCDT_DMA_CH1_SEL_SHIFT,
  175. MCDT_DMA_CH1_SEL_MASK);
  176. break;
  177. case SPRD_MCDT_DMA_CH2:
  178. sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
  179. channel << MCDT_DMA_CH2_SEL_SHIFT,
  180. MCDT_DMA_CH2_SEL_MASK);
  181. break;
  182. case SPRD_MCDT_DMA_CH3:
  183. sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
  184. channel << MCDT_DMA_CH3_SEL_SHIFT,
  185. MCDT_DMA_CH3_SEL_MASK);
  186. break;
  187. case SPRD_MCDT_DMA_CH4:
  188. sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
  189. channel << MCDT_DMA_CH4_SEL_SHIFT,
  190. MCDT_DMA_CH4_SEL_MASK);
  191. break;
  192. }
  193. }
  194. static void sprd_mcdt_adc_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,
  195. enum sprd_mcdt_dma_chan dma_chan)
  196. {
  197. switch (dma_chan) {
  198. case SPRD_MCDT_DMA_CH0:
  199. sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
  200. channel << MCDT_DMA_CH0_SEL_SHIFT,
  201. MCDT_DMA_CH0_SEL_MASK);
  202. break;
  203. case SPRD_MCDT_DMA_CH1:
  204. sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
  205. channel << MCDT_DMA_CH1_SEL_SHIFT,
  206. MCDT_DMA_CH1_SEL_MASK);
  207. break;
  208. case SPRD_MCDT_DMA_CH2:
  209. sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
  210. channel << MCDT_DMA_CH2_SEL_SHIFT,
  211. MCDT_DMA_CH2_SEL_MASK);
  212. break;
  213. case SPRD_MCDT_DMA_CH3:
  214. sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
  215. channel << MCDT_DMA_CH3_SEL_SHIFT,
  216. MCDT_DMA_CH3_SEL_MASK);
  217. break;
  218. case SPRD_MCDT_DMA_CH4:
  219. sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
  220. channel << MCDT_DMA_CH4_SEL_SHIFT,
  221. MCDT_DMA_CH4_SEL_MASK);
  222. break;
  223. }
  224. }
  225. static u32 sprd_mcdt_dma_ack_shift(u8 channel)
  226. {
  227. switch (channel) {
  228. default:
  229. case 0:
  230. case 8:
  231. return 0;
  232. case 1:
  233. case 9:
  234. return 4;
  235. case 2:
  236. return 8;
  237. case 3:
  238. return 12;
  239. case 4:
  240. return 16;
  241. case 5:
  242. return 20;
  243. case 6:
  244. return 24;
  245. case 7:
  246. return 28;
  247. }
  248. }
  249. static void sprd_mcdt_dac_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,
  250. enum sprd_mcdt_dma_chan dma_chan)
  251. {
  252. u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan;
  253. switch (channel) {
  254. case 0 ... 7:
  255. reg = MCDT_DMA_CFG2;
  256. break;
  257. case 8 ... 9:
  258. reg = MCDT_DMA_CFG3;
  259. break;
  260. default:
  261. return;
  262. }
  263. sprd_mcdt_update(mcdt, reg, ack << shift,
  264. MCDT_DMA_ACK_SEL_MASK << shift);
  265. }
  266. static void sprd_mcdt_adc_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,
  267. enum sprd_mcdt_dma_chan dma_chan)
  268. {
  269. u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan;
  270. switch (channel) {
  271. case 0 ... 7:
  272. reg = MCDT_DMA_CFG4;
  273. break;
  274. case 8 ... 9:
  275. reg = MCDT_DMA_CFG5;
  276. break;
  277. default:
  278. return;
  279. }
  280. sprd_mcdt_update(mcdt, reg, ack << shift,
  281. MCDT_DMA_ACK_SEL_MASK << shift);
  282. }
  283. static bool sprd_mcdt_chan_fifo_sts(struct sprd_mcdt_dev *mcdt, u8 channel,
  284. enum sprd_mcdt_fifo_sts fifo_sts)
  285. {
  286. u32 reg, shift;
  287. switch (channel) {
  288. case 0 ... 3:
  289. reg = MCDT_CH_FIFO_ST0;
  290. break;
  291. case 4 ... 7:
  292. reg = MCDT_CH_FIFO_ST1;
  293. break;
  294. case 8 ... 9:
  295. reg = MCDT_CH_FIFO_ST2;
  296. break;
  297. default:
  298. return false;
  299. }
  300. switch (channel) {
  301. case 0:
  302. case 4:
  303. case 8:
  304. shift = fifo_sts;
  305. break;
  306. case 1:
  307. case 5:
  308. case 9:
  309. shift = 8 + fifo_sts;
  310. break;
  311. case 2:
  312. case 6:
  313. shift = 16 + fifo_sts;
  314. break;
  315. case 3:
  316. case 7:
  317. shift = 24 + fifo_sts;
  318. break;
  319. default:
  320. return false;
  321. }
  322. return !!(readl_relaxed(mcdt->base + reg) & BIT(shift));
  323. }
  324. static void sprd_mcdt_dac_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)
  325. {
  326. sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(channel), BIT(channel));
  327. }
  328. static void sprd_mcdt_adc_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)
  329. {
  330. u32 shift = MCDT_ADC_FIFO_SHIFT + channel;
  331. sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(shift), BIT(shift));
  332. }
  333. static u32 sprd_mcdt_dac_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)
  334. {
  335. u32 reg = MCDT_DAC0_FIFO_ADDR_ST + channel * 8;
  336. u32 r_addr = (readl_relaxed(mcdt->base + reg) >>
  337. MCDT_CH_FIFO_ADDR_SHIFT) & MCDT_CH_FIFO_ADDR_MASK;
  338. u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK;
  339. if (w_addr >= r_addr)
  340. return 4 * (MCDT_FIFO_LENGTH - w_addr + r_addr);
  341. else
  342. return 4 * (r_addr - w_addr);
  343. }
  344. static u32 sprd_mcdt_adc_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)
  345. {
  346. u32 reg = MCDT_ADC0_FIFO_ADDR_ST + channel * 8;
  347. u32 r_addr = (readl_relaxed(mcdt->base + reg) >>
  348. MCDT_CH_FIFO_ADDR_SHIFT) & MCDT_CH_FIFO_ADDR_MASK;
  349. u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK;
  350. if (w_addr >= r_addr)
  351. return 4 * (w_addr - r_addr);
  352. else
  353. return 4 * (MCDT_FIFO_LENGTH - r_addr + w_addr);
  354. }
  355. static u32 sprd_mcdt_int_type_shift(u8 channel,
  356. enum sprd_mcdt_fifo_int int_type)
  357. {
  358. switch (channel) {
  359. case 0:
  360. case 4:
  361. case 8:
  362. return int_type;
  363. case 1:
  364. case 5:
  365. case 9:
  366. return 8 + int_type;
  367. case 2:
  368. case 6:
  369. return 16 + int_type;
  370. case 3:
  371. case 7:
  372. return 24 + int_type;
  373. default:
  374. return 0;
  375. }
  376. }
  377. static void sprd_mcdt_chan_int_en(struct sprd_mcdt_dev *mcdt, u8 channel,
  378. enum sprd_mcdt_fifo_int int_type, bool enable)
  379. {
  380. u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);
  381. switch (channel) {
  382. case 0 ... 3:
  383. reg = MCDT_INT_EN0;
  384. break;
  385. case 4 ... 7:
  386. reg = MCDT_INT_EN1;
  387. break;
  388. case 8 ... 9:
  389. reg = MCDT_INT_EN2;
  390. break;
  391. default:
  392. return;
  393. }
  394. if (enable)
  395. sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift));
  396. else
  397. sprd_mcdt_update(mcdt, reg, 0, BIT(shift));
  398. }
  399. static void sprd_mcdt_chan_int_clear(struct sprd_mcdt_dev *mcdt, u8 channel,
  400. enum sprd_mcdt_fifo_int int_type)
  401. {
  402. u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);
  403. switch (channel) {
  404. case 0 ... 3:
  405. reg = MCDT_INT_CLR0;
  406. break;
  407. case 4 ... 7:
  408. reg = MCDT_INT_CLR1;
  409. break;
  410. case 8 ... 9:
  411. reg = MCDT_INT_CLR2;
  412. break;
  413. default:
  414. return;
  415. }
  416. sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift));
  417. }
  418. static bool sprd_mcdt_chan_int_sts(struct sprd_mcdt_dev *mcdt, u8 channel,
  419. enum sprd_mcdt_fifo_int int_type)
  420. {
  421. u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type);
  422. switch (channel) {
  423. case 0 ... 3:
  424. reg = MCDT_INT_MSK1;
  425. break;
  426. case 4 ... 7:
  427. reg = MCDT_INT_MSK2;
  428. break;
  429. case 8 ... 9:
  430. reg = MCDT_INT_MSK3;
  431. break;
  432. default:
  433. return false;
  434. }
  435. return !!(readl_relaxed(mcdt->base + reg) & BIT(shift));
  436. }
  437. static irqreturn_t sprd_mcdt_irq_handler(int irq, void *dev_id)
  438. {
  439. struct sprd_mcdt_dev *mcdt = (struct sprd_mcdt_dev *)dev_id;
  440. int i;
  441. spin_lock(&mcdt->lock);
  442. for (i = 0; i < MCDT_ADC_CHANNEL_NUM; i++) {
  443. if (sprd_mcdt_chan_int_sts(mcdt, i, MCDT_ADC_FIFO_AF_INT)) {
  444. struct sprd_mcdt_chan *chan = &mcdt->chan[i];
  445. sprd_mcdt_chan_int_clear(mcdt, i, MCDT_ADC_FIFO_AF_INT);
  446. if (chan->cb)
  447. chan->cb->notify(chan->cb->data);
  448. }
  449. }
  450. for (i = 0; i < MCDT_DAC_CHANNEL_NUM; i++) {
  451. if (sprd_mcdt_chan_int_sts(mcdt, i, MCDT_DAC_FIFO_AE_INT)) {
  452. struct sprd_mcdt_chan *chan =
  453. &mcdt->chan[i + MCDT_ADC_CHANNEL_NUM];
  454. sprd_mcdt_chan_int_clear(mcdt, i, MCDT_DAC_FIFO_AE_INT);
  455. if (chan->cb)
  456. chan->cb->notify(chan->cb->data);
  457. }
  458. }
  459. spin_unlock(&mcdt->lock);
  460. return IRQ_HANDLED;
  461. }
  462. /**
  463. * sprd_mcdt_chan_write - write data to the MCDT channel's fifo
  464. * @chan: the MCDT channel
  465. * @tx_buf: send buffer
  466. * @size: data size
  467. *
  468. * Note: We can not write data to the channel fifo when enabling the DMA mode,
  469. * otherwise the channel fifo data will be invalid.
  470. *
  471. * If there are not enough space of the channel fifo, it will return errors
  472. * to users.
  473. *
  474. * Returns 0 on success, or an appropriate error code on failure.
  475. */
  476. int sprd_mcdt_chan_write(struct sprd_mcdt_chan *chan, char *tx_buf, u32 size)
  477. {
  478. struct sprd_mcdt_dev *mcdt = chan->mcdt;
  479. unsigned long flags;
  480. int avail, i = 0, words = size / 4;
  481. u32 *buf = (u32 *)tx_buf;
  482. spin_lock_irqsave(&mcdt->lock, flags);
  483. if (chan->dma_enable) {
  484. dev_err(mcdt->dev,
  485. "Can not write data when DMA mode enabled\n");
  486. spin_unlock_irqrestore(&mcdt->lock, flags);
  487. return -EINVAL;
  488. }
  489. if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_DAC_FIFO_REAL_FULL)) {
  490. dev_err(mcdt->dev, "Channel fifo is full now\n");
  491. spin_unlock_irqrestore(&mcdt->lock, flags);
  492. return -EBUSY;
  493. }
  494. avail = sprd_mcdt_dac_fifo_avail(mcdt, chan->id);
  495. if (size > avail) {
  496. dev_err(mcdt->dev,
  497. "Data size is larger than the available fifo size\n");
  498. spin_unlock_irqrestore(&mcdt->lock, flags);
  499. return -EBUSY;
  500. }
  501. while (i++ < words)
  502. sprd_mcdt_dac_write_fifo(mcdt, chan->id, *buf++);
  503. spin_unlock_irqrestore(&mcdt->lock, flags);
  504. return 0;
  505. }
  506. EXPORT_SYMBOL_GPL(sprd_mcdt_chan_write);
  507. /**
  508. * sprd_mcdt_chan_read - read data from the MCDT channel's fifo
  509. * @chan: the MCDT channel
  510. * @rx_buf: receive buffer
  511. * @size: data size
  512. *
  513. * Note: We can not read data from the channel fifo when enabling the DMA mode,
  514. * otherwise the reading data will be invalid.
  515. *
  516. * Usually user need start to read data once receiving the fifo full interrupt.
  517. *
  518. * Returns data size of reading successfully, or an error code on failure.
  519. */
  520. int sprd_mcdt_chan_read(struct sprd_mcdt_chan *chan, char *rx_buf, u32 size)
  521. {
  522. struct sprd_mcdt_dev *mcdt = chan->mcdt;
  523. unsigned long flags;
  524. int i = 0, avail, words = size / 4;
  525. u32 *buf = (u32 *)rx_buf;
  526. spin_lock_irqsave(&mcdt->lock, flags);
  527. if (chan->dma_enable) {
  528. dev_err(mcdt->dev, "Can not read data when DMA mode enabled\n");
  529. spin_unlock_irqrestore(&mcdt->lock, flags);
  530. return -EINVAL;
  531. }
  532. if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_ADC_FIFO_REAL_EMPTY)) {
  533. dev_err(mcdt->dev, "Channel fifo is empty\n");
  534. spin_unlock_irqrestore(&mcdt->lock, flags);
  535. return -EBUSY;
  536. }
  537. avail = sprd_mcdt_adc_fifo_avail(mcdt, chan->id);
  538. if (size > avail)
  539. words = avail / 4;
  540. while (i++ < words)
  541. sprd_mcdt_adc_read_fifo(mcdt, chan->id, buf++);
  542. spin_unlock_irqrestore(&mcdt->lock, flags);
  543. return words * 4;
  544. }
  545. EXPORT_SYMBOL_GPL(sprd_mcdt_chan_read);
  546. /**
  547. * sprd_mcdt_chan_int_enable - enable the interrupt mode for the MCDT channel
  548. * @chan: the MCDT channel
  549. * @water_mark: water mark to trigger a interrupt
  550. * @cb: callback when a interrupt happened
  551. *
  552. * Now it only can enable fifo almost full interrupt for ADC channel and fifo
  553. * almost empty interrupt for DAC channel. Morevoer for interrupt mode, user
  554. * should use sprd_mcdt_chan_read() or sprd_mcdt_chan_write() to read or write
  555. * data manually.
  556. *
  557. * For ADC channel, user can start to read data once receiving one fifo full
  558. * interrupt. For DAC channel, user can start to write data once receiving one
  559. * fifo empty interrupt or just call sprd_mcdt_chan_write() to write data
  560. * directly.
  561. *
  562. * Returns 0 on success, or an error code on failure.
  563. */
  564. int sprd_mcdt_chan_int_enable(struct sprd_mcdt_chan *chan, u32 water_mark,
  565. struct sprd_mcdt_chan_callback *cb)
  566. {
  567. struct sprd_mcdt_dev *mcdt = chan->mcdt;
  568. unsigned long flags;
  569. int ret = 0;
  570. spin_lock_irqsave(&mcdt->lock, flags);
  571. if (chan->dma_enable || chan->int_enable) {
  572. dev_err(mcdt->dev, "Failed to set interrupt mode.\n");
  573. spin_unlock_irqrestore(&mcdt->lock, flags);
  574. return -EINVAL;
  575. }
  576. switch (chan->type) {
  577. case SPRD_MCDT_ADC_CHAN:
  578. sprd_mcdt_adc_fifo_clear(mcdt, chan->id);
  579. sprd_mcdt_adc_set_watermark(mcdt, chan->id, water_mark,
  580. MCDT_FIFO_LENGTH - 1);
  581. sprd_mcdt_chan_int_en(mcdt, chan->id,
  582. MCDT_ADC_FIFO_AF_INT, true);
  583. sprd_mcdt_ap_int_enable(mcdt, chan->id, true);
  584. break;
  585. case SPRD_MCDT_DAC_CHAN:
  586. sprd_mcdt_dac_fifo_clear(mcdt, chan->id);
  587. sprd_mcdt_dac_set_watermark(mcdt, chan->id,
  588. MCDT_FIFO_LENGTH - 1, water_mark);
  589. sprd_mcdt_chan_int_en(mcdt, chan->id,
  590. MCDT_DAC_FIFO_AE_INT, true);
  591. sprd_mcdt_ap_int_enable(mcdt, chan->id, true);
  592. break;
  593. default:
  594. dev_err(mcdt->dev, "Unsupported channel type\n");
  595. ret = -EINVAL;
  596. }
  597. if (!ret) {
  598. chan->cb = cb;
  599. chan->int_enable = true;
  600. }
  601. spin_unlock_irqrestore(&mcdt->lock, flags);
  602. return ret;
  603. }
  604. EXPORT_SYMBOL_GPL(sprd_mcdt_chan_int_enable);
  605. /**
  606. * sprd_mcdt_chan_int_disable - disable the interrupt mode for the MCDT channel
  607. * @chan: the MCDT channel
  608. */
  609. void sprd_mcdt_chan_int_disable(struct sprd_mcdt_chan *chan)
  610. {
  611. struct sprd_mcdt_dev *mcdt = chan->mcdt;
  612. unsigned long flags;
  613. spin_lock_irqsave(&mcdt->lock, flags);
  614. if (!chan->int_enable) {
  615. spin_unlock_irqrestore(&mcdt->lock, flags);
  616. return;
  617. }
  618. switch (chan->type) {
  619. case SPRD_MCDT_ADC_CHAN:
  620. sprd_mcdt_chan_int_en(mcdt, chan->id,
  621. MCDT_ADC_FIFO_AF_INT, false);
  622. sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_ADC_FIFO_AF_INT);
  623. sprd_mcdt_ap_int_enable(mcdt, chan->id, false);
  624. break;
  625. case SPRD_MCDT_DAC_CHAN:
  626. sprd_mcdt_chan_int_en(mcdt, chan->id,
  627. MCDT_DAC_FIFO_AE_INT, false);
  628. sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_DAC_FIFO_AE_INT);
  629. sprd_mcdt_ap_int_enable(mcdt, chan->id, false);
  630. break;
  631. default:
  632. break;
  633. }
  634. chan->int_enable = false;
  635. spin_unlock_irqrestore(&mcdt->lock, flags);
  636. }
  637. EXPORT_SYMBOL_GPL(sprd_mcdt_chan_int_disable);
  638. /**
  639. * sprd_mcdt_chan_dma_enable - enable the DMA mode for the MCDT channel
  640. * @chan: the MCDT channel
  641. * @dma_chan: specify which DMA channel will be used for this MCDT channel
  642. * @water_mark: water mark to trigger a DMA request
  643. *
  644. * Enable the DMA mode for the MCDT channel, that means we can use DMA to
  645. * transfer data to the channel fifo and do not need reading/writing data
  646. * manually.
  647. *
  648. * Returns 0 on success, or an error code on failure.
  649. */
  650. int sprd_mcdt_chan_dma_enable(struct sprd_mcdt_chan *chan,
  651. enum sprd_mcdt_dma_chan dma_chan,
  652. u32 water_mark)
  653. {
  654. struct sprd_mcdt_dev *mcdt = chan->mcdt;
  655. unsigned long flags;
  656. int ret = 0;
  657. spin_lock_irqsave(&mcdt->lock, flags);
  658. if (chan->dma_enable || chan->int_enable ||
  659. dma_chan > SPRD_MCDT_DMA_CH4) {
  660. dev_err(mcdt->dev, "Failed to set DMA mode\n");
  661. spin_unlock_irqrestore(&mcdt->lock, flags);
  662. return -EINVAL;
  663. }
  664. switch (chan->type) {
  665. case SPRD_MCDT_ADC_CHAN:
  666. sprd_mcdt_adc_fifo_clear(mcdt, chan->id);
  667. sprd_mcdt_adc_set_watermark(mcdt, chan->id,
  668. water_mark, MCDT_FIFO_LENGTH - 1);
  669. sprd_mcdt_adc_dma_enable(mcdt, chan->id, true);
  670. sprd_mcdt_adc_dma_chn_select(mcdt, chan->id, dma_chan);
  671. sprd_mcdt_adc_dma_ack_select(mcdt, chan->id, dma_chan);
  672. break;
  673. case SPRD_MCDT_DAC_CHAN:
  674. sprd_mcdt_dac_fifo_clear(mcdt, chan->id);
  675. sprd_mcdt_dac_set_watermark(mcdt, chan->id,
  676. MCDT_FIFO_LENGTH - 1, water_mark);
  677. sprd_mcdt_dac_dma_enable(mcdt, chan->id, true);
  678. sprd_mcdt_dac_dma_chn_select(mcdt, chan->id, dma_chan);
  679. sprd_mcdt_dac_dma_ack_select(mcdt, chan->id, dma_chan);
  680. break;
  681. default:
  682. dev_err(mcdt->dev, "Unsupported channel type\n");
  683. ret = -EINVAL;
  684. }
  685. if (!ret)
  686. chan->dma_enable = true;
  687. spin_unlock_irqrestore(&mcdt->lock, flags);
  688. return ret;
  689. }
  690. EXPORT_SYMBOL_GPL(sprd_mcdt_chan_dma_enable);
  691. /**
  692. * sprd_mcdt_chan_dma_disable - disable the DMA mode for the MCDT channel
  693. * @chan: the MCDT channel
  694. */
  695. void sprd_mcdt_chan_dma_disable(struct sprd_mcdt_chan *chan)
  696. {
  697. struct sprd_mcdt_dev *mcdt = chan->mcdt;
  698. unsigned long flags;
  699. spin_lock_irqsave(&mcdt->lock, flags);
  700. if (!chan->dma_enable) {
  701. spin_unlock_irqrestore(&mcdt->lock, flags);
  702. return;
  703. }
  704. switch (chan->type) {
  705. case SPRD_MCDT_ADC_CHAN:
  706. sprd_mcdt_adc_dma_enable(mcdt, chan->id, false);
  707. sprd_mcdt_adc_fifo_clear(mcdt, chan->id);
  708. break;
  709. case SPRD_MCDT_DAC_CHAN:
  710. sprd_mcdt_dac_dma_enable(mcdt, chan->id, false);
  711. sprd_mcdt_dac_fifo_clear(mcdt, chan->id);
  712. break;
  713. default:
  714. break;
  715. }
  716. chan->dma_enable = false;
  717. spin_unlock_irqrestore(&mcdt->lock, flags);
  718. }
  719. EXPORT_SYMBOL_GPL(sprd_mcdt_chan_dma_disable);
  720. /**
  721. * sprd_mcdt_request_chan - request one MCDT channel
  722. * @channel: channel id
  723. * @type: channel type, it can be one ADC channel or DAC channel
  724. *
  725. * Rreturn NULL if no available channel.
  726. */
  727. struct sprd_mcdt_chan *sprd_mcdt_request_chan(u8 channel,
  728. enum sprd_mcdt_channel_type type)
  729. {
  730. struct sprd_mcdt_chan *temp;
  731. mutex_lock(&sprd_mcdt_list_mutex);
  732. list_for_each_entry(temp, &sprd_mcdt_chan_list, list) {
  733. if (temp->type == type && temp->id == channel) {
  734. list_del_init(&temp->list);
  735. break;
  736. }
  737. }
  738. if (list_entry_is_head(temp, &sprd_mcdt_chan_list, list))
  739. temp = NULL;
  740. mutex_unlock(&sprd_mcdt_list_mutex);
  741. return temp;
  742. }
  743. EXPORT_SYMBOL_GPL(sprd_mcdt_request_chan);
  744. /**
  745. * sprd_mcdt_free_chan - free one MCDT channel
  746. * @chan: the channel to be freed
  747. */
  748. void sprd_mcdt_free_chan(struct sprd_mcdt_chan *chan)
  749. {
  750. struct sprd_mcdt_chan *temp;
  751. sprd_mcdt_chan_dma_disable(chan);
  752. sprd_mcdt_chan_int_disable(chan);
  753. mutex_lock(&sprd_mcdt_list_mutex);
  754. list_for_each_entry(temp, &sprd_mcdt_chan_list, list) {
  755. if (temp == chan) {
  756. mutex_unlock(&sprd_mcdt_list_mutex);
  757. return;
  758. }
  759. }
  760. list_add_tail(&chan->list, &sprd_mcdt_chan_list);
  761. mutex_unlock(&sprd_mcdt_list_mutex);
  762. }
  763. EXPORT_SYMBOL_GPL(sprd_mcdt_free_chan);
  764. static void sprd_mcdt_init_chans(struct sprd_mcdt_dev *mcdt,
  765. struct resource *res)
  766. {
  767. int i;
  768. for (i = 0; i < MCDT_CHANNEL_NUM; i++) {
  769. struct sprd_mcdt_chan *chan = &mcdt->chan[i];
  770. if (i < MCDT_ADC_CHANNEL_NUM) {
  771. chan->id = i;
  772. chan->type = SPRD_MCDT_ADC_CHAN;
  773. chan->fifo_phys = res->start + MCDT_CH0_RXD + i * 4;
  774. } else {
  775. chan->id = i - MCDT_ADC_CHANNEL_NUM;
  776. chan->type = SPRD_MCDT_DAC_CHAN;
  777. chan->fifo_phys = res->start + MCDT_CH0_TXD +
  778. (i - MCDT_ADC_CHANNEL_NUM) * 4;
  779. }
  780. chan->mcdt = mcdt;
  781. INIT_LIST_HEAD(&chan->list);
  782. mutex_lock(&sprd_mcdt_list_mutex);
  783. list_add_tail(&chan->list, &sprd_mcdt_chan_list);
  784. mutex_unlock(&sprd_mcdt_list_mutex);
  785. }
  786. }
  787. static int sprd_mcdt_probe(struct platform_device *pdev)
  788. {
  789. struct sprd_mcdt_dev *mcdt;
  790. struct resource *res;
  791. int ret, irq;
  792. mcdt = devm_kzalloc(&pdev->dev, sizeof(*mcdt), GFP_KERNEL);
  793. if (!mcdt)
  794. return -ENOMEM;
  795. mcdt->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  796. if (IS_ERR(mcdt->base))
  797. return PTR_ERR(mcdt->base);
  798. mcdt->dev = &pdev->dev;
  799. spin_lock_init(&mcdt->lock);
  800. platform_set_drvdata(pdev, mcdt);
  801. irq = platform_get_irq(pdev, 0);
  802. if (irq < 0)
  803. return irq;
  804. ret = devm_request_irq(&pdev->dev, irq, sprd_mcdt_irq_handler,
  805. 0, "sprd-mcdt", mcdt);
  806. if (ret) {
  807. dev_err(&pdev->dev, "Failed to request MCDT IRQ\n");
  808. return ret;
  809. }
  810. sprd_mcdt_init_chans(mcdt, res);
  811. return 0;
  812. }
  813. static int sprd_mcdt_remove(struct platform_device *pdev)
  814. {
  815. struct sprd_mcdt_chan *chan, *temp;
  816. mutex_lock(&sprd_mcdt_list_mutex);
  817. list_for_each_entry_safe(chan, temp, &sprd_mcdt_chan_list, list)
  818. list_del(&chan->list);
  819. mutex_unlock(&sprd_mcdt_list_mutex);
  820. return 0;
  821. }
  822. static const struct of_device_id sprd_mcdt_of_match[] = {
  823. { .compatible = "sprd,sc9860-mcdt", },
  824. { }
  825. };
  826. MODULE_DEVICE_TABLE(of, sprd_mcdt_of_match);
  827. static struct platform_driver sprd_mcdt_driver = {
  828. .probe = sprd_mcdt_probe,
  829. .remove = sprd_mcdt_remove,
  830. .driver = {
  831. .name = "sprd-mcdt",
  832. .of_match_table = sprd_mcdt_of_match,
  833. },
  834. };
  835. module_platform_driver(sprd_mcdt_driver);
  836. MODULE_DESCRIPTION("Spreadtrum Multi-Channel Data Transfer Driver");
  837. MODULE_LICENSE("GPL v2");