ipc4-mtrace.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright(c) 2022 Intel Corporation. All rights reserved.
  4. #include <linux/debugfs.h>
  5. #include <linux/sched/signal.h>
  6. #include <sound/sof/ipc4/header.h>
  7. #include "sof-priv.h"
  8. #include "ipc4-priv.h"
  9. /*
  10. * debug info window is organized in 16 (equal sized) pages:
  11. *
  12. * ------------------------
  13. * | Page0 - descriptors |
  14. * ------------------------
  15. * | Page1 - slot0 |
  16. * ------------------------
  17. * | Page2 - slot1 |
  18. * ------------------------
  19. * | ... |
  20. * ------------------------
  21. * | Page14 - slot13 |
  22. * ------------------------
  23. * | Page15 - slot14 |
  24. * ------------------------
  25. *
  26. * The slot size == page size
  27. *
  28. * The first page contains descriptors for the remaining 15 cores
  29. * The slot descriptor is:
  30. * u32 res_id;
  31. * u32 type;
  32. * u32 vma;
  33. *
  34. * Log buffer slots have the following layout:
  35. * u32 host_read_ptr;
  36. * u32 dsp_write_ptr;
  37. * u8 buffer[];
  38. *
  39. * The two pointers are offsets within the buffer.
  40. */
  41. #define SOF_MTRACE_DESCRIPTOR_SIZE 12 /* 3 x u32 */
  42. #define FW_EPOCH_DELTA 11644473600LL
  43. #define INVALID_SLOT_OFFSET 0xffffffff
  44. #define MAX_ALLOWED_LIBRARIES 16
  45. #define MAX_MTRACE_SLOTS 15
  46. #define SOF_MTRACE_PAGE_SIZE 0x1000
  47. #define SOF_MTRACE_SLOT_SIZE SOF_MTRACE_PAGE_SIZE
  48. /* debug log slot types */
  49. #define SOF_MTRACE_SLOT_UNUSED 0x00000000
  50. #define SOF_MTRACE_SLOT_CRITICAL_LOG 0x54524300 /* byte 0: core ID */
  51. #define SOF_MTRACE_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */
  52. #define SOF_MTRACE_SLOT_GDB_STUB 0x42444700
  53. #define SOF_MTRACE_SLOT_TELEMETRY 0x4c455400
  54. #define SOF_MTRACE_SLOT_BROKEN 0x44414544
  55. /* for debug and critical types */
  56. #define SOF_MTRACE_SLOT_CORE_MASK GENMASK(7, 0)
  57. #define SOF_MTRACE_SLOT_TYPE_MASK GENMASK(31, 8)
  58. #define DEFAULT_AGING_TIMER_PERIOD_MS 0x100
  59. #define DEFAULT_FIFO_FULL_TIMER_PERIOD_MS 0x1000
  60. /* ipc4 log level and source definitions for logs_priorities_mask */
  61. #define SOF_MTRACE_LOG_LEVEL_CRITICAL BIT(0)
  62. #define SOF_MTRACE_LOG_LEVEL_ERROR BIT(1)
  63. #define SOF_MTRACE_LOG_LEVEL_WARNING BIT(2)
  64. #define SOF_MTRACE_LOG_LEVEL_INFO BIT(3)
  65. #define SOF_MTRACE_LOG_LEVEL_VERBOSE BIT(4)
  66. #define SOF_MTRACE_LOG_SOURCE_INFRA BIT(5) /* log source 0 */
  67. #define SOF_MTRACE_LOG_SOURCE_HAL BIT(6)
  68. #define SOF_MTRACE_LOG_SOURCE_MODULE BIT(7)
  69. #define SOF_MTRACE_LOG_SOURCE_AUDIO BIT(8)
  70. #define SOF_MTRACE_LOG_SOURCE_SCHEDULER BIT(9)
  71. #define SOF_MTRACE_LOG_SOURCE_ULP_INFRA BIT(10)
  72. #define SOF_MTRACE_LOG_SOURCE_ULP_MODULE BIT(11)
  73. #define SOF_MTRACE_LOG_SOURCE_VISION BIT(12) /* log source 7 */
  74. #define DEFAULT_LOGS_PRIORITIES_MASK (SOF_MTRACE_LOG_LEVEL_CRITICAL | \
  75. SOF_MTRACE_LOG_LEVEL_ERROR | \
  76. SOF_MTRACE_LOG_LEVEL_WARNING | \
  77. SOF_MTRACE_LOG_LEVEL_INFO | \
  78. SOF_MTRACE_LOG_SOURCE_INFRA | \
  79. SOF_MTRACE_LOG_SOURCE_HAL | \
  80. SOF_MTRACE_LOG_SOURCE_MODULE | \
  81. SOF_MTRACE_LOG_SOURCE_AUDIO)
  82. struct sof_log_state_info {
  83. u32 aging_timer_period;
  84. u32 fifo_full_timer_period;
  85. u32 enable;
  86. u32 logs_priorities_mask[MAX_ALLOWED_LIBRARIES];
  87. } __packed;
  88. enum sof_mtrace_state {
  89. SOF_MTRACE_DISABLED,
  90. SOF_MTRACE_INITIALIZING,
  91. SOF_MTRACE_ENABLED,
  92. };
  93. struct sof_mtrace_core_data {
  94. struct snd_sof_dev *sdev;
  95. int id;
  96. u32 slot_offset;
  97. void *log_buffer;
  98. struct mutex buffer_lock; /* for log_buffer alloc/free */
  99. u32 host_read_ptr;
  100. u32 dsp_write_ptr;
  101. /* pos update IPC arrived before the slot offset is known, queried */
  102. bool delayed_pos_update;
  103. wait_queue_head_t trace_sleep;
  104. };
  105. struct sof_mtrace_priv {
  106. struct snd_sof_dev *sdev;
  107. enum sof_mtrace_state mtrace_state;
  108. struct sof_log_state_info state_info;
  109. struct sof_mtrace_core_data cores[];
  110. };
  111. static int sof_ipc4_mtrace_dfs_open(struct inode *inode, struct file *file)
  112. {
  113. struct sof_mtrace_core_data *core_data = inode->i_private;
  114. int ret;
  115. mutex_lock(&core_data->buffer_lock);
  116. if (core_data->log_buffer) {
  117. ret = -EBUSY;
  118. goto out;
  119. }
  120. ret = debugfs_file_get(file->f_path.dentry);
  121. if (unlikely(ret))
  122. goto out;
  123. core_data->log_buffer = kmalloc(SOF_MTRACE_SLOT_SIZE, GFP_KERNEL);
  124. if (!core_data->log_buffer) {
  125. debugfs_file_put(file->f_path.dentry);
  126. ret = -ENOMEM;
  127. goto out;
  128. }
  129. ret = simple_open(inode, file);
  130. if (ret) {
  131. kfree(core_data->log_buffer);
  132. debugfs_file_put(file->f_path.dentry);
  133. }
  134. out:
  135. mutex_unlock(&core_data->buffer_lock);
  136. return ret;
  137. }
  138. static bool sof_wait_mtrace_avail(struct sof_mtrace_core_data *core_data)
  139. {
  140. wait_queue_entry_t wait;
  141. /* data immediately available */
  142. if (core_data->host_read_ptr != core_data->dsp_write_ptr)
  143. return true;
  144. /* wait for available trace data from FW */
  145. init_waitqueue_entry(&wait, current);
  146. set_current_state(TASK_INTERRUPTIBLE);
  147. add_wait_queue(&core_data->trace_sleep, &wait);
  148. if (!signal_pending(current)) {
  149. /* set timeout to max value, no error code */
  150. schedule_timeout(MAX_SCHEDULE_TIMEOUT);
  151. }
  152. remove_wait_queue(&core_data->trace_sleep, &wait);
  153. if (core_data->host_read_ptr != core_data->dsp_write_ptr)
  154. return true;
  155. return false;
  156. }
  157. static ssize_t sof_ipc4_mtrace_dfs_read(struct file *file, char __user *buffer,
  158. size_t count, loff_t *ppos)
  159. {
  160. struct sof_mtrace_core_data *core_data = file->private_data;
  161. u32 log_buffer_offset, log_buffer_size, read_ptr, write_ptr;
  162. struct snd_sof_dev *sdev = core_data->sdev;
  163. struct sof_mtrace_priv *priv = sdev->fw_trace_data;
  164. void *log_buffer = core_data->log_buffer;
  165. loff_t lpos = *ppos;
  166. u32 avail;
  167. int ret;
  168. /* check pos and count */
  169. if (lpos < 0)
  170. return -EINVAL;
  171. if (!count || count < sizeof(avail))
  172. return 0;
  173. /* get available count based on current host offset */
  174. if (!sof_wait_mtrace_avail(core_data)) {
  175. /* No data available */
  176. avail = 0;
  177. if (copy_to_user(buffer, &avail, sizeof(avail)))
  178. return -EFAULT;
  179. return 0;
  180. }
  181. if (core_data->slot_offset == INVALID_SLOT_OFFSET)
  182. return 0;
  183. /* The log data buffer starts after the two pointer in the slot */
  184. log_buffer_offset = core_data->slot_offset + (sizeof(u32) * 2);
  185. /* The log data size excludes the pointers */
  186. log_buffer_size = SOF_MTRACE_SLOT_SIZE - (sizeof(u32) * 2);
  187. read_ptr = core_data->host_read_ptr;
  188. write_ptr = core_data->dsp_write_ptr;
  189. if (read_ptr < write_ptr)
  190. avail = write_ptr - read_ptr;
  191. else
  192. avail = log_buffer_size - read_ptr + write_ptr;
  193. if (!avail)
  194. return 0;
  195. if (avail > log_buffer_size)
  196. avail = log_buffer_size;
  197. /* Need space for the initial u32 of the avail */
  198. if (avail > count - sizeof(avail))
  199. avail = count - sizeof(avail);
  200. if (sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
  201. dev_dbg(sdev->dev,
  202. "core%d, host read: %#x, dsp write: %#x, avail: %#x\n",
  203. core_data->id, read_ptr, write_ptr, avail);
  204. if (read_ptr < write_ptr) {
  205. /* Read data between read pointer and write pointer */
  206. sof_mailbox_read(sdev, log_buffer_offset + read_ptr, log_buffer, avail);
  207. } else {
  208. /* read from read pointer to end of the slot */
  209. sof_mailbox_read(sdev, log_buffer_offset + read_ptr, log_buffer,
  210. avail - write_ptr);
  211. /* read from slot start to write pointer */
  212. if (write_ptr)
  213. sof_mailbox_read(sdev, log_buffer_offset,
  214. (u8 *)(log_buffer) + avail - write_ptr,
  215. write_ptr);
  216. }
  217. /* first write the number of bytes we have gathered */
  218. ret = copy_to_user(buffer, &avail, sizeof(avail));
  219. if (ret)
  220. return -EFAULT;
  221. /* Followed by the data itself */
  222. ret = copy_to_user(buffer + sizeof(avail), log_buffer, avail);
  223. if (ret)
  224. return -EFAULT;
  225. /* Update the host_read_ptr in the slot for this core */
  226. read_ptr += avail;
  227. if (read_ptr >= log_buffer_size)
  228. read_ptr -= log_buffer_size;
  229. sof_mailbox_write(sdev, core_data->slot_offset, &read_ptr, sizeof(read_ptr));
  230. /* Only update the host_read_ptr if mtrace is enabled */
  231. if (priv->mtrace_state != SOF_MTRACE_DISABLED)
  232. core_data->host_read_ptr = read_ptr;
  233. /*
  234. * Ask for a new buffer from user space for the next chunk, not
  235. * streaming due to the heading number of bytes value.
  236. */
  237. *ppos += count;
  238. return count;
  239. }
  240. static int sof_ipc4_mtrace_dfs_release(struct inode *inode, struct file *file)
  241. {
  242. struct sof_mtrace_core_data *core_data = inode->i_private;
  243. debugfs_file_put(file->f_path.dentry);
  244. mutex_lock(&core_data->buffer_lock);
  245. kfree(core_data->log_buffer);
  246. core_data->log_buffer = NULL;
  247. mutex_unlock(&core_data->buffer_lock);
  248. return 0;
  249. }
  250. static const struct file_operations sof_dfs_mtrace_fops = {
  251. .open = sof_ipc4_mtrace_dfs_open,
  252. .read = sof_ipc4_mtrace_dfs_read,
  253. .llseek = default_llseek,
  254. .release = sof_ipc4_mtrace_dfs_release,
  255. .owner = THIS_MODULE,
  256. };
  257. static ssize_t sof_ipc4_priority_mask_dfs_read(struct file *file, char __user *to,
  258. size_t count, loff_t *ppos)
  259. {
  260. struct sof_mtrace_priv *priv = file->private_data;
  261. int i, ret, offset, remaining;
  262. char *buf;
  263. /*
  264. * one entry (14 char + new line = 15):
  265. * " 0: 000001ef"
  266. *
  267. * 16 * 15 + 1 = 241
  268. */
  269. buf = kzalloc(241, GFP_KERNEL);
  270. if (!buf)
  271. return -ENOMEM;
  272. for (i = 0; i < MAX_ALLOWED_LIBRARIES; i++) {
  273. offset = strlen(buf);
  274. remaining = 241 - offset;
  275. snprintf(buf + offset, remaining, "%2d: 0x%08x\n", i,
  276. priv->state_info.logs_priorities_mask[i]);
  277. }
  278. ret = simple_read_from_buffer(to, count, ppos, buf, strlen(buf));
  279. kfree(buf);
  280. return ret;
  281. }
  282. static ssize_t sof_ipc4_priority_mask_dfs_write(struct file *file,
  283. const char __user *from,
  284. size_t count, loff_t *ppos)
  285. {
  286. struct sof_mtrace_priv *priv = file->private_data;
  287. unsigned int id;
  288. char *buf;
  289. u32 mask;
  290. int ret;
  291. /*
  292. * To update Nth mask entry, write:
  293. * "N,0x1234" or "N,1234" to the debugfs file
  294. * The mask will be interpreted as hexadecimal number
  295. */
  296. buf = memdup_user_nul(from, count);
  297. if (IS_ERR(buf))
  298. return PTR_ERR(buf);
  299. ret = sscanf(buf, "%u,0x%x", &id, &mask);
  300. if (ret != 2) {
  301. ret = sscanf(buf, "%u,%x", &id, &mask);
  302. if (ret != 2) {
  303. ret = -EINVAL;
  304. goto out;
  305. }
  306. }
  307. if (id >= MAX_ALLOWED_LIBRARIES) {
  308. ret = -EINVAL;
  309. goto out;
  310. }
  311. priv->state_info.logs_priorities_mask[id] = mask;
  312. ret = count;
  313. out:
  314. kfree(buf);
  315. return ret;
  316. }
  317. static const struct file_operations sof_dfs_priority_mask_fops = {
  318. .open = simple_open,
  319. .read = sof_ipc4_priority_mask_dfs_read,
  320. .write = sof_ipc4_priority_mask_dfs_write,
  321. .llseek = default_llseek,
  322. .owner = THIS_MODULE,
  323. };
  324. static int mtrace_debugfs_create(struct snd_sof_dev *sdev)
  325. {
  326. struct sof_mtrace_priv *priv = sdev->fw_trace_data;
  327. struct dentry *dfs_root;
  328. char dfs_name[100];
  329. int i;
  330. dfs_root = debugfs_create_dir("mtrace", sdev->debugfs_root);
  331. if (IS_ERR_OR_NULL(dfs_root))
  332. return 0;
  333. /* Create files for the logging parameters */
  334. debugfs_create_u32("aging_timer_period", 0644, dfs_root,
  335. &priv->state_info.aging_timer_period);
  336. debugfs_create_u32("fifo_full_timer_period", 0644, dfs_root,
  337. &priv->state_info.fifo_full_timer_period);
  338. debugfs_create_file("logs_priorities_mask", 0644, dfs_root, priv,
  339. &sof_dfs_priority_mask_fops);
  340. /* Separate log files per core */
  341. for (i = 0; i < sdev->num_cores; i++) {
  342. snprintf(dfs_name, sizeof(dfs_name), "core%d", i);
  343. debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i],
  344. &sof_dfs_mtrace_fops);
  345. }
  346. return 0;
  347. }
  348. static int ipc4_mtrace_enable(struct snd_sof_dev *sdev)
  349. {
  350. struct sof_mtrace_priv *priv = sdev->fw_trace_data;
  351. const struct sof_ipc_ops *iops = sdev->ipc->ops;
  352. struct sof_ipc4_msg msg;
  353. u64 system_time;
  354. ktime_t kt;
  355. int ret;
  356. if (priv->mtrace_state != SOF_MTRACE_DISABLED)
  357. return 0;
  358. msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
  359. msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
  360. msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
  361. msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
  362. msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_SYSTEM_TIME);
  363. /* The system time is in usec, UTC, epoch is 1601-01-01 00:00:00 */
  364. kt = ktime_add_us(ktime_get_real(), FW_EPOCH_DELTA * USEC_PER_SEC);
  365. system_time = ktime_to_us(kt);
  366. msg.data_size = sizeof(system_time);
  367. msg.data_ptr = &system_time;
  368. ret = iops->set_get_data(sdev, &msg, msg.data_size, true);
  369. if (ret)
  370. return ret;
  371. msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_ENABLE_LOGS);
  372. priv->state_info.enable = 1;
  373. msg.data_size = sizeof(priv->state_info);
  374. msg.data_ptr = &priv->state_info;
  375. priv->mtrace_state = SOF_MTRACE_INITIALIZING;
  376. ret = iops->set_get_data(sdev, &msg, msg.data_size, true);
  377. if (ret) {
  378. priv->mtrace_state = SOF_MTRACE_DISABLED;
  379. return ret;
  380. }
  381. priv->mtrace_state = SOF_MTRACE_ENABLED;
  382. return 0;
  383. }
  384. static void ipc4_mtrace_disable(struct snd_sof_dev *sdev)
  385. {
  386. struct sof_mtrace_priv *priv = sdev->fw_trace_data;
  387. const struct sof_ipc_ops *iops = sdev->ipc->ops;
  388. struct sof_ipc4_msg msg;
  389. int i;
  390. if (priv->mtrace_state == SOF_MTRACE_DISABLED)
  391. return;
  392. msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
  393. msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
  394. msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
  395. msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
  396. msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_ENABLE_LOGS);
  397. priv->state_info.enable = 0;
  398. msg.data_size = sizeof(priv->state_info);
  399. msg.data_ptr = &priv->state_info;
  400. iops->set_get_data(sdev, &msg, msg.data_size, true);
  401. priv->mtrace_state = SOF_MTRACE_DISABLED;
  402. for (i = 0; i < sdev->num_cores; i++) {
  403. struct sof_mtrace_core_data *core_data = &priv->cores[i];
  404. core_data->host_read_ptr = 0;
  405. core_data->dsp_write_ptr = 0;
  406. wake_up(&core_data->trace_sleep);
  407. }
  408. }
  409. /*
  410. * Each DSP core logs to a dedicated slot.
  411. * Parse the slot descriptors at debug_box offset to find the debug log slots
  412. * and map them to cores.
  413. * There are 15 slots and therefore 15 descriptors to check (MAX_MTRACE_SLOTS)
  414. */
  415. static void sof_mtrace_find_core_slots(struct snd_sof_dev *sdev)
  416. {
  417. struct sof_mtrace_priv *priv = sdev->fw_trace_data;
  418. struct sof_mtrace_core_data *core_data;
  419. u32 slot_desc_type_offset, type, core;
  420. int i;
  421. for (i = 0; i < MAX_MTRACE_SLOTS; i++) {
  422. /* The type is the second u32 in the slot descriptor */
  423. slot_desc_type_offset = sdev->debug_box.offset;
  424. slot_desc_type_offset += SOF_MTRACE_DESCRIPTOR_SIZE * i + sizeof(u32);
  425. sof_mailbox_read(sdev, slot_desc_type_offset, &type, sizeof(type));
  426. if ((type & SOF_MTRACE_SLOT_TYPE_MASK) == SOF_MTRACE_SLOT_DEBUG_LOG) {
  427. core = type & SOF_MTRACE_SLOT_CORE_MASK;
  428. if (core >= sdev->num_cores) {
  429. dev_dbg(sdev->dev, "core%u is invalid for slot%d\n",
  430. core, i);
  431. continue;
  432. }
  433. core_data = &priv->cores[core];
  434. /*
  435. * The area reserved for descriptors have the same size
  436. * as a slot.
  437. * In other words: slot0 starts at
  438. * debug_box + SOF_MTRACE_SLOT_SIZE offset
  439. */
  440. core_data->slot_offset = sdev->debug_box.offset;
  441. core_data->slot_offset += SOF_MTRACE_SLOT_SIZE * (i + 1);
  442. dev_dbg(sdev->dev, "slot%d is used for core%u\n", i, core);
  443. if (core_data->delayed_pos_update) {
  444. sof_ipc4_mtrace_update_pos(sdev, core);
  445. core_data->delayed_pos_update = false;
  446. }
  447. } else if (type) {
  448. dev_dbg(sdev->dev, "slot%d is not a log slot (%#x)\n", i, type);
  449. }
  450. }
  451. }
  452. static int ipc4_mtrace_init(struct snd_sof_dev *sdev)
  453. {
  454. struct sof_ipc4_fw_data *ipc4_data = sdev->private;
  455. struct sof_mtrace_priv *priv;
  456. int i, ret;
  457. if (sdev->fw_trace_data) {
  458. dev_err(sdev->dev, "fw_trace_data has been already allocated\n");
  459. return -EBUSY;
  460. }
  461. if (!ipc4_data->mtrace_log_bytes ||
  462. ipc4_data->mtrace_type != SOF_IPC4_MTRACE_INTEL_CAVS_2) {
  463. sdev->fw_trace_is_supported = false;
  464. return 0;
  465. }
  466. priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores),
  467. GFP_KERNEL);
  468. if (!priv)
  469. return -ENOMEM;
  470. sdev->fw_trace_data = priv;
  471. /* Set initial values for mtrace parameters */
  472. priv->state_info.aging_timer_period = DEFAULT_AGING_TIMER_PERIOD_MS;
  473. priv->state_info.fifo_full_timer_period = DEFAULT_FIFO_FULL_TIMER_PERIOD_MS;
  474. /* Only enable basefw logs initially (index 0 is always basefw) */
  475. priv->state_info.logs_priorities_mask[0] = DEFAULT_LOGS_PRIORITIES_MASK;
  476. for (i = 0; i < sdev->num_cores; i++) {
  477. struct sof_mtrace_core_data *core_data = &priv->cores[i];
  478. init_waitqueue_head(&core_data->trace_sleep);
  479. mutex_init(&core_data->buffer_lock);
  480. core_data->sdev = sdev;
  481. core_data->id = i;
  482. }
  483. ret = ipc4_mtrace_enable(sdev);
  484. if (ret) {
  485. /*
  486. * Mark firmware tracing as not supported and return 0 to not
  487. * block the whole audio stack
  488. */
  489. sdev->fw_trace_is_supported = false;
  490. dev_dbg(sdev->dev, "initialization failed, fw tracing is disabled\n");
  491. return 0;
  492. }
  493. sof_mtrace_find_core_slots(sdev);
  494. ret = mtrace_debugfs_create(sdev);
  495. if (ret)
  496. ipc4_mtrace_disable(sdev);
  497. return ret;
  498. }
  499. static void ipc4_mtrace_free(struct snd_sof_dev *sdev)
  500. {
  501. ipc4_mtrace_disable(sdev);
  502. }
  503. int sof_ipc4_mtrace_update_pos(struct snd_sof_dev *sdev, int core)
  504. {
  505. struct sof_mtrace_priv *priv = sdev->fw_trace_data;
  506. struct sof_mtrace_core_data *core_data;
  507. if (!sdev->fw_trace_is_supported ||
  508. priv->mtrace_state == SOF_MTRACE_DISABLED)
  509. return 0;
  510. if (core >= sdev->num_cores)
  511. return -EINVAL;
  512. core_data = &priv->cores[core];
  513. if (core_data->slot_offset == INVALID_SLOT_OFFSET) {
  514. core_data->delayed_pos_update = true;
  515. return 0;
  516. }
  517. /* Read out the dsp_write_ptr from the slot for this core */
  518. sof_mailbox_read(sdev, core_data->slot_offset + sizeof(u32),
  519. &core_data->dsp_write_ptr, 4);
  520. core_data->dsp_write_ptr -= core_data->dsp_write_ptr % 4;
  521. if (sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
  522. dev_dbg(sdev->dev, "core%d, host read: %#x, dsp write: %#x",
  523. core, core_data->host_read_ptr, core_data->dsp_write_ptr);
  524. wake_up(&core_data->trace_sleep);
  525. return 0;
  526. }
  527. static int ipc4_mtrace_resume(struct snd_sof_dev *sdev)
  528. {
  529. return ipc4_mtrace_enable(sdev);
  530. }
  531. static void ipc4_mtrace_suspend(struct snd_sof_dev *sdev, pm_message_t pm_state)
  532. {
  533. ipc4_mtrace_disable(sdev);
  534. }
  535. const struct sof_ipc_fw_tracing_ops ipc4_mtrace_ops = {
  536. .init = ipc4_mtrace_init,
  537. .free = ipc4_mtrace_free,
  538. .suspend = ipc4_mtrace_suspend,
  539. .resume = ipc4_mtrace_resume,
  540. };