shim.h 6.1 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
  2. /*
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * Copyright(c) 2017 Intel Corporation. All rights reserved.
  7. *
  8. * Author: Liam Girdwood <[email protected]>
  9. */
  10. #ifndef __SOF_INTEL_SHIM_H
  11. #define __SOF_INTEL_SHIM_H
  12. enum sof_intel_hw_ip_version {
  13. SOF_INTEL_TANGIER,
  14. SOF_INTEL_BAYTRAIL,
  15. SOF_INTEL_BROADWELL,
  16. SOF_INTEL_CAVS_1_5, /* SkyLake, KabyLake, AmberLake */
  17. SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
  18. SOF_INTEL_CAVS_1_8, /* CannonLake, CometLake, CoffeeLake */
  19. SOF_INTEL_CAVS_2_0, /* IceLake, JasperLake */
  20. SOF_INTEL_CAVS_2_5, /* TigerLake, AlderLake */
  21. SOF_INTEL_ACE_1_0, /* MeteorLake */
  22. };
  23. /*
  24. * SHIM registers for BYT, BSW, CHT, BDW
  25. */
  26. #define SHIM_CSR (SHIM_OFFSET + 0x00)
  27. #define SHIM_PISR (SHIM_OFFSET + 0x08)
  28. #define SHIM_PIMR (SHIM_OFFSET + 0x10)
  29. #define SHIM_ISRX (SHIM_OFFSET + 0x18)
  30. #define SHIM_ISRD (SHIM_OFFSET + 0x20)
  31. #define SHIM_IMRX (SHIM_OFFSET + 0x28)
  32. #define SHIM_IMRD (SHIM_OFFSET + 0x30)
  33. #define SHIM_IPCX (SHIM_OFFSET + 0x38)
  34. #define SHIM_IPCD (SHIM_OFFSET + 0x40)
  35. #define SHIM_ISRSC (SHIM_OFFSET + 0x48)
  36. #define SHIM_ISRLPESC (SHIM_OFFSET + 0x50)
  37. #define SHIM_IMRSC (SHIM_OFFSET + 0x58)
  38. #define SHIM_IMRLPESC (SHIM_OFFSET + 0x60)
  39. #define SHIM_IPCSC (SHIM_OFFSET + 0x68)
  40. #define SHIM_IPCLPESC (SHIM_OFFSET + 0x70)
  41. #define SHIM_CLKCTL (SHIM_OFFSET + 0x78)
  42. #define SHIM_CSR2 (SHIM_OFFSET + 0x80)
  43. #define SHIM_LTRC (SHIM_OFFSET + 0xE0)
  44. #define SHIM_HMDC (SHIM_OFFSET + 0xE8)
  45. #define SHIM_PWMCTRL 0x1000
  46. /*
  47. * SST SHIM register bits for BYT, BSW, CHT, BDW
  48. * Register bit naming and functionaility can differ between devices.
  49. */
  50. /* CSR / CS */
  51. #define SHIM_CSR_RST BIT(1)
  52. #define SHIM_CSR_SBCS0 BIT(2)
  53. #define SHIM_CSR_SBCS1 BIT(3)
  54. #define SHIM_CSR_DCS(x) ((x) << 4)
  55. #define SHIM_CSR_DCS_MASK (0x7 << 4)
  56. #define SHIM_CSR_STALL BIT(10)
  57. #define SHIM_CSR_S0IOCS BIT(21)
  58. #define SHIM_CSR_S1IOCS BIT(23)
  59. #define SHIM_CSR_LPCS BIT(31)
  60. #define SHIM_CSR_24MHZ_LPCS \
  61. (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
  62. #define SHIM_CSR_24MHZ_NO_LPCS (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
  63. #define SHIM_BYT_CSR_RST BIT(0)
  64. #define SHIM_BYT_CSR_VECTOR_SEL BIT(1)
  65. #define SHIM_BYT_CSR_STALL BIT(2)
  66. #define SHIM_BYT_CSR_PWAITMODE BIT(3)
  67. /* ISRX / ISC */
  68. #define SHIM_ISRX_BUSY BIT(1)
  69. #define SHIM_ISRX_DONE BIT(0)
  70. #define SHIM_BYT_ISRX_REQUEST BIT(1)
  71. /* ISRD / ISD */
  72. #define SHIM_ISRD_BUSY BIT(1)
  73. #define SHIM_ISRD_DONE BIT(0)
  74. /* IMRX / IMC */
  75. #define SHIM_IMRX_BUSY BIT(1)
  76. #define SHIM_IMRX_DONE BIT(0)
  77. #define SHIM_BYT_IMRX_REQUEST BIT(1)
  78. /* IMRD / IMD */
  79. #define SHIM_IMRD_DONE BIT(0)
  80. #define SHIM_IMRD_BUSY BIT(1)
  81. #define SHIM_IMRD_SSP0 BIT(16)
  82. #define SHIM_IMRD_DMAC0 BIT(21)
  83. #define SHIM_IMRD_DMAC1 BIT(22)
  84. #define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
  85. /* IPCX / IPCC */
  86. #define SHIM_IPCX_DONE BIT(30)
  87. #define SHIM_IPCX_BUSY BIT(31)
  88. #define SHIM_BYT_IPCX_DONE BIT_ULL(62)
  89. #define SHIM_BYT_IPCX_BUSY BIT_ULL(63)
  90. /* IPCD */
  91. #define SHIM_IPCD_DONE BIT(30)
  92. #define SHIM_IPCD_BUSY BIT(31)
  93. #define SHIM_BYT_IPCD_DONE BIT_ULL(62)
  94. #define SHIM_BYT_IPCD_BUSY BIT_ULL(63)
  95. /* CLKCTL */
  96. #define SHIM_CLKCTL_SMOS(x) ((x) << 24)
  97. #define SHIM_CLKCTL_MASK (3 << 24)
  98. #define SHIM_CLKCTL_DCPLCG BIT(18)
  99. #define SHIM_CLKCTL_SCOE1 BIT(17)
  100. #define SHIM_CLKCTL_SCOE0 BIT(16)
  101. /* CSR2 / CS2 */
  102. #define SHIM_CSR2_SDFD_SSP0 BIT(1)
  103. #define SHIM_CSR2_SDFD_SSP1 BIT(2)
  104. /* LTRC */
  105. #define SHIM_LTRC_VAL(x) ((x) << 0)
  106. /* HMDC */
  107. #define SHIM_HMDC_HDDA0(x) ((x) << 0)
  108. #define SHIM_HMDC_HDDA1(x) ((x) << 7)
  109. #define SHIM_HMDC_HDDA_E0_CH0 1
  110. #define SHIM_HMDC_HDDA_E0_CH1 2
  111. #define SHIM_HMDC_HDDA_E0_CH2 4
  112. #define SHIM_HMDC_HDDA_E0_CH3 8
  113. #define SHIM_HMDC_HDDA_E1_CH0 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
  114. #define SHIM_HMDC_HDDA_E1_CH1 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
  115. #define SHIM_HMDC_HDDA_E1_CH2 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
  116. #define SHIM_HMDC_HDDA_E1_CH3 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
  117. #define SHIM_HMDC_HDDA_E0_ALLCH \
  118. (SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
  119. SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
  120. #define SHIM_HMDC_HDDA_E1_ALLCH \
  121. (SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
  122. SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
  123. /* Audio DSP PCI registers */
  124. #define PCI_VDRTCTL0 0xa0
  125. #define PCI_VDRTCTL1 0xa4
  126. #define PCI_VDRTCTL2 0xa8
  127. #define PCI_VDRTCTL3 0xaC
  128. /* VDRTCTL0 */
  129. #define PCI_VDRTCL0_D3PGD BIT(0)
  130. #define PCI_VDRTCL0_D3SRAMPGD BIT(1)
  131. #define PCI_VDRTCL0_DSRAMPGE_SHIFT 12
  132. #define PCI_VDRTCL0_DSRAMPGE_MASK GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
  133. PCI_VDRTCL0_DSRAMPGE_SHIFT)
  134. #define PCI_VDRTCL0_ISRAMPGE_SHIFT 2
  135. #define PCI_VDRTCL0_ISRAMPGE_MASK GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
  136. PCI_VDRTCL0_ISRAMPGE_SHIFT)
  137. /* VDRTCTL2 */
  138. #define PCI_VDRTCL2_DCLCGE BIT(1)
  139. #define PCI_VDRTCL2_DTCGE BIT(10)
  140. #define PCI_VDRTCL2_APLLSE_MASK BIT(31)
  141. /* PMCS */
  142. #define PCI_PMCS 0x84
  143. #define PCI_PMCS_PS_MASK 0x3
  144. /* Intel quirks */
  145. #define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
  146. /* DSP hardware descriptor */
  147. struct sof_intel_dsp_desc {
  148. int cores_num;
  149. int host_managed_cores_mask;
  150. int init_core_mask; /* cores available after fw boot */
  151. int ipc_req;
  152. int ipc_req_mask;
  153. int ipc_ack;
  154. int ipc_ack_mask;
  155. int ipc_ctl;
  156. int rom_status_reg;
  157. int rom_init_timeout;
  158. int ssp_count; /* ssp count of the platform */
  159. int ssp_base_offset; /* base address of the SSPs */
  160. u32 sdw_shim_base;
  161. u32 sdw_alh_base;
  162. u32 quirks;
  163. enum sof_intel_hw_ip_version hw_ip_version;
  164. bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
  165. bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
  166. int (*power_down_dsp)(struct snd_sof_dev *sdev);
  167. int (*disable_interrupts)(struct snd_sof_dev *sdev);
  168. int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
  169. };
  170. extern struct snd_sof_dsp_ops sof_tng_ops;
  171. extern const struct sof_intel_dsp_desc tng_chip_info;
  172. struct sof_intel_stream {
  173. size_t posn_offset;
  174. };
  175. static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata)
  176. {
  177. const struct sof_dev_desc *desc = pdata->desc;
  178. return desc->chip_info;
  179. }
  180. #endif