siu_pcm.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // siu_pcm.c - ALSA driver for Renesas SH7343, SH7722 SIU peripheral.
  4. //
  5. // Copyright (C) 2009-2010 Guennadi Liakhovetski <[email protected]>
  6. // Copyright (C) 2006 Carlos Munoz <[email protected]>
  7. #include <linux/delay.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <sound/control.h>
  14. #include <sound/core.h>
  15. #include <sound/pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include <sound/soc.h>
  18. #include <asm/siu.h>
  19. #include "siu.h"
  20. #define DRV_NAME "siu-i2s"
  21. #define GET_MAX_PERIODS(buf_bytes, period_bytes) \
  22. ((buf_bytes) / (period_bytes))
  23. #define PERIOD_OFFSET(buf_addr, period_num, period_bytes) \
  24. ((buf_addr) + ((period_num) * (period_bytes)))
  25. #define RWF_STM_RD 0x01 /* Read in progress */
  26. #define RWF_STM_WT 0x02 /* Write in progress */
  27. struct siu_port *siu_ports[SIU_PORT_NUM];
  28. /* transfersize is number of u32 dma transfers per period */
  29. static int siu_pcm_stmwrite_stop(struct siu_port *port_info)
  30. {
  31. struct siu_info *info = siu_i2s_data;
  32. u32 __iomem *base = info->reg;
  33. struct siu_stream *siu_stream = &port_info->playback;
  34. u32 stfifo;
  35. if (!siu_stream->rw_flg)
  36. return -EPERM;
  37. /* output FIFO disable */
  38. stfifo = siu_read32(base + SIU_STFIFO);
  39. siu_write32(base + SIU_STFIFO, stfifo & ~0x0c180c18);
  40. pr_debug("%s: STFIFO %x -> %x\n", __func__,
  41. stfifo, stfifo & ~0x0c180c18);
  42. /* during stmwrite clear */
  43. siu_stream->rw_flg = 0;
  44. return 0;
  45. }
  46. static int siu_pcm_stmwrite_start(struct siu_port *port_info)
  47. {
  48. struct siu_stream *siu_stream = &port_info->playback;
  49. if (siu_stream->rw_flg)
  50. return -EPERM;
  51. /* Current period in buffer */
  52. port_info->playback.cur_period = 0;
  53. /* during stmwrite flag set */
  54. siu_stream->rw_flg = RWF_STM_WT;
  55. /* DMA transfer start */
  56. queue_work(system_highpri_wq, &siu_stream->work);
  57. return 0;
  58. }
  59. static void siu_dma_tx_complete(void *arg)
  60. {
  61. struct siu_stream *siu_stream = arg;
  62. if (!siu_stream->rw_flg)
  63. return;
  64. /* Update completed period count */
  65. if (++siu_stream->cur_period >=
  66. GET_MAX_PERIODS(siu_stream->buf_bytes,
  67. siu_stream->period_bytes))
  68. siu_stream->cur_period = 0;
  69. pr_debug("%s: done period #%d (%u/%u bytes), cookie %d\n",
  70. __func__, siu_stream->cur_period,
  71. siu_stream->cur_period * siu_stream->period_bytes,
  72. siu_stream->buf_bytes, siu_stream->cookie);
  73. queue_work(system_highpri_wq, &siu_stream->work);
  74. /* Notify alsa: a period is done */
  75. snd_pcm_period_elapsed(siu_stream->substream);
  76. }
  77. static int siu_pcm_wr_set(struct siu_port *port_info,
  78. dma_addr_t buff, u32 size)
  79. {
  80. struct siu_info *info = siu_i2s_data;
  81. u32 __iomem *base = info->reg;
  82. struct siu_stream *siu_stream = &port_info->playback;
  83. struct snd_pcm_substream *substream = siu_stream->substream;
  84. struct device *dev = substream->pcm->card->dev;
  85. struct dma_async_tx_descriptor *desc;
  86. dma_cookie_t cookie;
  87. struct scatterlist sg;
  88. u32 stfifo;
  89. sg_init_table(&sg, 1);
  90. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
  91. size, offset_in_page(buff));
  92. sg_dma_len(&sg) = size;
  93. sg_dma_address(&sg) = buff;
  94. desc = dmaengine_prep_slave_sg(siu_stream->chan,
  95. &sg, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  96. if (!desc) {
  97. dev_err(dev, "Failed to allocate a dma descriptor\n");
  98. return -ENOMEM;
  99. }
  100. desc->callback = siu_dma_tx_complete;
  101. desc->callback_param = siu_stream;
  102. cookie = dmaengine_submit(desc);
  103. if (cookie < 0) {
  104. dev_err(dev, "Failed to submit a dma transfer\n");
  105. return cookie;
  106. }
  107. siu_stream->tx_desc = desc;
  108. siu_stream->cookie = cookie;
  109. dma_async_issue_pending(siu_stream->chan);
  110. /* only output FIFO enable */
  111. stfifo = siu_read32(base + SIU_STFIFO);
  112. siu_write32(base + SIU_STFIFO, stfifo | (port_info->stfifo & 0x0c180c18));
  113. dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
  114. stfifo, stfifo | (port_info->stfifo & 0x0c180c18));
  115. return 0;
  116. }
  117. static int siu_pcm_rd_set(struct siu_port *port_info,
  118. dma_addr_t buff, size_t size)
  119. {
  120. struct siu_info *info = siu_i2s_data;
  121. u32 __iomem *base = info->reg;
  122. struct siu_stream *siu_stream = &port_info->capture;
  123. struct snd_pcm_substream *substream = siu_stream->substream;
  124. struct device *dev = substream->pcm->card->dev;
  125. struct dma_async_tx_descriptor *desc;
  126. dma_cookie_t cookie;
  127. struct scatterlist sg;
  128. u32 stfifo;
  129. dev_dbg(dev, "%s: %u@%llx\n", __func__, size, (unsigned long long)buff);
  130. sg_init_table(&sg, 1);
  131. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
  132. size, offset_in_page(buff));
  133. sg_dma_len(&sg) = size;
  134. sg_dma_address(&sg) = buff;
  135. desc = dmaengine_prep_slave_sg(siu_stream->chan,
  136. &sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  137. if (!desc) {
  138. dev_err(dev, "Failed to allocate dma descriptor\n");
  139. return -ENOMEM;
  140. }
  141. desc->callback = siu_dma_tx_complete;
  142. desc->callback_param = siu_stream;
  143. cookie = dmaengine_submit(desc);
  144. if (cookie < 0) {
  145. dev_err(dev, "Failed to submit dma descriptor\n");
  146. return cookie;
  147. }
  148. siu_stream->tx_desc = desc;
  149. siu_stream->cookie = cookie;
  150. dma_async_issue_pending(siu_stream->chan);
  151. /* only input FIFO enable */
  152. stfifo = siu_read32(base + SIU_STFIFO);
  153. siu_write32(base + SIU_STFIFO, siu_read32(base + SIU_STFIFO) |
  154. (port_info->stfifo & 0x13071307));
  155. dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
  156. stfifo, stfifo | (port_info->stfifo & 0x13071307));
  157. return 0;
  158. }
  159. static void siu_io_work(struct work_struct *work)
  160. {
  161. struct siu_stream *siu_stream = container_of(work, struct siu_stream,
  162. work);
  163. struct snd_pcm_substream *substream = siu_stream->substream;
  164. struct device *dev = substream->pcm->card->dev;
  165. struct snd_pcm_runtime *rt = substream->runtime;
  166. struct siu_port *port_info = siu_port_info(substream);
  167. dev_dbg(dev, "%s: flags %x\n", __func__, siu_stream->rw_flg);
  168. if (!siu_stream->rw_flg) {
  169. dev_dbg(dev, "%s: stream inactive\n", __func__);
  170. return;
  171. }
  172. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  173. dma_addr_t buff;
  174. size_t count;
  175. buff = (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
  176. siu_stream->cur_period,
  177. siu_stream->period_bytes);
  178. count = siu_stream->period_bytes;
  179. /* DMA transfer start */
  180. siu_pcm_rd_set(port_info, buff, count);
  181. } else {
  182. siu_pcm_wr_set(port_info,
  183. (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
  184. siu_stream->cur_period,
  185. siu_stream->period_bytes),
  186. siu_stream->period_bytes);
  187. }
  188. }
  189. /* Capture */
  190. static int siu_pcm_stmread_start(struct siu_port *port_info)
  191. {
  192. struct siu_stream *siu_stream = &port_info->capture;
  193. if (siu_stream->xfer_cnt > 0x1000000)
  194. return -EINVAL;
  195. if (siu_stream->rw_flg)
  196. return -EPERM;
  197. /* Current period in buffer */
  198. siu_stream->cur_period = 0;
  199. /* during stmread flag set */
  200. siu_stream->rw_flg = RWF_STM_RD;
  201. queue_work(system_highpri_wq, &siu_stream->work);
  202. return 0;
  203. }
  204. static int siu_pcm_stmread_stop(struct siu_port *port_info)
  205. {
  206. struct siu_info *info = siu_i2s_data;
  207. u32 __iomem *base = info->reg;
  208. struct siu_stream *siu_stream = &port_info->capture;
  209. struct device *dev = siu_stream->substream->pcm->card->dev;
  210. u32 stfifo;
  211. if (!siu_stream->rw_flg)
  212. return -EPERM;
  213. /* input FIFO disable */
  214. stfifo = siu_read32(base + SIU_STFIFO);
  215. siu_write32(base + SIU_STFIFO, stfifo & ~0x13071307);
  216. dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
  217. stfifo, stfifo & ~0x13071307);
  218. /* during stmread flag clear */
  219. siu_stream->rw_flg = 0;
  220. return 0;
  221. }
  222. static bool filter(struct dma_chan *chan, void *secondary)
  223. {
  224. struct sh_dmae_slave *param = secondary;
  225. pr_debug("%s: secondary ID %d\n", __func__, param->shdma_slave.slave_id);
  226. chan->private = &param->shdma_slave;
  227. return true;
  228. }
  229. static int siu_pcm_open(struct snd_soc_component *component,
  230. struct snd_pcm_substream *ss)
  231. {
  232. /* Playback / Capture */
  233. struct siu_platform *pdata = component->dev->platform_data;
  234. struct siu_info *info = siu_i2s_data;
  235. struct siu_port *port_info = siu_port_info(ss);
  236. struct siu_stream *siu_stream;
  237. u32 port = info->port_id;
  238. struct device *dev = ss->pcm->card->dev;
  239. dma_cap_mask_t mask;
  240. struct sh_dmae_slave *param;
  241. dma_cap_zero(mask);
  242. dma_cap_set(DMA_SLAVE, mask);
  243. dev_dbg(dev, "%s, port=%d@%p\n", __func__, port, port_info);
  244. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  245. siu_stream = &port_info->playback;
  246. param = &siu_stream->param;
  247. param->shdma_slave.slave_id = port ? pdata->dma_slave_tx_b :
  248. pdata->dma_slave_tx_a;
  249. } else {
  250. siu_stream = &port_info->capture;
  251. param = &siu_stream->param;
  252. param->shdma_slave.slave_id = port ? pdata->dma_slave_rx_b :
  253. pdata->dma_slave_rx_a;
  254. }
  255. /* Get DMA channel */
  256. siu_stream->chan = dma_request_channel(mask, filter, param);
  257. if (!siu_stream->chan) {
  258. dev_err(dev, "DMA channel allocation failed!\n");
  259. return -EBUSY;
  260. }
  261. siu_stream->substream = ss;
  262. return 0;
  263. }
  264. static int siu_pcm_close(struct snd_soc_component *component,
  265. struct snd_pcm_substream *ss)
  266. {
  267. struct siu_info *info = siu_i2s_data;
  268. struct device *dev = ss->pcm->card->dev;
  269. struct siu_port *port_info = siu_port_info(ss);
  270. struct siu_stream *siu_stream;
  271. dev_dbg(dev, "%s: port=%d\n", __func__, info->port_id);
  272. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  273. siu_stream = &port_info->playback;
  274. else
  275. siu_stream = &port_info->capture;
  276. dma_release_channel(siu_stream->chan);
  277. siu_stream->chan = NULL;
  278. siu_stream->substream = NULL;
  279. return 0;
  280. }
  281. static int siu_pcm_prepare(struct snd_soc_component *component,
  282. struct snd_pcm_substream *ss)
  283. {
  284. struct siu_info *info = siu_i2s_data;
  285. struct siu_port *port_info = siu_port_info(ss);
  286. struct device *dev = ss->pcm->card->dev;
  287. struct snd_pcm_runtime *rt;
  288. struct siu_stream *siu_stream;
  289. snd_pcm_sframes_t xfer_cnt;
  290. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  291. siu_stream = &port_info->playback;
  292. else
  293. siu_stream = &port_info->capture;
  294. rt = siu_stream->substream->runtime;
  295. siu_stream->buf_bytes = snd_pcm_lib_buffer_bytes(ss);
  296. siu_stream->period_bytes = snd_pcm_lib_period_bytes(ss);
  297. dev_dbg(dev, "%s: port=%d, %d channels, period=%u bytes\n", __func__,
  298. info->port_id, rt->channels, siu_stream->period_bytes);
  299. /* We only support buffers that are multiples of the period */
  300. if (siu_stream->buf_bytes % siu_stream->period_bytes) {
  301. dev_err(dev, "%s() - buffer=%d not multiple of period=%d\n",
  302. __func__, siu_stream->buf_bytes,
  303. siu_stream->period_bytes);
  304. return -EINVAL;
  305. }
  306. xfer_cnt = bytes_to_frames(rt, siu_stream->period_bytes);
  307. if (!xfer_cnt || xfer_cnt > 0x1000000)
  308. return -EINVAL;
  309. siu_stream->format = rt->format;
  310. siu_stream->xfer_cnt = xfer_cnt;
  311. dev_dbg(dev, "port=%d buf=%lx buf_bytes=%d period_bytes=%d "
  312. "format=%d channels=%d xfer_cnt=%d\n", info->port_id,
  313. (unsigned long)rt->dma_addr, siu_stream->buf_bytes,
  314. siu_stream->period_bytes,
  315. siu_stream->format, rt->channels, (int)xfer_cnt);
  316. return 0;
  317. }
  318. static int siu_pcm_trigger(struct snd_soc_component *component,
  319. struct snd_pcm_substream *ss, int cmd)
  320. {
  321. struct siu_info *info = siu_i2s_data;
  322. struct device *dev = ss->pcm->card->dev;
  323. struct siu_port *port_info = siu_port_info(ss);
  324. int ret;
  325. dev_dbg(dev, "%s: port=%d@%p, cmd=%d\n", __func__,
  326. info->port_id, port_info, cmd);
  327. switch (cmd) {
  328. case SNDRV_PCM_TRIGGER_START:
  329. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  330. ret = siu_pcm_stmwrite_start(port_info);
  331. else
  332. ret = siu_pcm_stmread_start(port_info);
  333. if (ret < 0)
  334. dev_warn(dev, "%s: start failed on port=%d\n",
  335. __func__, info->port_id);
  336. break;
  337. case SNDRV_PCM_TRIGGER_STOP:
  338. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  339. siu_pcm_stmwrite_stop(port_info);
  340. else
  341. siu_pcm_stmread_stop(port_info);
  342. ret = 0;
  343. break;
  344. default:
  345. dev_err(dev, "%s() unsupported cmd=%d\n", __func__, cmd);
  346. ret = -EINVAL;
  347. }
  348. return ret;
  349. }
  350. /*
  351. * So far only resolution of one period is supported, subject to extending the
  352. * dmangine API
  353. */
  354. static snd_pcm_uframes_t
  355. siu_pcm_pointer_dma(struct snd_soc_component *component,
  356. struct snd_pcm_substream *ss)
  357. {
  358. struct device *dev = ss->pcm->card->dev;
  359. struct siu_info *info = siu_i2s_data;
  360. u32 __iomem *base = info->reg;
  361. struct siu_port *port_info = siu_port_info(ss);
  362. struct snd_pcm_runtime *rt = ss->runtime;
  363. size_t ptr;
  364. struct siu_stream *siu_stream;
  365. if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
  366. siu_stream = &port_info->playback;
  367. else
  368. siu_stream = &port_info->capture;
  369. /*
  370. * ptr is the offset into the buffer where the dma is currently at. We
  371. * check if the dma buffer has just wrapped.
  372. */
  373. ptr = PERIOD_OFFSET(rt->dma_addr,
  374. siu_stream->cur_period,
  375. siu_stream->period_bytes) - rt->dma_addr;
  376. dev_dbg(dev,
  377. "%s: port=%d, events %x, FSTS %x, xferred %u/%u, cookie %d\n",
  378. __func__, info->port_id, siu_read32(base + SIU_EVNTC),
  379. siu_read32(base + SIU_SBFSTS), ptr, siu_stream->buf_bytes,
  380. siu_stream->cookie);
  381. if (ptr >= siu_stream->buf_bytes)
  382. ptr = 0;
  383. return bytes_to_frames(ss->runtime, ptr);
  384. }
  385. static int siu_pcm_new(struct snd_soc_component *component,
  386. struct snd_soc_pcm_runtime *rtd)
  387. {
  388. /* card->dev == socdev->dev, see snd_soc_new_pcms() */
  389. struct snd_card *card = rtd->card->snd_card;
  390. struct snd_pcm *pcm = rtd->pcm;
  391. struct siu_info *info = siu_i2s_data;
  392. struct platform_device *pdev = to_platform_device(card->dev);
  393. int ret;
  394. int i;
  395. /* pdev->id selects between SIUA and SIUB */
  396. if (pdev->id < 0 || pdev->id >= SIU_PORT_NUM)
  397. return -EINVAL;
  398. info->port_id = pdev->id;
  399. /*
  400. * While the siu has 2 ports, only one port can be on at a time (only 1
  401. * SPB). So far all the boards using the siu had only one of the ports
  402. * wired to a codec. To simplify things, we only register one port with
  403. * alsa. In case both ports are needed, it should be changed here
  404. */
  405. for (i = pdev->id; i < pdev->id + 1; i++) {
  406. struct siu_port **port_info = &siu_ports[i];
  407. ret = siu_init_port(i, port_info, card);
  408. if (ret < 0)
  409. return ret;
  410. snd_pcm_set_managed_buffer_all(pcm,
  411. SNDRV_DMA_TYPE_DEV, card->dev,
  412. SIU_BUFFER_BYTES_MAX, SIU_BUFFER_BYTES_MAX);
  413. (*port_info)->pcm = pcm;
  414. /* IO works */
  415. INIT_WORK(&(*port_info)->playback.work, siu_io_work);
  416. INIT_WORK(&(*port_info)->capture.work, siu_io_work);
  417. }
  418. dev_info(card->dev, "SuperH SIU driver initialized.\n");
  419. return 0;
  420. }
  421. static void siu_pcm_free(struct snd_soc_component *component,
  422. struct snd_pcm *pcm)
  423. {
  424. struct platform_device *pdev = to_platform_device(pcm->card->dev);
  425. struct siu_port *port_info = siu_ports[pdev->id];
  426. cancel_work_sync(&port_info->capture.work);
  427. cancel_work_sync(&port_info->playback.work);
  428. siu_free_port(port_info);
  429. dev_dbg(pcm->card->dev, "%s\n", __func__);
  430. }
  431. const struct snd_soc_component_driver siu_component = {
  432. .name = DRV_NAME,
  433. .open = siu_pcm_open,
  434. .close = siu_pcm_close,
  435. .prepare = siu_pcm_prepare,
  436. .trigger = siu_pcm_trigger,
  437. .pointer = siu_pcm_pointer_dma,
  438. .pcm_construct = siu_pcm_new,
  439. .pcm_destruct = siu_pcm_free,
  440. .legacy_dai_naming = 1,
  441. };
  442. EXPORT_SYMBOL_GPL(siu_component);